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authorH.J. Lu <hjl.tools@gmail.com>2021-02-12 09:57:30 -0800
committerH.J. Lu <hjl.tools@gmail.com>2021-02-22 15:52:56 -0800
commit89de9d3958ff4e14f438c3f6800fac80901e2c2f (patch)
tree97313e7cba2d8bd385960ac8bf622804b24c638d /sysdeps/x86
parentb5be9ae77e3e266ed83f84f0bb29198d71211aa8 (diff)
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x86: Use x86/nptl/pthreaddef.h
1. Move sysdeps/i386/nptl/pthreaddef.h to sysdeps/x86/nptl/pthreaddef.h. 2. Remove sysdeps/x86_64/nptl/pthreaddef.h. Reviewed-by: DJ Delorie <dj@redhat.com>
Diffstat (limited to 'sysdeps/x86')
-rw-r--r--sysdeps/x86/nptl/pthreaddef.h49
1 files changed, 49 insertions, 0 deletions
diff --git a/sysdeps/x86/nptl/pthreaddef.h b/sysdeps/x86/nptl/pthreaddef.h
new file mode 100644
index 0000000000..6ff7d601eb
--- /dev/null
+++ b/sysdeps/x86/nptl/pthreaddef.h
@@ -0,0 +1,49 @@
+/* Copyright (C) 2002-2021 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+/* Default stack size. */
+#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024)
+
+/* Minimum guard size. */
+#define ARCH_MIN_GUARD_SIZE 0
+
+/* Required stack pointer alignment at beginning. SSE requires 16
+ bytes. */
+#define STACK_ALIGN 16
+
+/* Minimal stack size after allocating thread descriptor and guard size. */
+#define MINIMAL_REST_STACK 2048
+
+/* Alignment requirement for TCB.
+
+ Some processors such as Intel Atom pay a big penalty on every
+ access using a segment override if that segment's base is not
+ aligned to the size of a cache line. (See Intel 64 and IA-32
+ Architectures Optimization Reference Manual, section 13.3.3.3,
+ "Segment Base".) On such machines, a cache line is 64 bytes. */
+#define TCB_ALIGNMENT 64
+
+
+/* Location of current stack frame. */
+#ifdef __x86_64__
+/* The frame pointer is not usable. */
+# define CURRENT_STACK_FRAME \
+ ({ register char *frame __asm__("rsp"); frame; })
+#else
+# define CURRENT_STACK_FRAME __builtin_frame_address (0)
+#endif