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authorAndrew Senkevich <andrew.senkevich@intel.com>2015-06-17 15:38:29 +0300
committerAndrew Senkevich <andrew.senkevich@intel.com>2015-06-17 15:38:29 +0300
commit6af25acc7b6313fd8934c3b2f0eb3da5a1c6eb6b (patch)
tree6b667fc73a74f97c43853ce2ffd7b090321412df /sysdeps/x86/fpu/bits
parentc71c89e5c72baf43fd44d08dda8ab846eec5b1d6 (diff)
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Vector log for x86_64 and tests.
Here is implementation of vectorized log containing SSE, AVX, AVX2 and AVX512 versions according to Vector ABI <https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>. * bits/libm-simd-decl-stubs.h: Added stubs for log. * math/bits/mathcalls.h: Added log declaration with __MATHCALL_VEC. * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added. * sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm redirections for log. * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files. * sysdeps/x86_64/fpu/Versions: New versions added. * sysdeps/x86_64/fpu/libm-test-ulps: Regenerated. * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added build of SSE, AVX2 and AVX512 IFUNC versions. * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S: New file. * sysdeps/x86_64/fpu/svml_d_log2_core.S: New file. * sysdeps/x86_64/fpu/svml_d_log4_core.S: New file. * sysdeps/x86_64/fpu/svml_d_log4_core_avx.S: New file. * sysdeps/x86_64/fpu/svml_d_log8_core.S: New file. * sysdeps/x86_64/fpu/svml_d_log_data.S: New file. * sysdeps/x86_64/fpu/svml_d_log_data.h: New file. * sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector log test. * sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise. * NEWS: Mention addition of x86_64 vector log.
Diffstat (limited to 'sysdeps/x86/fpu/bits')
-rw-r--r--sysdeps/x86/fpu/bits/math-vector.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h
index 2b739c5444..ed85622560 100644
--- a/sysdeps/x86/fpu/bits/math-vector.h
+++ b/sysdeps/x86/fpu/bits/math-vector.h
@@ -36,5 +36,17 @@
# define __DECL_SIMD_sin __DECL_SIMD_x86_64
# undef __DECL_SIMD_sinf
# define __DECL_SIMD_sinf __DECL_SIMD_x86_64
+# undef __DECL_SIMD_log
+# define __DECL_SIMD_log __DECL_SIMD_x86_64
+
+/* Workaround to exclude unnecessary symbol aliases in libmvec
+ while GCC creates the vector names based on scalar asm name.
+ Corresponding discussion started at
+ <https://gcc.gnu.org/ml/gcc/2015-06/msg00173.html>. */
+__asm__ ("_ZGVbN2v___log_finite = _ZGVbN2v_log");
+__asm__ ("_ZGVcN4v___log_finite = _ZGVcN4v_log");
+__asm__ ("_ZGVdN4v___log_finite = _ZGVdN4v_log");
+__asm__ ("_ZGVeN8v___log_finite = _ZGVeN8v_log");
+
# endif
#endif