Update.

1999-10-10  Ulrich Drepper  <drepper@cygnus.com>

	* sysdeps/powerpc/sysdep.h: New file.
	* sysdeps/unix/powerpc/sysdep.h: New file.
	* sysdeps/unix/sysv/linux/powerpc/sysdep.h: Include
	sysdeps/unix/powerpc/sysdep.h, not sysdeps/unix/sysdep.h.
	* sysdeps/powerpc/fpu/s_copysign.S: Use symbolic names for registers
	instead of bare numbers.
	* sysdeps/powerpc/fpu/s_fabs.S: Likewise.
	* sysdeps/powerpc/fpu/s_fmax.S: Likewise.
	* sysdeps/powerpc/fpu/s_fmin.S: Likewise.

	* sysdeps/hppa/sysdep.h: New file.

5 files changed, 123 insertions, 20 deletions

diff --git a/sysdeps/powerpc/fpu/s_copysign.S b/sysdeps/powerpc/fpu/s_copysign.S
index 0f27fef809..f7a412db3c 100644
--- a/sysdeps/powerpc/fpu/s_copysign.S
+++ b/sysdeps/powerpc/fpu/s_copysign.S
@@ -26,15 +26,15 @@ ENTRY(__copysign)
 /* double [f1] copysign (double [f1] x, double [f2] y);
    copysign(x,y) returns a value with the magnitude of x and
    with the sign bit of y.  */
-	stwu	1,-16(1)
-	stfd	2,8(1)
-	lwz	3,8(1)
-	cmpwi   3,0
-	addi    1,1,16
+	stwu	r1,-16(r1)
+	stfd	f2,8(r1)
+	lwz	r3,8(r1)
+	cmpwi   r3,0
+	addi    r1,r1,16
 	blt     0f
-	fabs    1,1
+	fabs    f1,f1
 	blr
-0:	fnabs   1,1
+0:	fnabs   f1,f1
 	blr
 	END (__copysign)
 
diff --git a/sysdeps/powerpc/fpu/s_fabs.S b/sysdeps/powerpc/fpu/s_fabs.S
index ec0bdb461f..f152079e0a 100644
--- a/sysdeps/powerpc/fpu/s_fabs.S
+++ b/sysdeps/powerpc/fpu/s_fabs.S
@@ -21,7 +21,7 @@
 
 ENTRY(__fabs)
 /* double [f1] fabs (double [f1] x); */
-	fabs 1,1
+	fabs f1,f1
 	blr
 END(__fabs)
 
diff --git a/sysdeps/powerpc/fpu/s_fmax.S b/sysdeps/powerpc/fpu/s_fmax.S
index d5373d7bb1..3721db4c94 100644
--- a/sysdeps/powerpc/fpu/s_fmax.S
+++ b/sysdeps/powerpc/fpu/s_fmax.S
@@ -21,13 +21,13 @@
 
 ENTRY(__fmax)
 /* double [f1] fmax (double [f1] x, double [f2] y); */
-	fcmpu	0,1,2
-	blt	0,0f		/* if x < y, neither x nor y can be NaN... */
-	bnulr+	0
+	fcmpu	cr0,f1,f2
+	blt	cr0,0f		/* if x < y, neither x nor y can be NaN... */
+	bnulr+	cr0
 /* x and y are unordered, so one of x or y must be a NaN... */
-	fcmpu	1,2,2
-	bunlr	1
-0:	fmr	1,2
+	fcmpu	cr1,f2,f2
+	bunlr	cr1
+0:	fmr	f1,f2
 	blr
 END(__fmax)
 
diff --git a/sysdeps/powerpc/fpu/s_fmin.S b/sysdeps/powerpc/fpu/s_fmin.S
index 919ceb113b..384995f847 100644
--- a/sysdeps/powerpc/fpu/s_fmin.S
+++ b/sysdeps/powerpc/fpu/s_fmin.S
@@ -21,13 +21,13 @@
 
 ENTRY(__fmin)
 /* double [f1] fmin (double [f1] x, double [f2] y); */
-	fcmpu	0,1,2
-	bgt	0,0f		/* if x > y, neither x nor y can be NaN... */
-	bnulr+	0
+	fcmpu	cr0,f1,f2
+	bgt	cr0,0f		/* if x > y, neither x nor y can be NaN... */
+	bnulr+	cr0
 /* x and y are unordered, so one of x or y must be a NaN... */
-	fcmpu	1,2,2
-	bunlr	1
-0:	fmr	1,2
+	fcmpu	cr1,f2,f2
+	bunlr	cr1
+0:	fmr	f1,f2
 	blr
 END(__fmin)
 
diff --git a/sysdeps/powerpc/sysdep.h b/sysdeps/powerpc/sysdep.h
new file mode 100644
index 0000000000..785c52a8a9
--- /dev/null
+++ b/sysdeps/powerpc/sysdep.h
@@ -0,0 +1,103 @@
+/* Copyright (C) 1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If not,
+   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifdef __ASSEMBLER__
+
+/* Symbolic names for the registers.  The only portable way to write asm
+   code is to use number but this produces really unreadable code.
+   Therefore these symbolic names.  */
+
+/* Integer registers.  */
+#define r0	0
+#define r1	1
+#define r2	2
+#define r3	3
+#define r4	4
+#define r5	5
+#define r6	6
+#define r7	7
+#define r8	8
+#define r9	9
+#define r10	10
+#define r11	11
+#define r12	12
+#define r13	13
+#define r14	14
+#define r15	15
+#define r16	16
+#define r17	17
+#define r18	18
+#define r19	19
+#define r20	20
+#define r21	21
+#define r22	22
+#define r23	23
+#define r24	24
+#define r25	25
+#define r26	26
+#define r27	27
+#define r28	28
+#define r29	29
+#define r30	30
+#define r31	31
+
+/* Floating-point registers.  */
+#define fp0	0
+#define fp1	1
+#define fp2	2
+#define fp3	3
+#define fp4	4
+#define fp5	5
+#define fp6	6
+#define fp7	7
+#define fp8	8
+#define fp9	9
+#define fp10	10
+#define fp11	11
+#define fp12	12
+#define fp13	13
+#define fp14	14
+#define fp15	15
+#define fp16	16
+#define fp17	17
+#define fp18	18
+#define fp19	19
+#define fp20	20
+#define fp21	21
+#define fp22	22
+#define fp23	23
+#define fp24	24
+#define fp25	25
+#define fp26	26
+#define fp27	27
+#define fp28	28
+#define fp29	29
+#define fp30	30
+#define fp31	31
+
+/* Condition code registers.  */
+#define cr0	0
+#define cr1	1
+#define cr2	2
+#define cr3	3
+#define cr4	4
+#define cr5	5
+#define cr6	6
+#define cr7	7
+
+#endif /* assembler */