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| author | Ulrich Drepper <drepper@redhat.com> | 2006-08-14 23:11:18 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2006-08-14 23:11:18 +0000 |
| commit | f17efcb43e500d4af62b71bd6f286af831069b5a (patch) | |
| tree | bf062a11f158b5bc8e33e42cc85e625751bacf94 /sysdeps/powerpc | |
| parent | 107b8a922a9f72bae8d066549c675062bee0897f (diff) | |
| download | glibc-f17efcb43e500d4af62b71bd6f286af831069b5a.tar glibc-f17efcb43e500d4af62b71bd6f286af831069b5a.tar.gz glibc-f17efcb43e500d4af62b71bd6f286af831069b5a.tar.bz2 glibc-f17efcb43e500d4af62b71bd6f286af831069b5a.zip | |
* sysdeps/powerpc/powerpc32/dl-trampoline.S (_dl_runtime_resolve):
Don't clobber caller's LRSAVE.
(_dl_prof_resolve): Likewise.
Diffstat (limited to 'sysdeps/powerpc')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/dl-trampoline.S | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/sysdeps/powerpc/powerpc32/dl-trampoline.S b/sysdeps/powerpc/powerpc32/dl-trampoline.S index 392c109d4c..6a158c3fff 100644 --- a/sysdeps/powerpc/powerpc32/dl-trampoline.S +++ b/sysdeps/powerpc/powerpc32/dl-trampoline.S @@ -40,8 +40,9 @@ _dl_runtime_resolve: mflr r0 # We also need to save some of the condition register fields stw r7,32(r1) - stw r0,68(r1) - cfi_offset (lr, 4) + # Don't clobber the caller's LRSAVE, it is needed by _mcount. + stw r0,48(r1) + cfi_offset (lr, -16) stw r8,36(r1) mfcr r0 stw r9,40(r1) @@ -51,7 +52,7 @@ _dl_runtime_resolve: # 'fixup' returns the address we want to branch to. mtctr r3 # Put the registers back... - lwz r0,68(r1) + lwz r0,48(r1) lwz r10,44(r1) lwz r9,40(r1) mtlr r0 @@ -128,8 +129,9 @@ _dl_prof_resolve: mflr r5 # We also need to save some of the condition register fields. stw r7,32(r1) - stw r5,324(r1) - cfi_offset (lr, 4) + # Don't clobber the caller's LRSAVE, it is needed by _mcount. + stw r5,308(r1) + cfi_offset (lr, -12) stw r8,36(r1) mfcr r0 stw r9,40(r1) @@ -154,7 +156,7 @@ _dl_prof_resolve: # 'fixup' returns the address we want to branch to. mtctr r3 # Put the registers back... - lwz r0,324(r1) + lwz r0,308(r1) lwz r10,44(r1) lwz r9,40(r1) mtlr r0 |