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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-03-29 19:16:34 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-03-29 19:16:34 -0500 |
| commit | 10cce66930b3dc0405106bbb62a6d44602bec118 (patch) | |
| tree | c14098d79a790964bacb4ba50faa00d8f63ac00e /sysdeps/powerpc/fpu | |
| parent | 225d94459b3f713e56d4a5abe79d28e33d3fd114 (diff) | |
| download | glibc-10cce66930b3dc0405106bbb62a6d44602bec118.tar glibc-10cce66930b3dc0405106bbb62a6d44602bec118.tar.gz glibc-10cce66930b3dc0405106bbb62a6d44602bec118.tar.bz2 glibc-10cce66930b3dc0405106bbb62a6d44602bec118.zip | |
[powerpc] Use __builtin_{mffs,mtfsf}
Replace inline asm uses of the "mffs" and "mtfsf" instructions with
the analogous GCC builtins.
__builtin_mffs and __builtin_mtfsf are both available in GCC 5 and above.
Given the minimum GCC level for GLibC is now GCC 6.2, it is safe to use
these builtins without restriction.
2019-03-29 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_register): Replace inline
asm with builtin.
* sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h (FP_INIT_ROUNDMODE):
Likewise.
* sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_GET_DI_FPSCR): Likewise.
(_GET_SI_FPSCR): Likewise.
(_SET_SI_FPSCR): Likewise.
Diffstat (limited to 'sysdeps/powerpc/fpu')
| -rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 5 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/tst-setcontext-fpscr.c | 10 |
2 files changed, 5 insertions, 10 deletions
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 67a9c9a51a..8a0bace84d 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -32,8 +32,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Equivalent to fegetenv, but returns a fenv_t instead of taking a pointer. */ -#define fegetenv_register() \ - ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; }) +#define fegetenv_register() __builtin_mffs() /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */ #define fesetenv_register(env) \ @@ -45,7 +44,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; "mtfsf 0xff,%0,1,0; " \ ".machine pop" : : "f" (d)); \ else \ - asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \ + __builtin_mtfsf (0xff, d); \ } while(0) /* This very handy macro: diff --git a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c index 958afffc0b..7dfd5a9e74 100644 --- a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c +++ b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c @@ -97,9 +97,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); /* Macros for accessing the hardware control word on Power6[x]. */ #define _GET_DI_FPSCR(__fpscr) \ ({union { double d; di_fpscr_t fpscr; } u; \ - register double fr; \ - __asm__ ("mffs %0" : "=f" (fr)); \ - u.d = fr; \ + u.d = __builtin_mffs (); \ (__fpscr) = u.fpscr; \ u.fpscr; \ }) @@ -121,9 +119,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); # define _GET_SI_FPSCR(__fpscr) \ ({union { double d; di_fpscr_t fpscr; } u; \ - register double fr; \ - __asm__ ("mffs %0" : "=f" (fr)); \ - u.d = fr; \ + u.d = __builtin_mffs (); \ (__fpscr) = (si_fpscr_t) u.fpscr; \ (si_fpscr_t) u.fpscr; \ }) @@ -137,7 +133,7 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__))); u.fpscr = 0xfff80000ULL << 32; \ u.fpscr |= __fpscr & 0xffffffffULL; \ fr = u.d; \ - __asm__ ("mtfsf 255,%0" : : "f" (fr)); \ + __builtin_mtfsf (255, fr); \ fr = 0.0; \ } |