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author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2013-11-13 06:45:19 -0600 |
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committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2013-11-13 06:45:19 -0600 |
commit | 7a2ad8cf392acfcaef319e722dda9101d4d8b6bd (patch) | |
tree | c525169182b6b1d21663865c26224974f4541aa1 /sysdeps/powerpc/bits/fenv.h | |
parent | 50727aa76b42c3b989a8c0612eb7f63e29aa7fec (diff) | |
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PowerPC: Fix __fe_mask_env export
This patch does not export __fe_mask_env anymore, only providing a
compatibility symbol. It fixes BZ#14143.
Diffstat (limited to 'sysdeps/powerpc/bits/fenv.h')
-rw-r--r-- | sysdeps/powerpc/bits/fenv.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/sysdeps/powerpc/bits/fenv.h b/sysdeps/powerpc/bits/fenv.h index 122edd3dc3..86bf94e8fd 100644 --- a/sysdeps/powerpc/bits/fenv.h +++ b/sysdeps/powerpc/bits/fenv.h @@ -153,15 +153,12 @@ extern const fenv_t __fe_enabled_env; extern const fenv_t __fe_nonieee_env; # define FE_NONIEEE_ENV (&__fe_nonieee_env) -__BEGIN_DECLS - /* Floating-point environment with all exceptions enabled. Note that just evaluating this value does not change the processor exception mode. Passing this mask to fesetenv will result in a prctl syscall to change the MSR FE0/FE1 bits to "Precise Mode". On some processors this will result in slower floating point execution. This will last until an fenv or exception mask is installed that disables all FP exceptions. */ -extern const fenv_t *__fe_nomask_env (void); # define FE_NOMASK_ENV FE_ENABLED_ENV /* Floating-point environment with all exceptions disabled. Note that @@ -169,9 +166,6 @@ extern const fenv_t *__fe_nomask_env (void); Passing this mask to fesetenv will result in a prctl syscall to change the MSR FE0/FE1 bits to "Ignore Exceptions Mode". On most processors this allows the fastest possible floating point execution.*/ -extern const fenv_t *__fe_mask_env (void); # define FE_MASK_ENV FE_DFL_ENV -__END_DECLS - #endif |