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author | Alexandre Oliva <aoliva@redhat.com> | 2003-03-21 21:39:39 +0000 |
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committer | Alexandre Oliva <aoliva@redhat.com> | 2003-03-21 21:39:39 +0000 |
commit | 8f9fb0000e345b16902311b2d265f83b329e69c5 (patch) | |
tree | 1c095c4ab887f251889e9fc001d38272d3bce5e0 /sysdeps/mips/memset.S | |
parent | 88b3f3ede294499cef1cb36cc6a5f4662d205e9d (diff) | |
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* sysdeps/mips/mips64/memcpy.S: Fix porting bug that broke unaligned copying of 8-15 bytes. From Chris Demetriou <cgd@broadcom.com>. Fix label names. * sysdeps/mips/mips64/memset.S: Fix label names. Make similar change as to memcpy.S. * sysdeps/mips/memcpy.S: Formatting changes. * sysdeps/mips/memset.S: Likewise.
2003-03-21 Alexandre Oliva <aoliva@redhat.com>
* sysdeps/mips/mips64/memcpy.S: Fix porting bug that broke
unaligned copying of 8-15 bytes. From Chris Demetriou
<cgd@broadcom.com>. Fix label names.
* sysdeps/mips/mips64/memset.S: Fix label names. Make similar
change as to memcpy.S.
* sysdeps/mips/memcpy.S: Formatting changes.
* sysdeps/mips/memset.S: Likewise.
Diffstat (limited to 'sysdeps/mips/memset.S')
-rw-r--r-- | sysdeps/mips/memset.S | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/sysdeps/mips/memset.S b/sysdeps/mips/memset.S index b372d292f2..f120123544 100644 --- a/sysdeps/mips/memset.S +++ b/sysdeps/mips/memset.S @@ -43,35 +43,42 @@ ENTRY (memset) sll t0, a1, 16 or a1, t0 # a1 is now pattern in full word -L(ueven): subu t0, zero, a0 # Unaligned address? +L(ueven): + subu t0, zero, a0 # Unaligned address? andi t0, 0x3 beq t0, zero, L(chkw) subu a2, t0 SWHI a1, 0(a0) # Yes, handle first unaligned part addu a0, t0 # Now both a0 and a2 are updated -L(chkw): andi t0, a2, 0x7 # Enough left for one loop iteration? +L(chkw): + andi t0, a2, 0x7 # Enough left for one loop iteration? beq t0, a2, L(chkl) subu a3, a2, t0 addu a3, a0 # a3 is last loop address +1 move a2, t0 # a2 is now # of bytes left after loop -L(loopw): addiu a0, 8 # Handle 2 words pr. iteration +L(loopw): + addiu a0, 8 # Handle 2 words pr. iteration sw a1, -8(a0) bne a0, a3, L(loopw) sw a1, -4(a0) -L(chkl): andi t0, a2, 0x4 # Check if there is at least a full +L(chkl): + andi t0, a2, 0x4 # Check if there is at least a full beq t0, zero, L(last8) # word remaining after the loop subu a2, t0 sw a1, 0(a0) # Yes... addiu a0, 4 -L(last8): blez a2, L(exit) # Handle last 8 bytes (if cnt>0) +L(last8): + blez a2, L(exit) # Handle last 8 bytes (if cnt>0) addu a3, a2, a0 # a3 is last address +1 -L(lst8l): addiu a0, 1 +L(lst8l): + addiu a0, 1 bne a0, a3, L(lst8l) sb a1, -1(a0) -L(exit): j ra # Bye, bye +L(exit): + j ra # Bye, bye nop .set reorder |