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author | Torvald Riegel <triegel@redhat.com> | 2014-10-18 01:02:59 +0200 |
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committer | Torvald Riegel <triegel@redhat.com> | 2014-11-20 11:57:38 +0100 |
commit | 1ea339b69725cb2f30b5a84cb7ca96111c9a637b (patch) | |
tree | 130609da9190b04afb366f3a506d3415ea2f982f /sysdeps/microblaze/bits | |
parent | d960211ff52a6ab632eace2f905c4898f187df9e (diff) | |
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Add arch-specific configuration for C11 atomics support.
This sets __HAVE_64B_ATOMICS if provided. It also sets
USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the
__atomic* builtins (aarch64, mips partially) or if this has been
tested (x86_64); otherwise, this is set to false so that C11 atomics will
be based on the existing atomic operations.
Diffstat (limited to 'sysdeps/microblaze/bits')
-rw-r--r-- | sysdeps/microblaze/bits/atomic.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sysdeps/microblaze/bits/atomic.h b/sysdeps/microblaze/bits/atomic.h index 77004a0284..395162df2d 100644 --- a/sysdeps/microblaze/bits/atomic.h +++ b/sysdeps/microblaze/bits/atomic.h @@ -35,6 +35,9 @@ typedef uintptr_t uatomicptr_t; typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; +#define __HAVE_64B_ATOMICS 1 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + /* Microblaze does not have byte and halfword forms of load and reserve and store conditional. So for microblaze we stub out the 8- and 16-bit forms. */ |