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| author | Ulrich Drepper <drepper@redhat.com> | 2010-11-05 07:57:46 -0400 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2010-11-05 07:57:46 -0400 |
| commit | c0dde15b5dba7e02ce6f36eab3a4d1c166f9951b (patch) | |
| tree | ba46149312b4ab5e66771663289e3754bcc45d84 /sysdeps/i386 | |
| parent | 0e516e0e14f2f9783a21cd1727bc53776341f857 (diff) | |
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32bit memset-sse2.S fails with uneven cache size
32bit memset-sse2.S assumes cache size is multiple of 128 bytes. If
it isn't true, memset-sse2.S will fail. For example, a processor can
have 24576 KB L3 cache and 20 cores. That is 2516582 byte per core. Half
of it is 1258291, which isn't helpful for vector instructions. This
patch rounds cache sizes to multiple of 256 bytes and adds "raw" cache
sizes.
Diffstat (limited to 'sysdeps/i386')
| -rw-r--r-- | sysdeps/i386/i686/cacheinfo.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sysdeps/i386/i686/cacheinfo.c b/sysdeps/i386/i686/cacheinfo.c index f8b7f521ca..3635961727 100644 --- a/sysdeps/i386/i686/cacheinfo.c +++ b/sysdeps/i386/i686/cacheinfo.c @@ -1,7 +1,11 @@ #define __x86_64_data_cache_size __x86_data_cache_size +#define __x86_64_raw_data_cache_size __x86_raw_data_cache_size #define __x86_64_data_cache_size_half __x86_data_cache_size_half +#define __x86_64_raw_data_cache_size_half __x86_raw_data_cache_size_half #define __x86_64_shared_cache_size __x86_shared_cache_size +#define __x86_64_raw_shared_cache_size __x86_raw_shared_cache_size #define __x86_64_shared_cache_size_half __x86_shared_cache_size_half +#define __x86_64_raw_shared_cache_size_half __x86_raw_shared_cache_size_half #define DISABLE_PREFETCHW #define DISABLE_PREFERRED_MEMORY_INSTRUCTION |