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| author | Uros Bizjak <ubizjak@gmail.com> | 2019-04-01 15:58:37 +0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-04-01 16:00:37 +0700 |
| commit | 993e3107af67edefcfc79a62ae55f7b98aa5151e (patch) | |
| tree | 449aa8a58d1397aeb3d39b7fb106f0821ef1ef85 /sysdeps/alpha/divqu.S | |
| parent | d5ecee822e72a2fd156338ab2be2f2e70a1da55a (diff) | |
| download | glibc-993e3107af67edefcfc79a62ae55f7b98aa5151e.tar glibc-993e3107af67edefcfc79a62ae55f7b98aa5151e.tar.gz glibc-993e3107af67edefcfc79a62ae55f7b98aa5151e.tar.bz2 glibc-993e3107af67edefcfc79a62ae55f7b98aa5151e.zip | |
alpha: Improve sysdeps/alpha/divqu.S and sysdeps/alpha/remqu.S
* sysdeps/alpha/divqu.S (__divqu): Move save of $f0 and excb after
conditional branch to DIVBYZERO. Fix unwind info.
* sysdeps/alpha/remqu.S (__remqu): Move saves of $f0, $f1, $f2 and
excb after conditional branch to $powerof2. Add missing unop
instructions and .align directives and reorder instructions to
match __divqu.
Signed-off-by: Uroš Bizjak <ubizjak@gmail.com>
Diffstat (limited to 'sysdeps/alpha/divqu.S')
| -rw-r--r-- | sysdeps/alpha/divqu.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/sysdeps/alpha/divqu.S b/sysdeps/alpha/divqu.S index f5cedd0716..3165374b6d 100644 --- a/sysdeps/alpha/divqu.S +++ b/sysdeps/alpha/divqu.S @@ -56,10 +56,10 @@ __divqu: that's done, we have at least 22 cycles until its results are ready -- all the time in the world to figure out how we're going to use the results. */ - stt $f0, 0(sp) - excb beq Y, DIVBYZERO + stt $f0, 0(sp) + excb stt $f1, 8(sp) stt $f3, 48(sp) cfi_rel_offset ($f0, 0) @@ -70,6 +70,7 @@ __divqu: _ITOFT2 X, $f0, 16, Y, $f1, 24 cvtqt $f0, $f0 cvtqt $f1, $f1 + blt X, $x_is_neg divt/c $f0, $f1, $f0 @@ -90,12 +91,12 @@ __divqu: ldt $f0, 0(sp) ldt $f3, 48(sp) + lda sp, FRAME(sp) cfi_remember_state cfi_restore ($f0) cfi_restore ($f1) cfi_restore ($f3) cfi_def_cfa_offset (0) - lda sp, FRAME(sp) ret $31, (RA), 1 .align 4 |