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| author | Harsha Jagasia <harsha.jagasia@amd.com> | 2011-03-04 23:30:08 -0500 |
|---|---|---|
| committer | Ulrich Drepper <drepper@gmail.com> | 2011-03-04 23:30:08 -0500 |
| commit | 7e4ba49cd365555ddaff2ae8bba7b912464ad6e5 (patch) | |
| tree | ec4eaf0ea436e74b584daefdceeb4ab66c52728d /nptl/tst-rwlock11.c | |
| parent | 13a804de8f3091e8ccd9b650f61becd6e1304227 (diff) | |
| download | glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar.gz glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar.bz2 glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.zip | |
Enable SSE2 memset for AMD'supcoming Orochi processor.
This patch enables SSE2 memset for AMD's upcoming Orochi processor.
This patch also fixes the following bug:
For misaligned blocks larger than > 144 Bytes, memset branches into
the integer code path depending on the value of misalignment even if
the startup code chooses the SSE2 code path upfront, when multiarch
is enabled.
Diffstat (limited to 'nptl/tst-rwlock11.c')
0 files changed, 0 insertions, 0 deletions