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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2021-07-15 08:52:44 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2021-07-19 14:12:29 -0300 |
| commit | 469761eac842663365bba3dacd4cdf15a2ae328d (patch) | |
| tree | 570826e6942f9bc0bb7eec6bb34dedec141e0d01 /manual/platform.texi | |
| parent | 5adb0e14a5cc9e011e58a7aaf193b598ecbd7b07 (diff) | |
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elf: Fix tst-cpu-features-cpuinfo on some AMD systems (BZ #28090)
The SSBD feature is implemented in 2 different ways on AMD processors:
newer systems (Zen3) provides AMD_SSBD (function 8000_0008, EBX[24]),
while older system provides AMD_VIRT_SSBD (function 8000_0008, EBX[25]).
However for AMD_VIRT_SSBD, kernel shows both 'ssdb' and 'virt_ssdb' on
/proc/cpuinfo; while for AMD_SSBD only 'ssdb' is provided.
This now check is AMD_SSBD is set to check for 'ssbd', otherwise check
if AMD_VIRT_SSDB is set to check for 'virt_ssbd'.
Checked on x86_64-linux-gnu on a Ryzen 9 5900x.
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Diffstat (limited to 'manual/platform.texi')
| -rw-r--r-- | manual/platform.texi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/manual/platform.texi b/manual/platform.texi index 037dfc4f20..c56ba7d413 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -190,6 +190,9 @@ The supported processor features are: @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus. @item +@code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems). + +@item @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers. @item |