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| author | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:17:51 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:18:10 -0700 |
| commit | a3d9ab5070b56b49aa91be2887fa5b118012b2cd (patch) | |
| tree | 4352143efb08c51ec9cb480489e847de724afb06 /malloc/arena.c | |
| parent | 83569fb894050db7430047da2219ca50c68f882a (diff) | |
| download | glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.gz glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.bz2 glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.zip | |
Limit threads sharing L2 cache to 2 for SLM/KNL
Silvermont and Knights Landing have a modular system design with two cores
sharing an L2 cache. If more than 2 cores are detected to shared L2 cache,
it should be adjusted for Silvermont and Knights Landing.
[BZ #18185]
* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
sharing L2 cache to 2 for Silvermont/Knights Landing.
Diffstat (limited to 'malloc/arena.c')
0 files changed, 0 insertions, 0 deletions