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author | Zack Weinberg <zackw@panix.com> | 2017-06-08 15:39:03 -0400 |
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committer | Zack Weinberg <zackw@panix.com> | 2017-06-08 15:39:03 -0400 |
commit | 5046dbb4a7eba5eccfd258f92f4735c9ffc8d069 (patch) | |
tree | 4470480d904b65cf14ca524f96f79eca818c3eaf /REORG.TODO/sysdeps/x86_64/fpu | |
parent | 199fc19d3aaaf57944ef036e15904febe877fc93 (diff) | |
download | glibc-5046dbb4a7eba5eccfd258f92f4735c9ffc8d069.tar glibc-5046dbb4a7eba5eccfd258f92f4735c9ffc8d069.tar.gz glibc-5046dbb4a7eba5eccfd258f92f4735c9ffc8d069.tar.bz2 glibc-5046dbb4a7eba5eccfd258f92f4735c9ffc8d069.zip |
Prepare for radical source tree reorganization.zack/build-layout-experiment
All top-level files and directories are moved into a temporary storage
directory, REORG.TODO, except for files that will certainly still
exist in their current form at top level when we're done (COPYING,
COPYING.LIB, LICENSES, NEWS, README), all old ChangeLog files (which
are moved to the new directory OldChangeLogs, instead), and the
generated file INSTALL (which is just deleted; in the new order, there
will be no generated files checked into version control).
Diffstat (limited to 'REORG.TODO/sysdeps/x86_64/fpu')
337 files changed, 39845 insertions, 0 deletions
diff --git a/REORG.TODO/sysdeps/x86_64/fpu/Implies b/REORG.TODO/sysdeps/x86_64/fpu/Implies new file mode 100644 index 0000000000..2b745a34fb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/Implies @@ -0,0 +1 @@ +x86/fpu diff --git a/REORG.TODO/sysdeps/x86_64/fpu/Makefile b/REORG.TODO/sysdeps/x86_64/fpu/Makefile new file mode 100644 index 0000000000..2b7d69bb50 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/Makefile @@ -0,0 +1,239 @@ +ifeq ($(subdir),mathvec) +libmvec-support += svml_d_cos2_core svml_d_cos4_core_avx \ + svml_d_cos4_core svml_d_cos8_core \ + svml_d_sin2_core svml_d_sin4_core_avx \ + svml_d_sin4_core svml_d_sin8_core svml_d_trig_data \ + svml_s_cosf4_core svml_s_cosf8_core_avx \ + svml_s_cosf8_core svml_s_cosf16_core svml_s_trig_data \ + svml_s_sinf4_core svml_s_sinf8_core_avx \ + svml_s_sinf8_core svml_s_sinf16_core \ + svml_d_sincos2_core svml_d_sincos4_core_avx \ + svml_d_sincos4_core svml_d_sincos8_core \ + svml_d_log2_core svml_d_log4_core_avx svml_d_log4_core \ + svml_d_log8_core svml_d_log_data svml_s_logf4_core \ + svml_s_logf8_core_avx svml_s_logf8_core svml_s_logf16_core \ + svml_s_logf_data svml_d_exp2_core svml_d_exp4_core_avx \ + svml_d_exp4_core svml_d_exp8_core svml_d_exp_data \ + svml_s_expf4_core svml_s_expf8_core_avx svml_s_expf8_core \ + svml_s_expf16_core svml_s_expf_data svml_d_pow2_core \ + svml_d_pow4_core_avx svml_d_pow4_core svml_d_pow8_core \ + svml_d_pow_data svml_s_powf4_core svml_s_powf8_core_avx \ + svml_s_powf8_core svml_s_powf16_core svml_s_powf_data \ + svml_s_sincosf4_core svml_s_sincosf8_core_avx \ + svml_s_sincosf8_core svml_s_sincosf16_core svml_finite_alias + +libmvec-static-only-routines = svml_finite_alias +endif + +# Variables for libmvec tests. +ifeq ($(subdir),math) +ifeq ($(build-mathvec),yes) +libmvec-tests += double-vlen2 double-vlen4 double-vlen4-avx2 \ + float-vlen4 float-vlen8 float-vlen8-avx2 +tests += test-double-libmvec-alias test-double-libmvec-alias-avx \ + test-double-libmvec-alias-avx2 test-double-libmvec-alias-main \ + test-double-libmvec-alias-avx-main test-double-libmvec-alias-avx2-main \ + test-float-libmvec-alias test-float-libmvec-alias-avx \ + test-float-libmvec-alias-avx2 test-float-libmvec-alias-main \ + test-float-libmvec-alias-avx-main test-float-libmvec-alias-avx2-main \ + test-double-libmvec-sincos test-double-libmvec-sincos-avx \ + test-double-libmvec-sincos-avx2 test-float-libmvec-sincosf \ + test-float-libmvec-sincosf-avx test-float-libmvec-sincosf-avx2 +modules-names += test-double-libmvec-alias-mod \ + test-double-libmvec-alias-avx-mod \ + test-double-libmvec-alias-avx2-mod \ + test-float-libmvec-alias-mod \ + test-float-libmvec-alias-avx-mod \ + test-float-libmvec-alias-avx2-mod +modules-names-tests += test-double-libmvec-alias-mod \ + test-double-libmvec-alias-avx-mod \ + test-double-libmvec-alias-avx2-mod \ + test-float-libmvec-alias-mod \ + test-float-libmvec-alias-avx-mod \ + test-float-libmvec-alias-avx2-mod +extra-test-objs += test-double-libmvec-sincos-avx-main.o \ + test-double-libmvec-sincos-avx2-main.o \ + test-double-libmvec-sincos-main.o \ + test-float-libmvec-sincosf-avx-main.o \ + test-float-libmvec-sincosf-avx2-main.o\ + test-float-libmvec-sincosf-main.o +test-double-libmvec-alias-mod.so-no-z-defs = yes +test-double-libmvec-alias-avx-mod.so-no-z-defs = yes +test-double-libmvec-alias-avx2-mod.so-no-z-defs = yes +test-float-libmvec-alias-mod.so-no-z-defs = yes +test-float-libmvec-alias-avx-mod.so-no-z-defs = yes +test-float-libmvec-alias-avx2-mod.so-no-z-defs = yes + +$(objpfx)test-double-libmvec-alias: \ + $(objpfx)test-double-libmvec-alias-mod.so +$(objpfx)test-double-libmvec-alias-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-avx: \ + $(objpfx)test-double-libmvec-alias-avx-mod.so +$(objpfx)test-double-libmvec-alias-avx-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-avx2: \ + $(objpfx)test-double-libmvec-alias-avx2-mod.so +$(objpfx)test-double-libmvec-alias-avx2-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-main: \ + $(objpfx)test-double-libmvec-alias-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-avx-main: \ + $(objpfx)test-double-libmvec-alias-avx-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-avx2-main: \ + $(objpfx)test-double-libmvec-alias-avx2-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias: \ + $(objpfx)test-float-libmvec-alias-mod.so +$(objpfx)test-float-libmvec-alias-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx: \ + $(objpfx)test-float-libmvec-alias-avx-mod.so +$(objpfx)test-float-libmvec-alias-avx-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx2: \ + $(objpfx)test-float-libmvec-alias-avx2-mod.so +$(objpfx)test-float-libmvec-alias-avx2-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-main: \ + $(objpfx)test-float-libmvec-alias-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx-main: \ + $(objpfx)test-float-libmvec-alias-avx-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx2-main: \ + $(objpfx)test-float-libmvec-alias-avx2-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-sincos: \ + $(objpfx)test-double-libmvec-sincos.o \ + $(objpfx)test-double-libmvec-sincos-main.o $(libmvec) + +$(objpfx)test-double-libmvec-sincos-avx: \ + $(objpfx)test-double-libmvec-sincos-avx.o \ + $(objpfx)test-double-libmvec-sincos-avx-main.o $(libmvec) + +$(objpfx)test-double-libmvec-sincos-avx2: \ + $(objpfx)test-double-libmvec-sincos-avx2.o \ + $(objpfx)test-double-libmvec-sincos-avx2-main.o $(libmvec) + +$(objpfx)test-float-libmvec-sincosf: \ + $(objpfx)test-float-libmvec-sincosf.o \ + $(objpfx)test-float-libmvec-sincosf-main.o $(libmvec) + +$(objpfx)test-float-libmvec-sincosf-avx: \ + $(objpfx)test-float-libmvec-sincosf-avx.o \ + $(objpfx)test-float-libmvec-sincosf-avx-main.o $(libmvec) + +$(objpfx)test-float-libmvec-sincosf-avx2: \ + $(objpfx)test-float-libmvec-sincosf-avx2.o \ + $(objpfx)test-float-libmvec-sincosf-avx2-main.o $(libmvec) + +ifeq (yes,$(config-cflags-avx512)) +libmvec-tests += double-vlen8 float-vlen16 +tests += test-double-libmvec-alias-avx512 \ + test-float-libmvec-alias-avx512 \ + test-double-libmvec-alias-avx512-main \ + test-float-libmvec-alias-avx512-main \ + test-double-libmvec-sincos-avx512 \ + test-float-libmvec-sincosf-avx512 +modules-names += test-double-libmvec-alias-avx512-mod \ + test-float-libmvec-alias-avx512-mod +modules-names-tests += test-double-libmvec-alias-avx512-mod \ + test-float-libmvec-alias-avx512-mod +extra-test-objs += test-double-libmvec-sincos-avx512-main.o \ + test-float-libmvec-sincosf-avx512-main.o +test-double-libmvec-alias-avx512-mod.so-no-z-defs = yes +test-float-libmvec-alias-avx512-mod.so-no-z-defs = yes + +$(objpfx)test-double-libmvec-alias-avx512: \ + $(objpfx)test-double-libmvec-alias-avx512-mod.so +$(objpfx)test-double-libmvec-alias-avx512-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-alias-avx512-main: \ + $(objpfx)test-double-libmvec-alias-avx512-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx512: \ + $(objpfx)test-float-libmvec-alias-avx512-mod.so +$(objpfx)test-float-libmvec-alias-avx512-mod.so: \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-float-libmvec-alias-avx512-main: \ + $(objpfx)test-float-libmvec-alias-avx512-mod.os \ + $(objpfx)../mathvec/libmvec_nonshared.a $(libmvec) + +$(objpfx)test-double-libmvec-sincos-avx512: \ + $(objpfx)test-double-libmvec-sincos-avx512.o \ + $(objpfx)test-double-libmvec-sincos-avx512-main.o $(libmvec) + +$(objpfx)test-float-libmvec-sincosf-avx512: \ + $(objpfx)test-float-libmvec-sincosf-avx512.o \ + $(objpfx)test-float-libmvec-sincosf-avx512-main.o $(libmvec) +endif + +double-vlen2-funcs = cos exp log pow sin sincos +double-vlen4-funcs = cos exp log pow sin sincos +double-vlen4-avx2-funcs = cos exp log pow sin sincos +double-vlen8-funcs = cos exp log pow sin sincos +float-vlen4-funcs = cos exp log pow sin sincos +float-vlen8-funcs = cos exp log pow sin sincos +float-vlen8-avx2-funcs = cos exp log pow sin sincos +float-vlen16-funcs = cos exp log pow sin sincos + +double-vlen4-arch-ext-cflags = -mavx +double-vlen4-arch-ext2-cflags = -mavx2 +double-vlen8-arch-ext-cflags = -mavx512f + +float-vlen8-arch-ext-cflags = -mavx +float-vlen8-arch-ext2-cflags = -mavx2 +float-vlen16-arch-ext-cflags = -mavx512f + +libmvec-sincos-cflags = $(libm-test-fast-math-cflags) -fno-inline -fopenmp -Wno-unknown-pragmas +libmvec-alias-cflags = $(libmvec-sincos-cflags) -ffloat-store -ffinite-math-only + +CFLAGS-test-double-libmvec-alias-mod.c = $(libmvec-alias-cflags) +CFLAGS-test-double-libmvec-alias-avx-mod.c = $(double-vlen4-arch-ext-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX +CFLAGS-test-double-libmvec-alias-avx2-mod.c = $(double-vlen4-arch-ext2-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX2 +CFLAGS-test-double-libmvec-alias-avx512-mod.c = $(double-vlen8-arch-ext-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX512F + +CFLAGS-test-float-libmvec-alias-mod.c = $(libmvec-alias-cflags) +CFLAGS-test-float-libmvec-alias-avx-mod.c = $(double-vlen4-arch-ext-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX +CFLAGS-test-float-libmvec-alias-avx2-mod.c = $(double-vlen4-arch-ext2-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX2 +CFLAGS-test-float-libmvec-alias-avx512-mod.c = $(double-vlen8-arch-ext-cflags) $(libmvec-alias-cflags) -DREQUIRE_AVX512F + +CFLAGS-test-double-vlen4-avx2-wrappers.c = $(double-vlen4-arch-ext2-cflags) + +CFLAGS-test-float-vlen8-avx2-wrappers.c = $(float-vlen8-arch-ext2-cflags) + +CFLAGS-test-double-libmvec-sincos-main.c = $(libmvec-sincos-cflags) +CFLAGS-test-double-libmvec-sincos-avx.c = -DREQUIRE_AVX +CFLAGS-test-double-libmvec-sincos-avx-main.c = $(libmvec-sincos-cflags) $(double-vlen4-arch-ext-cflags) +CFLAGS-test-double-libmvec-sincos-avx2.c = -DREQUIRE_AVX2 +CFLAGS-test-double-libmvec-sincos-avx2-main.c = $(libmvec-sincos-cflags) $(double-vlen4-arch-ext2-cflags) +CFLAGS-test-double-libmvec-sincos-avx512.c = -DREQUIRE_AVX512F +CFLAGS-test-double-libmvec-sincos-avx512-main.c = $(libmvec-sincos-cflags) $(double-vlen8-arch-ext-cflags) + +CFLAGS-test-float-libmvec-sincosf-main.c = $(libmvec-sincos-cflags) +CFLAGS-test-float-libmvec-sincosf-avx.c = -DREQUIRE_AVX +CFLAGS-test-float-libmvec-sincosf-avx-main.c = $(libmvec-sincos-cflags) $(float-vlen8-arch-ext-cflags) +CFLAGS-test-float-libmvec-sincosf-avx2.c = -DREQUIRE_AVX2 +CFLAGS-test-float-libmvec-sincosf-avx2-main.c = $(libmvec-sincos-cflags) $(float-vlen8-arch-ext2-cflags) +CFLAGS-test-float-libmvec-sincosf-avx512.c = -DREQUIRE_AVX512F +CFLAGS-test-float-libmvec-sincosf-avx512-main.c = $(libmvec-sincos-cflags) $(float-vlen16-arch-ext-cflags) +endif +endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/Versions b/REORG.TODO/sysdeps/x86_64/fpu/Versions new file mode 100644 index 0000000000..08132045d6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/Versions @@ -0,0 +1,16 @@ +libmvec { + GLIBC_2.22 { + _ZGVbN2v_cos; _ZGVcN4v_cos; _ZGVdN4v_cos; _ZGVeN8v_cos; + _ZGVbN2v_sin; _ZGVcN4v_sin; _ZGVdN4v_sin; _ZGVeN8v_sin; + _ZGVbN2vvv_sincos; _ZGVcN4vvv_sincos; _ZGVdN4vvv_sincos; _ZGVeN8vvv_sincos; + _ZGVbN2v_log; _ZGVcN4v_log; _ZGVdN4v_log; _ZGVeN8v_log; + _ZGVbN2v_exp; _ZGVcN4v_exp; _ZGVdN4v_exp; _ZGVeN8v_exp; + _ZGVbN2vv_pow; _ZGVcN4vv_pow; _ZGVdN4vv_pow; _ZGVeN8vv_pow; + _ZGVbN4v_cosf; _ZGVcN8v_cosf; _ZGVdN8v_cosf; _ZGVeN16v_cosf; + _ZGVbN4v_sinf; _ZGVcN8v_sinf; _ZGVdN8v_sinf; _ZGVeN16v_sinf; + _ZGVbN4v_logf; _ZGVcN8v_logf; _ZGVdN8v_logf; _ZGVeN16v_logf; + _ZGVbN4v_expf; _ZGVcN8v_expf; _ZGVdN8v_expf; _ZGVeN16v_expf; + _ZGVbN4vv_powf; _ZGVcN8vv_powf; _ZGVdN8vv_powf; _ZGVeN16vv_powf; + _ZGVbN4vvv_sincosf; _ZGVcN8vvv_sincosf; _ZGVdN8vvv_sincosf; _ZGVeN16vvv_sincosf; + } +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_acosl.c b/REORG.TODO/sysdeps/x86_64/fpu/e_acosl.c new file mode 100644 index 0000000000..1ef6d3c94a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_acosl.c @@ -0,0 +1 @@ +#include "sysdeps/i386/fpu/e_acosl.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_atan2l.c b/REORG.TODO/sysdeps/x86_64/fpu/e_atan2l.c new file mode 100644 index 0000000000..bbd549f307 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_atan2l.c @@ -0,0 +1,2 @@ +#include "sysdeps/i386/fpu/e_atan2l.c" + diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_exp10l.S b/REORG.TODO/sysdeps/x86_64/fpu/e_exp10l.S new file mode 100644 index 0000000000..d843e2b5e8 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_exp10l.S @@ -0,0 +1,2 @@ +#define USE_AS_EXP10L +#include <e_expl.S> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_exp2l.S b/REORG.TODO/sysdeps/x86_64/fpu/e_exp2l.S new file mode 100644 index 0000000000..0e059b7565 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_exp2l.S @@ -0,0 +1,58 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Adapted for exp2 by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + * Public domain. + */ + +#include <machine/asm.h> +#include <x86_64-math-asm.h> + +DEFINE_LDBL_MIN + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_exp2l) + fldt 8(%rsp) +/* I added the following ugly construct because exp(+-Inf) resulted + in NaN. The ugliness results from the bright minds at Intel. + For the i686 the code can be written better. + -- drepper@cygnus.com. */ + fxam /* Is NaN or +-Inf? */ + fstsw %ax + movb $0x45, %dh + andb %ah, %dh + cmpb $0x05, %dh + je 1f /* Is +-Inf, jump. */ + movzwl 8+8(%rsp), %eax + andl $0x7fff, %eax + cmpl $0x3fbe, %eax + jge 3f + /* Argument's exponent below -65, result rounds to 1. */ + fld1 + faddp + ret +3: fld %st + frndint /* int(x) */ + fsubr %st,%st(1) /* fract(x) */ + fxch + f2xm1 /* 2^(fract(x)) - 1 */ + fld1 + faddp /* 2^(fract(x)) */ + fscale /* e^x */ + fstp %st(1) + LDBL_CHECK_FORCE_UFLOW_NONNEG_NAN + ret + +1: testl $0x200, %eax /* Test sign. */ + jz 2f /* If positive, jump. */ + fstp %st + fldz /* Set result to 0. */ +2: ret +END (__ieee754_exp2l) +strong_alias (__ieee754_exp2l, __exp2l_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_expf.S b/REORG.TODO/sysdeps/x86_64/fpu/e_expf.S new file mode 100644 index 0000000000..4fd2bb1fb5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_expf.S @@ -0,0 +1,339 @@ +/* Optimized __ieee754_expf function. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + Contributed by Intel Corporation. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* Short algorithm description: + * + * Let K = 64 (table size). + * e^x = 2^(x/log(2)) = 2^n * T[j] * (1 + P(y)) + * where + * x = m*log(2)/K + y, y in [0.0..log(2)/K] + * m = n*K + j, m,n,j - signed integer, j in [0..K-1] + * values of 2^(j/K) are tabulated as T[j]. + * + * P(y) is a minimax polynomial approximation of expf(x)-1 + * on small interval [0.0..log(2)/K]. + * + * P(y) = P3*y*y*y*y + P2*y*y*y + P1*y*y + P0*y, calculated as + * z = y*y; P(y) = (P3*z + P1)*z + (P2*z + P0)*y + * + * Special cases: + * expf(NaN) = NaN + * expf(+INF) = +INF + * expf(-INF) = 0 + * expf(x) = 1 for subnormals + * for finite argument, only expf(0)=1 is exact + * expf(x) overflows if x>88.7228317260742190 + * expf(x) underflows if x<-103.972076416015620 + */ + + .text +ENTRY(__ieee754_expf) + /* Input: single precision x in %xmm0 */ + cvtss2sd %xmm0, %xmm1 /* Convert x to double precision */ + movd %xmm0, %ecx /* Copy x */ + movsd L(DP_KLN2)(%rip), %xmm2 /* DP K/log(2) */ + movsd L(DP_P2)(%rip), %xmm3 /* DP P2 */ + movl %ecx, %eax /* x */ + mulsd %xmm1, %xmm2 /* DP x*K/log(2) */ + andl $0x7fffffff, %ecx /* |x| */ + lea L(DP_T)(%rip), %rsi /* address of table T[j] */ + cmpl $0x42ad496b, %ecx /* |x|<125*log(2) ? */ + movsd L(DP_P3)(%rip), %xmm4 /* DP P3 */ + addsd L(DP_RS)(%rip), %xmm2 /* DP x*K/log(2)+RS */ + jae L(special_paths) + + /* Here if |x|<125*log(2) */ + cmpl $0x31800000, %ecx /* |x|<2^(-28) ? */ + jb L(small_arg) + + /* Main path: here if 2^(-28)<=|x|<125*log(2) */ + cvtsd2ss %xmm2, %xmm2 /* SP x*K/log(2)+RS */ + movd %xmm2, %eax /* bits of n*K+j with trash */ + subss L(SP_RS)(%rip), %xmm2 /* SP t=round(x*K/log(2)) */ + movl %eax, %edx /* n*K+j with trash */ + cvtss2sd %xmm2, %xmm2 /* DP t */ + andl $0x3f, %eax /* bits of j */ + mulsd L(DP_NLN2K)(%rip), %xmm2/* DP -t*log(2)/K */ + andl $0xffffffc0, %edx /* bits of n */ +#ifdef __AVX__ + vaddsd %xmm1, %xmm2, %xmm0 /* DP y=x-t*log(2)/K */ + vmulsd %xmm0, %xmm0, %xmm2 /* DP z=y*y */ +#else + addsd %xmm1, %xmm2 /* DP y=x-t*log(2)/K */ + movaps %xmm2, %xmm0 /* DP y */ + mulsd %xmm2, %xmm2 /* DP z=y*y */ +#endif + mulsd %xmm2, %xmm4 /* DP P3*z */ + addl $0x1fc0, %edx /* bits of n + SP exponent bias */ + mulsd %xmm2, %xmm3 /* DP P2*z */ + shll $17, %edx /* SP 2^n */ + addsd L(DP_P1)(%rip), %xmm4 /* DP P3*z+P1 */ + addsd L(DP_P0)(%rip), %xmm3 /* DP P2*z+P0 */ + movd %edx, %xmm1 /* SP 2^n */ + mulsd %xmm2, %xmm4 /* DP (P3*z+P1)*z */ + mulsd %xmm3, %xmm0 /* DP (P2*z+P0)*y */ + addsd %xmm4, %xmm0 /* DP P(y) */ + mulsd (%rsi,%rax,8), %xmm0 /* DP P(y)*T[j] */ + addsd (%rsi,%rax,8), %xmm0 /* DP T[j]*(P(y)+1) */ + cvtsd2ss %xmm0, %xmm0 /* SP T[j]*(P(y)+1) */ + mulss %xmm1, %xmm0 /* SP result=2^n*(T[j]*(P(y)+1)) */ + ret + + .p2align 4 +L(small_arg): + /* Here if 0<=|x|<2^(-28) */ + addss L(SP_ONE)(%rip), %xmm0 /* 1.0 + x */ + /* Return 1.0 with inexact raised, except for x==0 */ + ret + + .p2align 4 +L(special_paths): + /* Here if 125*log(2)<=|x| */ + shrl $31, %eax /* Get sign bit of x, and depending on it: */ + lea L(SP_RANGE)(%rip), %rdx /* load over/underflow bound */ + cmpl (%rdx,%rax,4), %ecx /* |x|<under/overflow bound ? */ + jbe L(near_under_or_overflow) + + /* Here if |x|>under/overflow bound */ + cmpl $0x7f800000, %ecx /* |x| is finite ? */ + jae L(arg_inf_or_nan) + + /* Here if |x|>under/overflow bound, and x is finite */ + testq %rax, %rax /* sign of x nonzero ? */ + je L(res_overflow) + + /* Here if -inf<x<underflow bound (x<0) */ + movss L(SP_SMALL)(%rip), %xmm0/* load small value 2^(-100) */ + mulss %xmm0, %xmm0 /* Return underflowed result (zero or subnormal) */ + ret + + .p2align 4 +L(res_overflow): + /* Here if overflow bound<x<inf (x>0) */ + movss L(SP_LARGE)(%rip), %xmm0/* load large value 2^100 */ + mulss %xmm0, %xmm0 /* Return overflowed result (Inf or max normal) */ + ret + + .p2align 4 +L(arg_inf_or_nan): + /* Here if |x| is Inf or NAN */ + jne L(arg_nan) /* |x| is Inf ? */ + + /* Here if |x| is Inf */ + lea L(SP_INF_0)(%rip), %rdx /* depending on sign of x: */ + movss (%rdx,%rax,4), %xmm0 /* return zero or Inf */ + ret + + .p2align 4 +L(arg_nan): + /* Here if |x| is NaN */ + addss %xmm0, %xmm0 /* Return x+x (raise invalid) */ + ret + + .p2align 4 +L(near_under_or_overflow): + /* Here if 125*log(2)<=|x|<under/overflow bound */ + cvtsd2ss %xmm2, %xmm2 /* SP x*K/log(2)+RS */ + movd %xmm2, %eax /* bits of n*K+j with trash */ + subss L(SP_RS)(%rip), %xmm2 /* SP t=round(x*K/log(2)) */ + movl %eax, %edx /* n*K+j with trash */ + cvtss2sd %xmm2, %xmm2 /* DP t */ + andl $0x3f, %eax /* bits of j */ + mulsd L(DP_NLN2K)(%rip), %xmm2/* DP -t*log(2)/K */ + andl $0xffffffc0, %edx /* bits of n */ +#ifdef __AVX__ + vaddsd %xmm1, %xmm2, %xmm0 /* DP y=x-t*log(2)/K */ + vmulsd %xmm0, %xmm0, %xmm2 /* DP z=y*y */ +#else + addsd %xmm1, %xmm2 /* DP y=x-t*log(2)/K */ + movaps %xmm2, %xmm0 /* DP y */ + mulsd %xmm2, %xmm2 /* DP z=y*y */ +#endif + mulsd %xmm2, %xmm4 /* DP P3*z */ + addl $0xffc0, %edx /* bits of n + DP exponent bias */ + mulsd %xmm2, %xmm3 /* DP P2*z */ + shlq $46, %rdx /* DP 2^n */ + addsd L(DP_P1)(%rip), %xmm4 /* DP P3*z+P1 */ + addsd L(DP_P0)(%rip), %xmm3 /* DP P2*z+P0 */ + movd %rdx, %xmm1 /* DP 2^n */ + mulsd %xmm2, %xmm4 /* DP (P3*z+P1)*z */ + mulsd %xmm3, %xmm0 /* DP (P2*z+P0)*y */ + addsd %xmm4, %xmm0 /* DP P(y) */ + mulsd (%rsi,%rax,8), %xmm0 /* DP P(y)*T[j] */ + addsd (%rsi,%rax,8), %xmm0 /* DP T[j]*(P(y)+1) */ + mulsd %xmm1, %xmm0 /* DP result=2^n*(T[j]*(P(y)+1)) */ + cvtsd2ss %xmm0, %xmm0 /* convert result to single precision */ + ret +END(__ieee754_expf) + + .section .rodata, "a" + .p2align 3 +L(DP_T): /* table of double precision values 2^(j/K) for j=[0..K-1] */ + .long 0x00000000, 0x3ff00000 + .long 0x3e778061, 0x3ff02c9a + .long 0xd3158574, 0x3ff059b0 + .long 0x18759bc8, 0x3ff08745 + .long 0x6cf9890f, 0x3ff0b558 + .long 0x32d3d1a2, 0x3ff0e3ec + .long 0xd0125b51, 0x3ff11301 + .long 0xaea92de0, 0x3ff1429a + .long 0x3c7d517b, 0x3ff172b8 + .long 0xeb6fcb75, 0x3ff1a35b + .long 0x3168b9aa, 0x3ff1d487 + .long 0x88628cd6, 0x3ff2063b + .long 0x6e756238, 0x3ff2387a + .long 0x65e27cdd, 0x3ff26b45 + .long 0xf51fdee1, 0x3ff29e9d + .long 0xa6e4030b, 0x3ff2d285 + .long 0x0a31b715, 0x3ff306fe + .long 0xb26416ff, 0x3ff33c08 + .long 0x373aa9cb, 0x3ff371a7 + .long 0x34e59ff7, 0x3ff3a7db + .long 0x4c123422, 0x3ff3dea6 + .long 0x21f72e2a, 0x3ff4160a + .long 0x6061892d, 0x3ff44e08 + .long 0xb5c13cd0, 0x3ff486a2 + .long 0xd5362a27, 0x3ff4bfda + .long 0x769d2ca7, 0x3ff4f9b2 + .long 0x569d4f82, 0x3ff5342b + .long 0x36b527da, 0x3ff56f47 + .long 0xdd485429, 0x3ff5ab07 + .long 0x15ad2148, 0x3ff5e76f + .long 0xb03a5585, 0x3ff6247e + .long 0x82552225, 0x3ff66238 + .long 0x667f3bcd, 0x3ff6a09e + .long 0x3c651a2f, 0x3ff6dfb2 + .long 0xe8ec5f74, 0x3ff71f75 + .long 0x564267c9, 0x3ff75feb + .long 0x73eb0187, 0x3ff7a114 + .long 0x36cf4e62, 0x3ff7e2f3 + .long 0x994cce13, 0x3ff82589 + .long 0x9b4492ed, 0x3ff868d9 + .long 0x422aa0db, 0x3ff8ace5 + .long 0x99157736, 0x3ff8f1ae + .long 0xb0cdc5e5, 0x3ff93737 + .long 0x9fde4e50, 0x3ff97d82 + .long 0x82a3f090, 0x3ff9c491 + .long 0x7b5de565, 0x3ffa0c66 + .long 0xb23e255d, 0x3ffa5503 + .long 0x5579fdbf, 0x3ffa9e6b + .long 0x995ad3ad, 0x3ffae89f + .long 0xb84f15fb, 0x3ffb33a2 + .long 0xf2fb5e47, 0x3ffb7f76 + .long 0x904bc1d2, 0x3ffbcc1e + .long 0xdd85529c, 0x3ffc199b + .long 0x2e57d14b, 0x3ffc67f1 + .long 0xdcef9069, 0x3ffcb720 + .long 0x4a07897c, 0x3ffd072d + .long 0xdcfba487, 0x3ffd5818 + .long 0x03db3285, 0x3ffda9e6 + .long 0x337b9b5f, 0x3ffdfc97 + .long 0xe78b3ff6, 0x3ffe502e + .long 0xa2a490da, 0x3ffea4af + .long 0xee615a27, 0x3ffefa1b + .long 0x5b6e4540, 0x3fff5076 + .long 0x819e90d8, 0x3fffa7c1 + .type L(DP_T), @object + ASM_SIZE_DIRECTIVE(L(DP_T)) + + .section .rodata.cst8,"aM",@progbits,8 + .p2align 3 +L(DP_KLN2): /* double precision K/log(2) */ + .long 0x652b82fe, 0x40571547 + .type L(DP_KLN2), @object + ASM_SIZE_DIRECTIVE(L(DP_KLN2)) + + .p2align 3 +L(DP_NLN2K): /* double precision -log(2)/K */ + .long 0xfefa39ef, 0xbf862e42 + .type L(DP_NLN2K), @object + ASM_SIZE_DIRECTIVE(L(DP_NLN2K)) + + .p2align 3 +L(DP_RS): /* double precision 2^23+2^22 */ + .long 0x00000000, 0x41680000 + .type L(DP_RS), @object + ASM_SIZE_DIRECTIVE(L(DP_RS)) + + .p2align 3 +L(DP_P3): /* double precision polynomial coefficient P3 */ + .long 0xeb78fa85, 0x3fa56420 + .type L(DP_P3), @object + ASM_SIZE_DIRECTIVE(L(DP_P3)) + + .p2align 3 +L(DP_P1): /* double precision polynomial coefficient P1 */ + .long 0x008d6118, 0x3fe00000 + .type L(DP_P1), @object + ASM_SIZE_DIRECTIVE(L(DP_P1)) + + .p2align 3 +L(DP_P2): /* double precision polynomial coefficient P2 */ + .long 0xda752d4f, 0x3fc55550 + .type L(DP_P2), @object + ASM_SIZE_DIRECTIVE(L(DP_P2)) + + .p2align 3 +L(DP_P0): /* double precision polynomial coefficient P0 */ + .long 0xffffe7c6, 0x3fefffff + .type L(DP_P0), @object + ASM_SIZE_DIRECTIVE(L(DP_P0)) + + .p2align 2 +L(SP_RANGE): /* single precision overflow/underflow bounds */ + .long 0x42b17217 /* if x>this bound, then result overflows */ + .long 0x42cff1b4 /* if x<this bound, then result underflows */ + .type L(SP_RANGE), @object + ASM_SIZE_DIRECTIVE(L(SP_RANGE)) + + .p2align 2 +L(SP_INF_0): + .long 0x7f800000 /* single precision Inf */ + .long 0 /* single precision zero */ + .type L(SP_INF_0), @object + ASM_SIZE_DIRECTIVE(L(SP_INF_0)) + + .section .rodata.cst4,"aM",@progbits,4 + .p2align 2 +L(SP_RS): /* single precision 2^23+2^22 */ + .long 0x4b400000 + .type L(SP_RS), @object + ASM_SIZE_DIRECTIVE(L(SP_RS)) + + .p2align 2 +L(SP_SMALL): /* single precision small value 2^(-100) */ + .long 0x0d800000 + .type L(SP_SMALL), @object + ASM_SIZE_DIRECTIVE(L(SP_SMALL)) + + .p2align 2 +L(SP_LARGE): /* single precision large value 2^100 */ + .long 0x71800000 + .type L(SP_LARGE), @object + ASM_SIZE_DIRECTIVE(L(SP_LARGE)) + + .p2align 2 +L(SP_ONE): /* single precision 1.0 */ + .long 0x3f800000 + .type L(SP_ONE), @object + ASM_SIZE_DIRECTIVE(L(SP_ONE)) + +strong_alias (__ieee754_expf, __expf_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_expl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_expl.S new file mode 100644 index 0000000000..a4ef023b2b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_expl.S @@ -0,0 +1,219 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + */ + +/* + * The 8087 method for the exponential function is to calculate + * exp(x) = 2^(x log2(e)) + * after separating integer and fractional parts + * x log2(e) = i + f, |f| <= .5 + * 2^i is immediate but f needs to be precise for long double accuracy. + * Suppress range reduction error in computing f by the following. + * Separate x into integer and fractional parts + * x = xi + xf, |xf| <= .5 + * Separate log2(e) into the sum of an exact number c0 and small part c1. + * c0 + c1 = log2(e) to extra precision + * Then + * f = (c0 xi - i) + c0 xf + c1 x + * where c0 xi is exact and so also is (c0 xi - i). + * -- moshier@na-net.ornl.gov + */ + +#include <machine/asm.h> +#include <x86_64-math-asm.h> + +#ifdef USE_AS_EXP10L +# define IEEE754_EXPL __ieee754_exp10l +# define EXPL_FINITE __exp10l_finite +# define FLDLOG fldl2t +#elif defined USE_AS_EXPM1L +# define IEEE754_EXPL __expm1l +# undef EXPL_FINITE +# define FLDLOG fldl2e +#else +# define IEEE754_EXPL __ieee754_expl +# define EXPL_FINITE __expl_finite +# define FLDLOG fldl2e +#endif + + .section .rodata.cst16,"aM",@progbits,16 + + .p2align 4 +#ifdef USE_AS_EXP10L + .type c0,@object +c0: .byte 0, 0, 0, 0, 0, 0, 0x9a, 0xd4, 0x00, 0x40 + .byte 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(c0) + .type c1,@object +c1: .byte 0x58, 0x92, 0xfc, 0x15, 0x37, 0x9a, 0x97, 0xf0, 0xef, 0x3f + .byte 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(c1) +#else + .type c0,@object +c0: .byte 0, 0, 0, 0, 0, 0, 0xaa, 0xb8, 0xff, 0x3f + .byte 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(c0) + .type c1,@object +c1: .byte 0x20, 0xfa, 0xee, 0xc2, 0x5f, 0x70, 0xa5, 0xec, 0xed, 0x3f + .byte 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(c1) +#endif +#ifndef USE_AS_EXPM1L + .type csat,@object +csat: .byte 0, 0, 0, 0, 0, 0, 0, 0x80, 0x0e, 0x40 + .byte 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(csat) +DEFINE_LDBL_MIN +#endif + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(IEEE754_EXPL) +#ifdef USE_AS_EXPM1L + movzwl 8+8(%rsp), %eax + xorb $0x80, %ah // invert sign bit (now 1 is "positive") + cmpl $0xc006, %eax // is num positive and exp >= 6 (number is >= 128.0)? + jae HIDDEN_JUMPTARGET (__expl) // (if num is denormal, it is at least >= 64.0) +#endif + fldt 8(%rsp) +/* I added the following ugly construct because expl(+-Inf) resulted + in NaN. The ugliness results from the bright minds at Intel. + For the i686 the code can be written better. + -- drepper@cygnus.com. */ + fxam /* Is NaN or +-Inf? */ +#ifdef USE_AS_EXPM1L + xorb $0x80, %ah + cmpl $0xc006, %eax + fstsw %ax + movb $0x45, %dh + jb 4f + + /* Below -64.0 (may be -NaN or -Inf). */ + andb %ah, %dh + cmpb $0x01, %dh + je 6f /* Is +-NaN, jump. */ + jmp 1f /* -large, possibly -Inf. */ + +4: /* In range -64.0 to 64.0 (may be +-0 but not NaN or +-Inf). */ + /* Test for +-0 as argument. */ + andb %ah, %dh + cmpb $0x40, %dh + je 2f + + /* Test for arguments that are small but not subnormal. */ + movzwl 8+8(%rsp), %eax + andl $0x7fff, %eax + cmpl $0x3fbf, %eax + jge 3f + /* Argument's exponent below -64; avoid spurious underflow if + normal. */ + cmpl $0x0001, %eax + jge 2f + /* Force underflow and return the argument, to avoid wrong signs + of zero results from the code below in some rounding modes. */ + fld %st + fmul %st + fstp %st + jmp 2f +#else + movzwl 8+8(%rsp), %eax + andl $0x7fff, %eax + cmpl $0x400d, %eax + jg 5f + cmpl $0x3fbc, %eax + jge 3f + /* Argument's exponent below -67, result rounds to 1. */ + fld1 + faddp + jmp 2f +5: /* Overflow, underflow or infinity or NaN as argument. */ + fstsw %ax + movb $0x45, %dh + andb %ah, %dh + cmpb $0x05, %dh + je 1f /* Is +-Inf, jump. */ + cmpb $0x01, %dh + je 6f /* Is +-NaN, jump. */ + /* Overflow or underflow; saturate. */ + fstp %st + fldt MO(csat) + andb $2, %ah + jz 3f + fchs +#endif +3: FLDLOG /* 1 log2(base) */ + fmul %st(1), %st /* 1 x log2(base) */ + /* Set round-to-nearest temporarily. */ + fstcw -4(%rsp) + movl $0xf3ff, %edx + andl -4(%rsp), %edx + movl %edx, -8(%rsp) + fldcw -8(%rsp) + frndint /* 1 i */ + fld %st(1) /* 2 x */ + frndint /* 2 xi */ + fldcw -4(%rsp) + fld %st(1) /* 3 i */ + fldt MO(c0) /* 4 c0 */ + fld %st(2) /* 5 xi */ + fmul %st(1), %st /* 5 c0 xi */ + fsubp %st, %st(2) /* 4 f = c0 xi - i */ + fld %st(4) /* 5 x */ + fsub %st(3), %st /* 5 xf = x - xi */ + fmulp %st, %st(1) /* 4 c0 xf */ + faddp %st, %st(1) /* 3 f = f + c0 xf */ + fldt MO(c1) /* 4 */ + fmul %st(4), %st /* 4 c1 * x */ + faddp %st, %st(1) /* 3 f = f + c1 * x */ + f2xm1 /* 3 2^(fract(x * log2(base))) - 1 */ +#ifdef USE_AS_EXPM1L + fstp %st(1) /* 2 */ + fscale /* 2 scale factor is st(1); base^x - 2^i */ + fxch /* 2 i */ + fld1 /* 3 1.0 */ + fscale /* 3 2^i */ + fld1 /* 4 1.0 */ + fsubrp %st, %st(1) /* 3 2^i - 1.0 */ + fstp %st(1) /* 2 */ + faddp %st, %st(1) /* 1 base^x - 1.0 */ +#else + fld1 /* 4 1.0 */ + faddp /* 3 2^(fract(x * log2(base))) */ + fstp %st(1) /* 2 */ + fscale /* 2 scale factor is st(1); base^x */ + fstp %st(1) /* 1 */ + LDBL_CHECK_FORCE_UFLOW_NONNEG +#endif + fstp %st(1) /* 0 */ + jmp 2f +1: +#ifdef USE_AS_EXPM1L + /* For expm1l, only negative sign gets here. */ + fstp %st + fld1 + fchs +#else + testl $0x200, %eax /* Test sign. */ + jz 2f /* If positive, jump. */ + fstp %st + fldz /* Set result to 0. */ +#endif +2: ret +6: /* NaN argument. */ + fadd %st + ret +END(IEEE754_EXPL) +#ifdef USE_AS_EXPM1L +libm_hidden_def (__expm1l) +weak_alias (__expm1l, expm1l) +#else +strong_alias (IEEE754_EXPL, EXPL_FINITE) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_fmodl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_fmodl.S new file mode 100644 index 0000000000..07c50df8d1 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_fmodl.S @@ -0,0 +1,23 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + +RCSID("$NetBSD: $") + +ENTRY(__ieee754_fmodl) + fldt 24(%rsp) + fldt 8(%rsp) +1: fprem + fstsw %ax + and $04,%ah + jnz 1b + fstp %st(1) + ret +END (__ieee754_fmodl) +strong_alias (__ieee754_fmodl, __fmodl_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_ilogbl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_ilogbl.S new file mode 100644 index 0000000000..ae6c0fe6f9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_ilogbl.S @@ -0,0 +1,39 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com> + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + * Public domain. + */ + +#include <machine/asm.h> + +ENTRY(__ieee754_ilogbl) + fldt 8(%rsp) +/* I added the following ugly construct because ilogb(+-Inf) is + required to return INT_MAX in ISO C99. + -- jakub@redhat.com. */ + fxam /* Is NaN or +-Inf? */ + fstsw %ax + movb $0x45, %dh + andb %ah, %dh + cmpb $0x05, %dh + je 1f /* Is +-Inf, jump. */ + cmpb $0x40, %dh + je 2f /* Is +-Inf, jump. */ + + fxtract + fstp %st + + fistpl -4(%rsp) + fwait + movl -4(%rsp),%eax + + ret + +1: fstp %st + movl $0x7fffffff, %eax + ret +2: fstp %st + movl $0x80000000, %eax /* FP_ILOGB0 */ + ret +END (__ieee754_ilogbl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_log10l.S b/REORG.TODO/sysdeps/x86_64/fpu/e_log10l.S new file mode 100644 index 0000000000..e0cb88e32e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_log10l.S @@ -0,0 +1,92 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * + * Changed to use fyl2xp1 for values near 1, <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + + .section .rodata.cst8,"aM",@progbits,8 + + .p2align 3 + .type one,@object +one: .double 1.0 + ASM_SIZE_DIRECTIVE(one) + /* It is not important that this constant is precise. It is only + a value which is known to be on the safe side for using the + fyl2xp1 instruction. */ + .type limit,@object +limit: .double 0.29 + ASM_SIZE_DIRECTIVE(limit) + + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_log10l) + fldlg2 // log10(2) + fldt 8(%rsp) // x : log10(2) + fxam + fnstsw + fld %st // x : x : log10(2) + testb $1, %ah + jnz 3f // in case x is NaN or ±Inf +4: fsubl MO(one) // x-1 : x : log10(2) + fld %st // x-1 : x-1 : x : log10(2) + fabs // |x-1| : x-1 : x : log10(2) + fcompl MO(limit) // x-1 : x : log10(2) + fnstsw // x-1 : x : log10(2) + andb $0x45, %ah + jz 2f + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 5f + fabs // log10(1) is +0 in all rounding modes. +5: fstp %st(1) // x-1 : log10(2) + fyl2xp1 // log10(x) + ret + +2: fstp %st(0) // x : log10(2) + fyl2x // log10(x) + ret + +3: testb $4, %ah + jnz 4b // in case x is ±Inf + fstp %st(1) + fstp %st(1) + fadd %st(0) + ret +END(__ieee754_log10l) + + +ENTRY(__log10l_finite) + fldlg2 // log10(2) + fldt 8(%rsp) // x : log10(2) + fld %st // x : x : log10(2) +4: fsubl MO(one) // x-1 : x : log10(2) + fld %st // x-1 : x-1 : x : log10(2) + fabs // |x-1| : x-1 : x : log10(2) + fcompl MO(limit) // x-1 : x : log10(2) + fnstsw // x-1 : x : log10(2) + andb $0x45, %ah + jz 2b + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 6f + fabs // log10(1) is +0 in all rounding modes. +6: fstp %st(1) // x-1 : log10(2) + fyl2xp1 // log10(x) + ret +END(__log10l_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_log2l.S b/REORG.TODO/sysdeps/x86_64/fpu/e_log2l.S new file mode 100644 index 0000000000..023ec29164 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_log2l.S @@ -0,0 +1,91 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Adapted for use as log2 by Ulrich Drepper <drepper@cygnus.com>. + * Public domain. + * + * Changed to use fyl2xp1 for values near 1, <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + + .section .rodata.cst8,"aM",@progbits,8 + + .p2align 3 + .type one,@object +one: .double 1.0 + ASM_SIZE_DIRECTIVE(one) + /* It is not important that this constant is precise. It is only + a value which is known to be on the safe side for using the + fyl2xp1 instruction. */ + .type limit,@object +limit: .double 0.29 + ASM_SIZE_DIRECTIVE(limit) + + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_log2l) + fldl MO(one) + fldt 8(%rsp) // x : 1 + fxam + fnstsw + fld %st // x : x : 1 + testb $1, %ah + jnz 3f // in case x is NaN or ±Inf +4: fsub %st(2), %st // x-1 : x : 1 + fld %st // x-1 : x-1 : x : 1 + fabs // |x-1| : x-1 : x : 1 + fcompl MO(limit) // x-1 : x : 1 + fnstsw // x-1 : x : 1 + andb $0x45, %ah + jz 2f + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 5f + fabs // log2(1) is +0 in all rounding modes. +5: fstp %st(1) // x-1 : 1 + fyl2xp1 // log(x) + ret + +2: fstp %st(0) // x : 1 + fyl2x // log(x) + ret + +3: testb $4, %ah + jnz 4b // in case x is ±Inf + fstp %st(1) + fstp %st(1) + fadd %st(0) + ret +END (__ieee754_log2l) + + +ENTRY(__log2l_finite) + fldl MO(one) + fldt 8(%rsp) // x : 1 + fld %st // x : x : 1 + fsub %st(2), %st // x-1 : x : 1 + fld %st // x-1 : x-1 : x : 1 + fabs // |x-1| : x-1 : x : 1 + fcompl MO(limit) // x-1 : x : 1 + fnstsw // x-1 : x : 1 + andb $0x45, %ah + jz 2b + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 6f + fabs // log2(1) is +0 in all rounding modes. +6: fstp %st(1) // x-1 : 1 + fyl2xp1 // log(x) + ret +END (__log2l_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_logl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_logl.S new file mode 100644 index 0000000000..0d3576f48b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_logl.S @@ -0,0 +1,94 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + + + .section .rodata.cst8,"aM",@progbits,8 + + .p2align 3 + .type one,@object +one: .double 1.0 + ASM_SIZE_DIRECTIVE(one) + /* It is not important that this constant is precise. It is only + a value which is known to be on the safe side for using the + fyl2xp1 instruction. */ + .type limit,@object +limit: .double 0.29 + ASM_SIZE_DIRECTIVE(limit) + + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_logl) + fldln2 // log(2) + fldt 8(%rsp) // x : log(2) + fxam + fnstsw + fld %st // x : x : log(2) + testb $1, %ah + jnz 3f // in case x is NaN or +-Inf + movzwl 8+8(%rsp), %eax + cmpl $0xc000, %eax + jae 6f // x <= -2, avoid overflow from -LDBL_MAX - 1. +4: fsubl MO(one) // x-1 : x : log(2) +6: fld %st // x-1 : x-1 : x : log(2) + fabs // |x-1| : x-1 : x : log(2) + fcompl MO(limit) // x-1 : x : log(2) + fnstsw // x-1 : x : log(2) + andb $0x45, %ah + jz 2f + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 5f + fabs // log(1) is +0 in all rounding modes. +5: fstp %st(1) // x-1 : log(2) + fyl2xp1 // log(x) + ret + +2: fstp %st(0) // x : log(2) + fyl2x // log(x) + ret + +3: testb $4, %ah + jnz 4b // in case x is +-Inf + fstp %st(1) + fstp %st(1) + fadd %st(0) + ret +END (__ieee754_logl) + + +ENTRY(__logl_finite) + fldln2 // log(2) + fldt 8(%rsp) // x : log(2) + fld %st // x : x : log(2) + fsubl MO(one) // x-1 : x : log(2) + fld %st // x-1 : x-1 : x : log(2) + fabs // |x-1| : x-1 : x : log(2) + fcompl MO(limit) // x-1 : x : log(2) + fnstsw // x-1 : x : log(2) + andb $0x45, %ah + jz 2b + fxam + fnstsw + andb $0x45, %ah + cmpb $0x40, %ah + jne 7f + fabs // log(1) is +0 in all rounding modes. +7: fstp %st(1) // x-1 : log(2) + fyl2xp1 // log(x) + ret +END (__logl_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_powl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_powl.S new file mode 100644 index 0000000000..571c0a18d5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_powl.S @@ -0,0 +1,433 @@ +/* ix87 specific implementation of pow function. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1996. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <x86_64-math-asm.h> + + .section .rodata.cst8,"aM",@progbits,8 + + .p2align 3 + .type one,@object +one: .double 1.0 + ASM_SIZE_DIRECTIVE(one) + .type p2,@object +p2: .byte 0, 0, 0, 0, 0, 0, 0x10, 0x40 + ASM_SIZE_DIRECTIVE(p2) + .type p63,@object +p63: .byte 0, 0, 0, 0, 0, 0, 0xe0, 0x43 + ASM_SIZE_DIRECTIVE(p63) + .type p64,@object +p64: .byte 0, 0, 0, 0, 0, 0, 0xf0, 0x43 + ASM_SIZE_DIRECTIVE(p64) + .type p78,@object +p78: .byte 0, 0, 0, 0, 0, 0, 0xd0, 0x44 + ASM_SIZE_DIRECTIVE(p78) + .type pm79,@object +pm79: .byte 0, 0, 0, 0, 0, 0, 0, 0x3b + ASM_SIZE_DIRECTIVE(pm79) + + .section .rodata.cst16,"aM",@progbits,16 + + .p2align 3 + .type infinity,@object +inf_zero: +infinity: + .byte 0, 0, 0, 0, 0, 0, 0xf0, 0x7f + ASM_SIZE_DIRECTIVE(infinity) + .type zero,@object +zero: .double 0.0 + ASM_SIZE_DIRECTIVE(zero) + .type minf_mzero,@object +minf_mzero: +minfinity: + .byte 0, 0, 0, 0, 0, 0, 0xf0, 0xff +mzero: + .byte 0, 0, 0, 0, 0, 0, 0, 0x80 + ASM_SIZE_DIRECTIVE(minf_mzero) +DEFINE_LDBL_MIN + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_powl) + fldt 24(%rsp) // y + fxam + + + fnstsw + movb %ah, %dl + andb $0x45, %ah + cmpb $0x40, %ah // is y == 0 ? + je 11f + + cmpb $0x05, %ah // is y == ±inf ? + je 12f + + cmpb $0x01, %ah // is y == NaN ? + je 30f + + fldt 8(%rsp) // x : y + + fxam + fnstsw + movb %ah, %dh + andb $0x45, %ah + cmpb $0x40, %ah + je 20f // x is ±0 + + cmpb $0x05, %ah + je 15f // x is ±inf + + cmpb $0x01, %ah + je 31f // x is NaN + + fxch // y : x + + /* fistpll raises invalid exception for |y| >= 1L<<63. */ + fldl MO(p63) // 1L<<63 : y : x + fld %st(1) // y : 1L<<63 : y : x + fabs // |y| : 1L<<63 : y : x + fcomip %st(1), %st // 1L<<63 : y : x + fstp %st(0) // y : x + jnc 2f + + /* First see whether `y' is a natural number. In this case we + can use a more precise algorithm. */ + fld %st // y : y : x + fistpll -8(%rsp) // y : x + fildll -8(%rsp) // int(y) : y : x + fucomip %st(1),%st // y : x + je 9f + + // If y has absolute value at most 0x1p-79, then any finite + // nonzero x will result in 1. Saturate y to those bounds to + // avoid underflow in the calculation of y*log2(x). + fldl MO(pm79) // 0x1p-79 : y : x + fld %st(1) // y : 0x1p-79 : y : x + fabs // |y| : 0x1p-79 : y : x + fcomip %st(1), %st // 0x1p-79 : y : x + fstp %st(0) // y : x + jnc 3f + fstp %st(0) // pop y + fldl MO(pm79) // 0x1p-79 : x + testb $2, %dl + jnz 3f // y > 0 + fchs // -0x1p-79 : x + jmp 3f + +9: /* OK, we have an integer value for y. Unless very small + (we use < 4), use the algorithm for real exponent to avoid + accumulation of errors. */ + fldl MO(p2) // 4 : y : x + fld %st(1) // y : 4 : y : x + fabs // |y| : 4 : y : x + fcomip %st(1), %st // 4 : y : x + fstp %st(0) // y : x + jnc 3f + mov -8(%rsp),%eax + mov -4(%rsp),%edx + orl $0, %edx + fstp %st(0) // x + jns 4f // y >= 0, jump + fdivrl MO(one) // 1/x (now referred to as x) + negl %eax + adcl $0, %edx + negl %edx +4: fldl MO(one) // 1 : x + fxch + + /* If y is even, take the absolute value of x. Otherwise, + ensure all intermediate values that might overflow have the + sign of x. */ + testb $1, %al + jnz 6f + fabs + +6: shrdl $1, %edx, %eax + jnc 5f + fxch + fabs + fmul %st(1) // x : ST*x + fxch +5: fld %st // x : x : ST*x + fabs // |x| : x : ST*x + fmulp // |x|*x : ST*x + shrl $1, %edx + movl %eax, %ecx + orl %edx, %ecx + jnz 6b + fstp %st(0) // ST*x + LDBL_CHECK_FORCE_UFLOW_NONNAN + ret + + /* y is ±NAN */ +30: fldt 8(%rsp) // x : y + fldl MO(one) // 1.0 : x : y + fucomip %st(1),%st // x : y + je 32f +31: /* At least one argument NaN, and result should be NaN. */ + faddp + ret +32: jc 31b + /* pow (1, NaN); check if the NaN signaling. */ + testb $0x40, 31(%rsp) + jz 31b + fstp %st(1) + ret + + .align ALIGNARG(4) +2: // y is a large integer (absolute value at least 1L<<63). + // If y has absolute value at least 1L<<78, then any finite + // nonzero x will result in 0 (underflow), 1 or infinity (overflow). + // Saturate y to those bounds to avoid overflow in the calculation + // of y*log2(x). + fldl MO(p78) // 1L<<78 : y : x + fld %st(1) // y : 1L<<78 : y : x + fabs // |y| : 1L<<78 : y : x + fcomip %st(1), %st // 1L<<78 : y : x + fstp %st(0) // y : x + jc 3f + fstp %st(0) // pop y + fldl MO(p78) // 1L<<78 : x + testb $2, %dl + jz 3f // y > 0 + fchs // -(1L<<78) : x + .align ALIGNARG(4) +3: /* y is a real number. */ + subq $40, %rsp + cfi_adjust_cfa_offset (40) + fstpt 16(%rsp) // x + fstpt (%rsp) // <empty> + call HIDDEN_JUMPTARGET (__powl_helper) // <result> + addq $40, %rsp + cfi_adjust_cfa_offset (-40) + ret + + // pow(x,±0) = 1, unless x is sNaN + .align ALIGNARG(4) +11: fstp %st(0) // pop y + fldt 8(%rsp) // x + fxam + fnstsw + andb $0x45, %ah + cmpb $0x01, %ah + je 112f // x is NaN +111: fstp %st(0) + fldl MO(one) + ret + +112: testb $0x40, 15(%rsp) + jnz 111b + fadd %st(0) + ret + + // y == ±inf + .align ALIGNARG(4) +12: fstp %st(0) // pop y + fldl MO(one) // 1 + fldt 8(%rsp) // x : 1 + fabs // abs(x) : 1 + fucompp // < 1, == 1, or > 1 + fnstsw + andb $0x45, %ah + cmpb $0x45, %ah + je 13f // jump if x is NaN + + cmpb $0x40, %ah + je 14f // jump if |x| == 1 + + shlb $1, %ah + xorb %ah, %dl + andl $2, %edx +#ifdef PIC + lea inf_zero(%rip),%rcx + fldl (%rcx, %rdx, 4) +#else + fldl inf_zero(,%rdx, 4) +#endif + ret + + .align ALIGNARG(4) +14: fldl MO(one) + ret + + .align ALIGNARG(4) +13: fldt 8(%rsp) // load x == NaN + fadd %st(0) + ret + + .align ALIGNARG(4) + // x is ±inf +15: fstp %st(0) // y + testb $2, %dh + jz 16f // jump if x == +inf + + // fistpll raises invalid exception for |y| >= 1L<<63, but y + // may be odd unless we know |y| >= 1L<<64. + fldl MO(p64) // 1L<<64 : y + fld %st(1) // y : 1L<<64 : y + fabs // |y| : 1L<<64 : y + fcomip %st(1), %st // 1L<<64 : y + fstp %st(0) // y + jnc 16f + fldl MO(p63) // p63 : y + fxch // y : p63 + fprem // y%p63 : p63 + fstp %st(1) // y%p63 + + // We must find out whether y is an odd integer. + fld %st // y : y + fistpll -8(%rsp) // y + fildll -8(%rsp) // int(y) : y + fucomip %st(1),%st + ffreep %st // <empty> + jne 17f + + // OK, the value is an integer, but is it odd? + mov -8(%rsp), %eax + mov -4(%rsp), %edx + andb $1, %al + jz 18f // jump if not odd + // It's an odd integer. + shrl $31, %edx +#ifdef PIC + lea minf_mzero(%rip),%rcx + fldl (%rcx, %rdx, 8) +#else + fldl minf_mzero(,%rdx, 8) +#endif + ret + + .align ALIGNARG(4) +16: fcompl MO(zero) + fnstsw + shrl $5, %eax + andl $8, %eax +#ifdef PIC + lea inf_zero(%rip),%rcx + fldl (%rcx, %rax, 1) +#else + fldl inf_zero(,%rax, 1) +#endif + ret + + .align ALIGNARG(4) +17: shll $30, %edx // sign bit for y in right position +18: shrl $31, %edx +#ifdef PIC + lea inf_zero(%rip),%rcx + fldl (%rcx, %rdx, 8) +#else + fldl inf_zero(,%rdx, 8) +#endif + ret + + .align ALIGNARG(4) + // x is ±0 +20: fstp %st(0) // y + testb $2, %dl + jz 21f // y > 0 + + // x is ±0 and y is < 0. We must find out whether y is an odd integer. + testb $2, %dh + jz 25f + + // fistpll raises invalid exception for |y| >= 1L<<63, but y + // may be odd unless we know |y| >= 1L<<64. + fldl MO(p64) // 1L<<64 : y + fld %st(1) // y : 1L<<64 : y + fabs // |y| : 1L<<64 : y + fcomip %st(1), %st // 1L<<64 : y + fstp %st(0) // y + jnc 25f + fldl MO(p63) // p63 : y + fxch // y : p63 + fprem // y%p63 : p63 + fstp %st(1) // y%p63 + + fld %st // y : y + fistpll -8(%rsp) // y + fildll -8(%rsp) // int(y) : y + fucomip %st(1),%st + ffreep %st // <empty> + jne 26f + + // OK, the value is an integer, but is it odd? + mov -8(%rsp),%eax + mov -4(%rsp),%edx + andb $1, %al + jz 27f // jump if not odd + // It's an odd integer. + // Raise divide-by-zero exception and get minus infinity value. + fldl MO(one) + fdivl MO(zero) + fchs + ret + +25: fstp %st(0) +26: +27: // Raise divide-by-zero exception and get infinity value. + fldl MO(one) + fdivl MO(zero) + ret + + .align ALIGNARG(4) + // x is ±0 and y is > 0. We must find out whether y is an odd integer. +21: testb $2, %dh + jz 22f + + // fistpll raises invalid exception for |y| >= 1L<<63, but y + // may be odd unless we know |y| >= 1L<<64. + fldl MO(p64) // 1L<<64 : y + fxch // y : 1L<<64 + fcomi %st(1), %st // y : 1L<<64 + fstp %st(1) // y + jnc 22f + fldl MO(p63) // p63 : y + fxch // y : p63 + fprem // y%p63 : p63 + fstp %st(1) // y%p63 + + fld %st // y : y + fistpll -8(%rsp) // y + fildll -8(%rsp) // int(y) : y + fucomip %st(1),%st + ffreep %st // <empty> + jne 23f + + // OK, the value is an integer, but is it odd? + mov -8(%rsp),%eax + mov -4(%rsp),%edx + andb $1, %al + jz 24f // jump if not odd + // It's an odd integer. + fldl MO(mzero) + ret + +22: fstp %st(0) +23: +24: fldl MO(zero) + ret + +END(__ieee754_powl) +strong_alias (__ieee754_powl, __powl_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_remainderl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_remainderl.S new file mode 100644 index 0000000000..4ee0910912 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_remainderl.S @@ -0,0 +1,21 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + +ENTRY(__ieee754_remainderl) + fldt 24(%rsp) + fldt 8(%rsp) +1: fprem1 + fstsw %ax + testl $0x400,%eax + jnz 1b + fstp %st(1) + ret +END (__ieee754_remainderl) +strong_alias (__ieee754_remainderl, __remainderl_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_scalbl.S b/REORG.TODO/sysdeps/x86_64/fpu/e_scalbl.S new file mode 100644 index 0000000000..2982dc3b9e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_scalbl.S @@ -0,0 +1,89 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de> + * + * Correct handling of y==-inf <drepper@gnu> + */ + +#include <machine/asm.h> + + .section .rodata + + .align ALIGNARG(4) + .type zero_nan,@object +zero_nan: + .double 0.0 +nan: .byte 0, 0, 0, 0, 0, 0, 0xff, 0x7f + .byte 0, 0, 0, 0, 0, 0, 0, 0x80 + .byte 0, 0, 0, 0, 0, 0, 0xff, 0x7f + ASM_SIZE_DIRECTIVE(zero_nan) + + +#ifdef PIC +# define MO(op) op##(%rip) +#else +# define MO(op) op +#endif + + .text +ENTRY(__ieee754_scalbl) + fldt 24(%rsp) + fxam + fnstsw + fldt 8(%rsp) + andl $0x4700, %eax + cmpl $0x0700, %eax + je 1f + andl $0x4500, %eax + cmpl $0x0100, %eax + je 2f + fxam + fnstsw + andl $0x4500, %eax + cmpl $0x0100, %eax + je 2f + fld %st(1) + frndint + fcomip %st(2), %st + jne 4f + fscale + fstp %st(1) + ret + + /* y is -inf */ +1: fxam + fnstsw + movl 16(%rsp), %edx + shrl $5, %eax + fstp %st + fstp %st + andl $0x8000, %edx + andl $0x0228, %eax + cmpl $0x0028, %eax + je 4f + andl $8, %eax + shrl $11, %edx + addl %edx, %eax +#ifdef PIC + lea zero_nan(%rip),%rdx + fldl (%rdx,%rax,1) +#else + fldl zero_nan(%rax, 1) +#endif + ret + + /* The result is NaN; raise an exception for sNaN arguments. */ +2: faddp + ret + + /* Return NaN and raise the invalid exception. */ +4: fstp %st + fstp %st + fldz + fdiv %st + ret +END(__ieee754_scalbl) +strong_alias (__ieee754_scalbl, __scalbl_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_sqrt.c b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrt.c new file mode 100644 index 0000000000..33b59f67c1 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrt.c @@ -0,0 +1,31 @@ +/* Square root of floating point number. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math_private.h> + +#undef __ieee754_sqrt +double +__ieee754_sqrt (double x) +{ + double res; + + asm ("sqrtsd %1, %0" : "=x" (res) : "xm" (x)); + + return res; +} +strong_alias (__ieee754_sqrt, __sqrt_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtf.c b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtf.c new file mode 100644 index 0000000000..386b903c43 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtf.c @@ -0,0 +1,31 @@ +/* Square root of floating point number. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math_private.h> + +#undef __ieee754_sqrtf +float +__ieee754_sqrtf (float x) +{ + float res; + + asm ("sqrtss %1, %0" : "=x" (res) : "xm" (x)); + + return res; +} +strong_alias (__ieee754_sqrtf, __sqrtf_finite) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtl.c b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtl.c new file mode 100644 index 0000000000..90e4e164e5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/e_sqrtl.c @@ -0,0 +1 @@ +#include "sysdeps/i386/fpu/e_sqrtl.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fclrexcpt.c b/REORG.TODO/sysdeps/x86_64/fpu/fclrexcpt.c new file mode 100644 index 0000000000..93bf0d341f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fclrexcpt.c @@ -0,0 +1,52 @@ +/* Clear given exceptions in current floating-point environment. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +feclearexcept (int excepts) +{ + fenv_t temp; + unsigned int mxcsr; + + /* Mask out unsupported bits/exceptions. */ + excepts &= FE_ALL_EXCEPT; + + /* Bah, we have to clear selected exceptions. Since there is no + `fldsw' instruction we have to do it the hard way. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Clear the relevant bits. */ + temp.__status_word &= excepts ^ FE_ALL_EXCEPT; + + /* Put the new data in effect. */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + + /* And the same procedure for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear the relevant bits. */ + mxcsr &= ~excepts; + + /* And put them into effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + + /* Success. */ + return 0; +} +libm_hidden_def (feclearexcept) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fedisblxcpt.c b/REORG.TODO/sysdeps/x86_64/fpu/fedisblxcpt.c new file mode 100644 index 0000000000..512987bd03 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fedisblxcpt.c @@ -0,0 +1,46 @@ +/* Disable floating-point exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2001. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fedisableexcept (int excepts) +{ + unsigned short int new_exc, old_exc; + unsigned int new; + + excepts &= FE_ALL_EXCEPT; + + /* Get the current control word of the x87 FPU. */ + __asm__ ("fstcw %0" : "=m" (*&new_exc)); + + old_exc = (~new_exc) & FE_ALL_EXCEPT; + + new_exc |= excepts; + __asm__ ("fldcw %0" : : "m" (*&new_exc)); + + /* And now the same for the SSE MXCSR register. */ + __asm__ ("stmxcsr %0" : "=m" (*&new)); + + /* The SSE exception masks are shifted by 7 bits. */ + new |= excepts << 7; + __asm__ ("ldmxcsr %0" : : "m" (*&new)); + + return old_exc; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/feenablxcpt.c b/REORG.TODO/sysdeps/x86_64/fpu/feenablxcpt.c new file mode 100644 index 0000000000..0985d71a00 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/feenablxcpt.c @@ -0,0 +1,46 @@ +/* Enable floating-point exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2001. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +feenableexcept (int excepts) +{ + unsigned short int new_exc, old_exc; + unsigned int new; + + excepts &= FE_ALL_EXCEPT; + + /* Get the current control word of the x87 FPU. */ + __asm__ ("fstcw %0" : "=m" (*&new_exc)); + + old_exc = (~new_exc) & FE_ALL_EXCEPT; + + new_exc &= ~excepts; + __asm__ ("fldcw %0" : : "m" (*&new_exc)); + + /* And now the same for the SSE MXCSR register. */ + __asm__ ("stmxcsr %0" : "=m" (*&new)); + + /* The SSE exception masks are shifted by 7 bits. */ + new &= ~(excepts << 7); + __asm__ ("ldmxcsr %0" : : "m" (*&new)); + + return old_exc; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fegetenv.c b/REORG.TODO/sysdeps/x86_64/fpu/fegetenv.c new file mode 100644 index 0000000000..af7642e990 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fegetenv.c @@ -0,0 +1,35 @@ +/* Store current floating-point environment. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__fegetenv (fenv_t *envp) +{ + __asm__ ("fnstenv %0\n" + /* fnstenv changes the exception mask, so load back the + stored environment. */ + "fldenv %0\n" + "stmxcsr %1" : "=m" (*envp), "=m" (envp->__mxcsr)); + + /* Success. */ + return 0; +} +libm_hidden_def (__fegetenv) +weak_alias (__fegetenv, fegetenv) +libm_hidden_weak (fegetenv) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fegetexcept.c b/REORG.TODO/sysdeps/x86_64/fpu/fegetexcept.c new file mode 100644 index 0000000000..7dbf40401e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fegetexcept.c @@ -0,0 +1,31 @@ +/* Get enabled floating-point exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2001. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fegetexcept (void) +{ + unsigned short int exc; + + /* Get the current control word. */ + __asm__ ("fstcw %0" : "=m" (*&exc)); + + return (~exc) & FE_ALL_EXCEPT; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fegetmode.c b/REORG.TODO/sysdeps/x86_64/fpu/fegetmode.c new file mode 100644 index 0000000000..4513f80c85 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fegetmode.c @@ -0,0 +1,28 @@ +/* Store current floating-point control modes. x86_64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <fpu_control.h> + +int +fegetmode (femode_t *modep) +{ + _FPU_GETCW (modep->__control_word); + __asm__ ("stmxcsr %0" : "=m" (modep->__mxcsr)); + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fegetround.c b/REORG.TODO/sysdeps/x86_64/fpu/fegetround.c new file mode 100644 index 0000000000..bff3eae102 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fegetround.c @@ -0,0 +1,35 @@ +/* Return current rounding direction. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__fegetround (void) +{ + int cw; + /* We only check the x87 FPU unit. The SSE unit should be the same + - and if it's not the same there's no way to signal it. */ + + __asm__ ("fnstcw %0" : "=m" (*&cw)); + + return cw & 0xc00; +} +libm_hidden_def (__fegetround) +weak_alias (__fegetround, fegetround) +libm_hidden_weak (fegetround) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/feholdexcpt.c b/REORG.TODO/sysdeps/x86_64/fpu/feholdexcpt.c new file mode 100644 index 0000000000..0a6c836f4f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/feholdexcpt.c @@ -0,0 +1,41 @@ +/* Store current floating-point environment and clear exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__feholdexcept (fenv_t *envp) +{ + unsigned int mxcsr; + + /* Store the environment. Recall that fnstenv has a side effect of + masking all exceptions. Then clear all exceptions. */ + __asm__ ("fnstenv %0\n\t" + "stmxcsr %1\n\t" + "fnclex" + : "=m" (*envp), "=m" (envp->__mxcsr)); + + /* Set the SSE MXCSR register. */ + mxcsr = (envp->__mxcsr | 0x1f80) & ~0x3f; + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + + return 0; +} +libm_hidden_def (__feholdexcept) +weak_alias (__feholdexcept, feholdexcept) +libm_hidden_weak (feholdexcept) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fesetenv.c b/REORG.TODO/sysdeps/x86_64/fpu/fesetenv.c new file mode 100644 index 0000000000..90164bf3d3 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fesetenv.c @@ -0,0 +1,114 @@ +/* Install given floating-point environment. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <fpu_control.h> +#include <assert.h> + + +/* All exceptions, including the x86-specific "denormal operand" + exception. */ +#define FE_ALL_EXCEPT_X86 (FE_ALL_EXCEPT | __FE_DENORM) + + +int +__fesetenv (const fenv_t *envp) +{ + fenv_t temp; + + /* Install the environment specified by ENVP. But there are a few + values which we do not want to come from the saved environment. + Therefore, we get the current environment and replace the values + we want to use from the environment specified by the parameter. */ + __asm__ ("fnstenv %0\n" + "stmxcsr %1" : "=m" (*&temp), "=m" (*&temp.__mxcsr)); + + if (envp == FE_DFL_ENV) + { + temp.__control_word |= FE_ALL_EXCEPT_X86; + temp.__control_word &= ~FE_TOWARDZERO; + temp.__control_word |= _FPU_EXTENDED; + temp.__status_word &= ~FE_ALL_EXCEPT_X86; + temp.__eip = 0; + temp.__cs_selector = 0; + temp.__opcode = 0; + temp.__data_offset = 0; + temp.__data_selector = 0; + /* Clear SSE exceptions. */ + temp.__mxcsr &= ~FE_ALL_EXCEPT_X86; + /* Set mask for SSE MXCSR. */ + temp.__mxcsr |= (FE_ALL_EXCEPT_X86 << 7); + /* Set rounding to FE_TONEAREST. */ + temp.__mxcsr &= ~ 0x6000; + temp.__mxcsr |= (FE_TONEAREST << 3); + /* Clear the FZ and DAZ bits. */ + temp.__mxcsr &= ~0x8040; + } + else if (envp == FE_NOMASK_ENV) + { + temp.__control_word &= ~(FE_ALL_EXCEPT | FE_TOWARDZERO); + /* Keep the "denormal operand" exception masked. */ + temp.__control_word |= __FE_DENORM; + temp.__control_word |= _FPU_EXTENDED; + temp.__status_word &= ~FE_ALL_EXCEPT_X86; + temp.__eip = 0; + temp.__cs_selector = 0; + temp.__opcode = 0; + temp.__data_offset = 0; + temp.__data_selector = 0; + /* Clear SSE exceptions. */ + temp.__mxcsr &= ~FE_ALL_EXCEPT_X86; + /* Set mask for SSE MXCSR. */ + /* Set rounding to FE_TONEAREST. */ + temp.__mxcsr &= ~ 0x6000; + temp.__mxcsr |= (FE_TONEAREST << 3); + /* Do not mask exceptions. */ + temp.__mxcsr &= ~(FE_ALL_EXCEPT << 7); + /* Keep the "denormal operand" exception masked. */ + temp.__mxcsr |= (__FE_DENORM << 7); + /* Clear the FZ and DAZ bits. */ + temp.__mxcsr &= ~0x8040; + } + else + { + temp.__control_word &= ~(FE_ALL_EXCEPT_X86 + | FE_TOWARDZERO + | _FPU_EXTENDED); + temp.__control_word |= (envp->__control_word + & (FE_ALL_EXCEPT_X86 + | FE_TOWARDZERO + | _FPU_EXTENDED)); + temp.__status_word &= ~FE_ALL_EXCEPT_X86; + temp.__status_word |= envp->__status_word & FE_ALL_EXCEPT_X86; + temp.__eip = envp->__eip; + temp.__cs_selector = envp->__cs_selector; + temp.__opcode = envp->__opcode; + temp.__data_offset = envp->__data_offset; + temp.__data_selector = envp->__data_selector; + temp.__mxcsr = envp->__mxcsr; + } + + __asm__ ("fldenv %0\n" + "ldmxcsr %1" : : "m" (temp), "m" (temp.__mxcsr)); + + /* Success. */ + return 0; +} +libm_hidden_def (__fesetenv) +weak_alias (__fesetenv, fesetenv) +libm_hidden_weak (fesetenv) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fesetexcept.c b/REORG.TODO/sysdeps/x86_64/fpu/fesetexcept.c new file mode 100644 index 0000000000..65683b5697 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fesetexcept.c @@ -0,0 +1,31 @@ +/* Set given exception flags. x86_64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fesetexcept (int excepts) +{ + unsigned int mxcsr; + + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + mxcsr |= excepts & FE_ALL_EXCEPT; + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fesetmode.c b/REORG.TODO/sysdeps/x86_64/fpu/fesetmode.c new file mode 100644 index 0000000000..27429f7887 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fesetmode.c @@ -0,0 +1,50 @@ +/* Install given floating-point control modes. x86_64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <fpu_control.h> + +/* All exceptions, including the x86-specific "denormal operand" + exception. */ +#define FE_ALL_EXCEPT_X86 (FE_ALL_EXCEPT | __FE_DENORM) + +int +fesetmode (const femode_t *modep) +{ + fpu_control_t cw; + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (mxcsr)); + /* Preserve SSE exception flags but restore other state in + MXCSR. */ + mxcsr &= FE_ALL_EXCEPT_X86; + if (modep == FE_DFL_MODE) + { + cw = _FPU_DEFAULT; + /* Default MXCSR state has all bits zero except for those + masking exceptions. */ + mxcsr |= FE_ALL_EXCEPT_X86 << 7; + } + else + { + cw = modep->__control_word; + mxcsr |= modep->__mxcsr & ~FE_ALL_EXCEPT_X86; + } + _FPU_SETCW (cw); + __asm__ ("ldmxcsr %0" : : "m" (mxcsr)); + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fesetround.c b/REORG.TODO/sysdeps/x86_64/fpu/fesetround.c new file mode 100644 index 0000000000..939297252a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fesetround.c @@ -0,0 +1,48 @@ +/* Set current rounding direction. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__fesetround (int round) +{ + unsigned short int cw; + int mxcsr; + + if ((round & ~0xc00) != 0) + /* ROUND is no valid rounding mode. */ + return 1; + + /* First set the x87 FPU. */ + asm ("fnstcw %0" : "=m" (*&cw)); + cw &= ~0xc00; + cw |= round; + asm ("fldcw %0" : : "m" (*&cw)); + + /* And now the MSCSR register for SSE, the precision is at different bit + positions in the different units, we need to shift it 3 bits. */ + asm ("stmxcsr %0" : "=m" (*&mxcsr)); + mxcsr &= ~ 0x6000; + mxcsr |= round << 3; + asm ("ldmxcsr %0" : : "m" (*&mxcsr)); + + return 0; +} +libm_hidden_def (__fesetround) +weak_alias (__fesetround, fesetround) +libm_hidden_weak (fesetround) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/feupdateenv.c b/REORG.TODO/sysdeps/x86_64/fpu/feupdateenv.c new file mode 100644 index 0000000000..3bc110ce48 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/feupdateenv.c @@ -0,0 +1,52 @@ +/* Install given floating-point environment and raise exceptions. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__feupdateenv (const fenv_t *envp) +{ + fexcept_t temp; + unsigned int xtemp; + + /* Save current exceptions. */ + __asm__ ("fnstsw %0\n\tstmxcsr %1" : "=m" (*&temp), "=m" (xtemp)); + temp = (temp | xtemp) & FE_ALL_EXCEPT; + + /* Install new environment. */ + __fesetenv (envp); + + /* Raise the saved exception. Incidently for us the implementation + defined format of the values in objects of type fexcept_t is the + same as the ones specified using the FE_* constants. */ + __feraiseexcept ((int) temp); + + /* Success. */ + return 0; +} + +#include <shlib-compat.h> +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__feupdateenv, __old_feupdateenv) +compat_symbol (libm, __old_feupdateenv, feupdateenv, GLIBC_2_1); +#endif + +libm_hidden_def (__feupdateenv) +libm_hidden_ver (__feupdateenv, feupdateenv) +versioned_symbol (libm, __feupdateenv, feupdateenv, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fgetexcptflg.c b/REORG.TODO/sysdeps/x86_64/fpu/fgetexcptflg.c new file mode 100644 index 0000000000..c1a0c2f872 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fgetexcptflg.c @@ -0,0 +1,35 @@ +/* Store current representation for exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fegetexceptflag (fexcept_t *flagp, int excepts) +{ + fexcept_t temp; + unsigned int mxscr; + + /* Get the current exceptions for the x87 FPU and SSE unit. */ + __asm__ ("fnstsw %0\n" + "stmxcsr %1" : "=m" (*&temp), "=m" (*&mxscr)); + + *flagp = (temp | mxscr) & FE_ALL_EXCEPT & excepts; + + /* Success. */ + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fraiseexcpt.c b/REORG.TODO/sysdeps/x86_64/fpu/fraiseexcpt.c new file mode 100644 index 0000000000..13eb4af331 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fraiseexcpt.c @@ -0,0 +1,121 @@ +/* Raise given exceptions. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <math.h> + +int +__feraiseexcept (int excepts) +{ + /* Raise exceptions represented by EXPECTS. But we must raise only + one signal at a time. It is important that if the overflow/underflow + exception and the inexact exception are given at the same time, + the overflow/underflow exception follows the inexact exception. */ + + /* First: invalid exception. */ + if ((FE_INVALID & excepts) != 0) + { + /* One example of an invalid operation is 0.0 / 0.0. */ + float f = 0.0; + + __asm__ __volatile__ ("divss %0, %0 " : : "x" (f)); + (void) &f; + } + + /* Next: division by zero. */ + if ((FE_DIVBYZERO & excepts) != 0) + { + float f = 1.0; + float g = 0.0; + + __asm__ __volatile__ ("divss %1, %0" : : "x" (f), "x" (g)); + (void) &f; + } + + /* Next: overflow. */ + if ((FE_OVERFLOW & excepts) != 0) + { + /* XXX: Is it ok to only set the x87 FPU? */ + /* There is no way to raise only the overflow flag. Do it the + hard way. */ + fenv_t temp; + + /* Bah, we have to clear selected exceptions. Since there is no + `fldsw' instruction we have to do it the hard way. */ + __asm__ __volatile__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set the relevant bits. */ + temp.__status_word |= FE_OVERFLOW; + + /* Put the new data in effect. */ + __asm__ __volatile__ ("fldenv %0" : : "m" (*&temp)); + + /* And raise the exception. */ + __asm__ __volatile__ ("fwait"); + } + + /* Next: underflow. */ + if ((FE_UNDERFLOW & excepts) != 0) + { + /* XXX: Is it ok to only set the x87 FPU? */ + /* There is no way to raise only the underflow flag. Do it the + hard way. */ + fenv_t temp; + + /* Bah, we have to clear selected exceptions. Since there is no + `fldsw' instruction we have to do it the hard way. */ + __asm__ __volatile__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set the relevant bits. */ + temp.__status_word |= FE_UNDERFLOW; + + /* Put the new data in effect. */ + __asm__ __volatile__ ("fldenv %0" : : "m" (*&temp)); + + /* And raise the exception. */ + __asm__ __volatile__ ("fwait"); + } + + /* Last: inexact. */ + if ((FE_INEXACT & excepts) != 0) + { + /* XXX: Is it ok to only set the x87 FPU? */ + /* There is no way to raise only the inexact flag. Do it the + hard way. */ + fenv_t temp; + + /* Bah, we have to clear selected exceptions. Since there is no + `fldsw' instruction we have to do it the hard way. */ + __asm__ __volatile__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set the relevant bits. */ + temp.__status_word |= FE_INEXACT; + + /* Put the new data in effect. */ + __asm__ __volatile__ ("fldenv %0" : : "m" (*&temp)); + + /* And raise the exception. */ + __asm__ __volatile__ ("fwait"); + } + + /* Success. */ + return 0; +} +libm_hidden_def (__feraiseexcept) +weak_alias (__feraiseexcept, feraiseexcept) +libm_hidden_weak (feraiseexcept) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/fsetexcptflg.c b/REORG.TODO/sysdeps/x86_64/fpu/fsetexcptflg.c new file mode 100644 index 0000000000..ffc44dcad5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -0,0 +1,53 @@ +/* Set floating-point environment exception handling. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <math.h> + +int +fesetexceptflag (const fexcept_t *flagp, int excepts) +{ + fenv_t temp; + unsigned int mxcsr; + + /* XXX: Do we really need to set both the exception in both units? + Shouldn't it be enough to set only the SSE unit? */ + + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); + temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + + /* Store the new status word (along with the rest of the environment. + Possibly new exceptions are set but they won't get executed unless + the next floating-point instruction. */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + + /* And now the same for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + mxcsr &= ~(excepts & FE_ALL_EXCEPT); + mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + + /* Success. */ + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/ftestexcept.c b/REORG.TODO/sysdeps/x86_64/fpu/ftestexcept.c new file mode 100644 index 0000000000..502bdb2c42 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/ftestexcept.c @@ -0,0 +1,33 @@ +/* Test exception in current environment. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fetestexcept (int excepts) +{ + int temp; + unsigned int mxscr; + + /* Get current exceptions. */ + __asm__ ("fnstsw %0\n" + "stmxcsr %1" : "=m" (*&temp), "=m" (*&mxscr)); + + return (temp | mxscr) & excepts & FE_ALL_EXCEPT; +} +libm_hidden_def (fetestexcept) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps b/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps new file mode 100644 index 0000000000..61da961a57 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps @@ -0,0 +1,2368 @@ +# Begin of automatic generation + +# Maximal error of functions: +Function: "acos": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "acos_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "acos_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "acos_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "acosh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "acosh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "acosh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "acosh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "asin": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "asin_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "asin_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "asin_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "asinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "asinh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "asinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "asinh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "atan": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan2": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan2_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "atan2_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "atan2_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "atan_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "atan_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "atanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "atanh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "atanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "atanh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "cabs": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_downward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_towardzero": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_upward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cacos": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "cacos": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacos_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 6 +ldouble: 6 + +Function: Real part of "cacos_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "cacos_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos_upward": +double: 5 +float: 7 +idouble: 5 +ifloat: 7 +ildouble: 7 +ldouble: 7 + +Function: Real part of "cacosh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacosh": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cacosh_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "cacosh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacosh_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_upward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "carg": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "carg_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "carg_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "carg_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "casin": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "casin": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "casin_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "casin_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 6 +ldouble: 6 + +Function: Real part of "casin_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "casin_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "casin_upward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "casin_upward": +double: 5 +float: 7 +idouble: 5 +ifloat: 7 +ildouble: 7 +ldouble: 7 + +Function: Real part of "casinh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "casinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "casinh_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "casinh_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "casinh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "casinh_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "casinh_upward": +double: 5 +float: 7 +idouble: 5 +ifloat: 7 +ildouble: 7 +ldouble: 7 + +Function: Imaginary part of "casinh_upward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "catan": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catan_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Real part of "catan_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Real part of "catan_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "catanh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catanh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catanh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "catanh_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "catanh_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catanh_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "catanh_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_downward": +double: 4 +float: 1 +idouble: 4 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_upward": +double: 5 +float: 1 +idouble: 5 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccos": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "ccos": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccos_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccos_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ccos_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccos_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ccos_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccos_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "ccosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccosh_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccosh_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ccosh_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccosh_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ccosh_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccosh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cexp": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "cexp": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cexp_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cexp_downward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "cexp_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cexp_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "cexp_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cexp_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "clog": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "clog10": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "clog10": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "clog10_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 8 +ldouble: 8 + +Function: Imaginary part of "clog10_downward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog10_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: Imaginary part of "clog10_towardzero": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog10_upward": +double: 6 +float: 5 +idouble: 6 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: Imaginary part of "clog10_upward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog_downward": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "clog_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "clog_towardzero": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "clog_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 1 +ldouble: 1 + +Function: Real part of "clog_upward": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "clog_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "cos": +ildouble: 1 +ldouble: 1 + +Function: "cos_downward": +double: 1 +idouble: 1 +ildouble: 3 +ldouble: 3 + +Function: "cos_towardzero": +double: 1 +idouble: 1 +ildouble: 2 +ldouble: 2 + +Function: "cos_upward": +double: 1 +idouble: 1 +ildouble: 2 +ldouble: 2 + +Function: "cos_vlen16": +float: 1 + +Function: "cos_vlen2": +double: 2 + +Function: "cos_vlen4": +double: 2 +float: 1 + +Function: "cos_vlen4_avx2": +double: 2 + +Function: "cos_vlen8": +double: 1 +float: 1 + +Function: "cos_vlen8_avx2": +float: 1 + +Function: "cosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "cosh_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 3 + +Function: "cosh_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "cosh_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 3 + +Function: Real part of "cpow": +double: 2 +float: 5 +idouble: 2 +ifloat: 5 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cpow": +float: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Real part of "cpow_downward": +double: 4 +float: 8 +idouble: 4 +ifloat: 8 +ildouble: 7 +ldouble: 7 + +Function: Imaginary part of "cpow_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cpow_towardzero": +double: 4 +float: 8 +idouble: 4 +ifloat: 8 +ildouble: 7 +ldouble: 7 + +Function: Imaginary part of "cpow_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cpow_upward": +double: 4 +float: 1 +idouble: 4 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cpow_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csin": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "csin_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csin_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csin_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csin_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csin_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csin_upward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csinh": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "csinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "csinh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csinh_upward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csqrt": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "csqrt": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csqrt_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "csqrt_downward": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Real part of "csqrt_towardzero": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "csqrt_towardzero": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Real part of "csqrt_upward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "csqrt_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Real part of "ctan": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ctan": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ctan_downward": +double: 6 +float: 5 +idouble: 6 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctan_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Real part of "ctan_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctan_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Real part of "ctan_upward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ctan_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "ctanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ctanh_downward": +double: 4 +float: 2 +idouble: 4 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "ctanh_downward": +double: 6 +float: 5 +idouble: 6 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: Real part of "ctanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "ctanh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctanh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ctanh_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: "erf": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erf_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erf_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erf_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erfc": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "erfc_downward": +double: 5 +float: 6 +idouble: 5 +ifloat: 6 +ildouble: 4 +ldouble: 4 + +Function: "erfc_towardzero": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "erfc_upward": +double: 5 +float: 6 +idouble: 5 +ifloat: 6 +ildouble: 5 +ldouble: 5 + +Function: "exp": +ildouble: 1 +ldouble: 1 + +Function: "exp10": +double: 2 +idouble: 2 +ildouble: 1 +ldouble: 1 + +Function: "exp10_downward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "exp10_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "exp10_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "exp2": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp_downward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp_towardzero": +double: 1 +idouble: 1 +ildouble: 2 +ldouble: 2 + +Function: "exp_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp_vlen16": +float: 1 + +Function: "exp_vlen2": +double: 1 + +Function: "exp_vlen4": +double: 1 +float: 1 + +Function: "exp_vlen4_avx2": +double: 1 + +Function: "exp_vlen8": +double: 1 +float: 1 + +Function: "exp_vlen8_avx2": +float: 1 + +Function: "expm1": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "expm1_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 4 +ldouble: 4 + +Function: "expm1_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "expm1_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 4 +ldouble: 4 + +Function: "gamma": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "gamma_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 7 +ldouble: 7 + +Function: "gamma_towardzero": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 7 +ldouble: 7 + +Function: "gamma_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: "hypot": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_downward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_towardzero": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_upward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "j0": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "j0_downward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "j0_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "j0_upward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "j1": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "j1_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "j1_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "j1_upward": +double: 3 +float: 5 +idouble: 3 +ifloat: 5 +ildouble: 3 +ldouble: 3 + +Function: "jn": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "jn_downward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: "jn_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "jn_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "lgamma": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "lgamma_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 7 +ldouble: 7 + +Function: "lgamma_towardzero": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 7 +ldouble: 7 + +Function: "lgamma_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: "log": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "log10": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log10_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: "log10_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "log10_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log1p": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "log1p_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "log1p_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "log1p_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "log2": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "log2_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 1 +ldouble: 1 + +Function: "log2_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log2_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 1 +ldouble: 1 + +Function: "log_downward": +float: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "log_towardzero": +float: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "log_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log_vlen16": +float: 3 + +Function: "log_vlen2": +double: 1 + +Function: "log_vlen4": +double: 1 +float: 3 + +Function: "log_vlen4_avx2": +double: 1 + +Function: "log_vlen8": +double: 1 +float: 3 + +Function: "log_vlen8_avx2": +float: 2 + +Function: "pow": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "pow10": +double: 2 +idouble: 2 +ildouble: 1 +ldouble: 1 + +Function: "pow10_downward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "pow10_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "pow10_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "pow_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 4 +ldouble: 4 + +Function: "pow_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 4 +ldouble: 4 + +Function: "pow_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 4 +ldouble: 4 + +Function: "pow_vlen16": +float: 3 + +Function: "pow_vlen2": +double: 1 + +Function: "pow_vlen4": +double: 1 +float: 3 + +Function: "pow_vlen4_avx2": +double: 1 + +Function: "pow_vlen8": +double: 1 +float: 3 + +Function: "pow_vlen8_avx2": +float: 3 + +Function: "sin": +ildouble: 1 +ldouble: 1 + +Function: "sin_downward": +double: 1 +idouble: 1 +ildouble: 3 +ldouble: 3 + +Function: "sin_towardzero": +double: 1 +idouble: 1 +ildouble: 2 +ldouble: 2 + +Function: "sin_upward": +double: 1 +idouble: 1 +ildouble: 3 +ldouble: 3 + +Function: "sin_vlen16": +float: 1 + +Function: "sin_vlen2": +double: 2 + +Function: "sin_vlen4": +double: 2 +float: 1 + +Function: "sin_vlen4_avx2": +double: 2 + +Function: "sin_vlen8": +double: 2 +float: 1 + +Function: "sin_vlen8_avx2": +float: 1 + +Function: "sincos": +ildouble: 1 +ldouble: 1 + +Function: "sincos_downward": +double: 1 +idouble: 1 +ildouble: 3 +ldouble: 3 + +Function: "sincos_towardzero": +double: 1 +idouble: 1 +ildouble: 2 +ldouble: 2 + +Function: "sincos_upward": +double: 1 +idouble: 1 +ildouble: 3 +ldouble: 3 + +Function: "sincos_vlen16": +float: 1 + +Function: "sincos_vlen2": +double: 2 + +Function: "sincos_vlen4": +double: 2 +float: 1 + +Function: "sincos_vlen4_avx2": +double: 2 + +Function: "sincos_vlen8": +double: 1 +float: 1 + +Function: "sincos_vlen8_avx2": +float: 1 + +Function: "sinh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "sinh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "sinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "sinh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "tan": +float: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "tan_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "tan_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "tan_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "tanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "tanh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "tanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "tanh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "tgamma": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "tgamma_downward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "tgamma_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "tgamma_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "y0": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "y0_downward": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "y0_towardzero": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "y0_upward": +double: 3 +float: 5 +idouble: 3 +ifloat: 5 +ildouble: 3 +ldouble: 3 + +Function: "y1": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "y1_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 7 +ldouble: 7 + +Function: "y1_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "y1_upward": +double: 7 +float: 2 +idouble: 7 +ifloat: 2 +ildouble: 7 +ldouble: 7 + +Function: "yn": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "yn_downward": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "yn_towardzero": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "yn_upward": +double: 4 +float: 5 +idouble: 4 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +# end of automatic generation diff --git a/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps-name b/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps-name new file mode 100644 index 0000000000..1c09346681 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/libm-test-ulps-name @@ -0,0 +1 @@ +x86_64 diff --git a/REORG.TODO/sysdeps/x86_64/fpu/math-tests-arch.h b/REORG.TODO/sysdeps/x86_64/fpu/math-tests-arch.h new file mode 100644 index 0000000000..9278e3440b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/math-tests-arch.h @@ -0,0 +1,53 @@ +/* Runtime architecture check for math tests. x86_64 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <cpu-features.h> + +#if defined REQUIRE_AVX + +# define INIT_ARCH_EXT +# define CHECK_ARCH_EXT \ + do \ + { \ + if (!HAS_ARCH_FEATURE (AVX_Usable)) return; \ + } \ + while (0) + +#elif defined REQUIRE_AVX2 + +# define INIT_ARCH_EXT +# define CHECK_ARCH_EXT \ + do \ + { \ + if (!HAS_ARCH_FEATURE (AVX2_Usable)) return; \ + } \ + while (0) + +#elif defined REQUIRE_AVX512F + +# define INIT_ARCH_EXT +# define CHECK_ARCH_EXT \ + do \ + { \ + if (!HAS_ARCH_FEATURE (AVX512F_Usable)) return; \ + } \ + while (0) + +#else +# include <sysdeps/generic/math-tests-arch.h> +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/math_ldbl.h b/REORG.TODO/sysdeps/x86_64/fpu/math_ldbl.h new file mode 100644 index 0000000000..6c5bc13455 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/math_ldbl.h @@ -0,0 +1,100 @@ +/* Manipulation of the bit representation of 'long double' quantities. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _MATH_LDBL_H_ +#define _MATH_LDBL_H_ 1 + +#include <stdint.h> + +/* A union which permits us to convert between a long double and + three 32 bit ints. */ + +typedef union +{ + long double value; + struct + { + uint32_t lsw; + uint32_t msw; + int sign_exponent:16; + unsigned int empty1:16; + unsigned int empty0:32; + } parts; +} ieee_long_double_shape_type; + +/* Get three 32 bit ints from a double. */ + +#define GET_LDOUBLE_WORDS(exp,ix0,ix1,d) \ +do { \ + ieee_long_double_shape_type ew_u; \ + ew_u.value = (d); \ + (exp) = ew_u.parts.sign_exponent; \ + (ix0) = ew_u.parts.msw; \ + (ix1) = ew_u.parts.lsw; \ +} while (0) + +/* Set a double from two 32 bit ints. */ + +#define SET_LDOUBLE_WORDS(d,exp,ix0,ix1) \ +do { \ + ieee_long_double_shape_type iw_u; \ + iw_u.parts.sign_exponent = (exp); \ + iw_u.parts.msw = (ix0); \ + iw_u.parts.lsw = (ix1); \ + (d) = iw_u.value; \ +} while (0) + +/* Get the more significant 32 bits of a long double mantissa. */ + +#define GET_LDOUBLE_MSW(v,d) \ +do { \ + ieee_long_double_shape_type sh_u; \ + sh_u.value = (d); \ + (v) = sh_u.parts.msw; \ +} while (0) + +/* Set the more significant 32 bits of a long double mantissa from an int. */ + +#define SET_LDOUBLE_MSW(d,v) \ +do { \ + ieee_long_double_shape_type sh_u; \ + sh_u.value = (d); \ + sh_u.parts.msw = (v); \ + (d) = sh_u.value; \ +} while (0) + +/* Get int from the exponent of a long double. */ + +#define GET_LDOUBLE_EXP(exp,d) \ +do { \ + ieee_long_double_shape_type ge_u; \ + ge_u.value = (d); \ + (exp) = ge_u.parts.sign_exponent; \ +} while (0) + +/* Set exponent of a long double from an int. */ + +#define SET_LDOUBLE_EXP(d,exp) \ +do { \ + ieee_long_double_shape_type se_u; \ + se_u.value = (d); \ + se_u.parts.sign_exponent = (exp); \ + (d) = se_u.value; \ +} while (0) + +#endif /* math_ldbl.h */ diff --git a/REORG.TODO/sysdeps/x86_64/fpu/math_private.h b/REORG.TODO/sysdeps/x86_64/fpu/math_private.h new file mode 100644 index 0000000000..027a6a3a4d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/math_private.h @@ -0,0 +1,133 @@ +#ifndef X86_64_MATH_PRIVATE_H +#define X86_64_MATH_PRIVATE_H 1 + +/* We can do a few things better on x86-64. */ + +#if defined __AVX__ || defined SSE2AVX +# define MOVD "vmovd" +# define MOVQ "vmovq" +#else +# define MOVD "movd" +# define MOVQ "movq" +#endif + +/* Direct movement of float into integer register. */ +#define EXTRACT_WORDS64(i, d) \ + do { \ + int64_t i_; \ + asm (MOVQ " %1, %0" : "=rm" (i_) : "x" ((double) (d))); \ + (i) = i_; \ + } while (0) + +/* And the reverse. */ +#define INSERT_WORDS64(d, i) \ + do { \ + int64_t i_ = i; \ + double d__; \ + asm (MOVQ " %1, %0" : "=x" (d__) : "rm" (i_)); \ + d = d__; \ + } while (0) + +/* Direct movement of float into integer register. */ +#define GET_FLOAT_WORD(i, d) \ + do { \ + int i_; \ + asm (MOVD " %1, %0" : "=rm" (i_) : "x" ((float) (d))); \ + (i) = i_; \ + } while (0) + +/* And the reverse. */ +#define SET_FLOAT_WORD(f, i) \ + do { \ + int i_ = i; \ + float f__; \ + asm (MOVD " %1, %0" : "=x" (f__) : "rm" (i_)); \ + f = f__; \ + } while (0) + +#include <sysdeps/i386/fpu/fenv_private.h> +#include_next <math_private.h> + +extern __always_inline double +__ieee754_sqrt (double d) +{ + double res; +#if defined __AVX__ || defined SSE2AVX + asm ("vsqrtsd %1, %0, %0" : "=x" (res) : "xm" (d)); +#else + asm ("sqrtsd %1, %0" : "=x" (res) : "xm" (d)); +#endif + return res; +} + +extern __always_inline float +__ieee754_sqrtf (float d) +{ + float res; +#if defined __AVX__ || defined SSE2AVX + asm ("vsqrtss %1, %0, %0" : "=x" (res) : "xm" (d)); +#else + asm ("sqrtss %1, %0" : "=x" (res) : "xm" (d)); +#endif + return res; +} + +extern __always_inline long double +__ieee754_sqrtl (long double d) +{ + long double res; + asm ("fsqrt" : "=t" (res) : "0" (d)); + return res; +} + +#ifdef __SSE4_1__ +extern __always_inline double +__rint (double d) +{ + double res; +# if defined __AVX__ || defined SSE2AVX + asm ("vroundsd $4, %1, %0, %0" : "=x" (res) : "xm" (d)); +# else + asm ("roundsd $4, %1, %0" : "=x" (res) : "xm" (d)); +# endif + return res; +} + +extern __always_inline float +__rintf (float d) +{ + float res; +# if defined __AVX__ || defined SSE2AVX + asm ("vroundss $4, %1, %0, %0" : "=x" (res) : "xm" (d)); +# else + asm ("roundss $4, %1, %0" : "=x" (res) : "xm" (d)); +# endif + return res; +} + +extern __always_inline double +__floor (double d) +{ + double res; +# if defined __AVX__ || defined SSE2AVX + asm ("vroundsd $1, %1, %0, %0" : "=x" (res) : "xm" (d)); +# else + asm ("roundsd $1, %1, %0" : "=x" (res) : "xm" (d)); +# endif + return res; +} + +extern __always_inline float +__floorf (float d) +{ + float res; +# if defined __AVX__ || defined SSE2AVX + asm ("vroundss $1, %1, %0, %0" : "=x" (res) : "xm" (d)); +# else + asm ("roundss $1, %1, %0" : "=x" (res) : "xm" (d)); +# endif + return res; +} +#endif /* __SSE4_1__ */ + +#endif /* X86_64_MATH_PRIVATE_H */ diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/Makefile b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/Makefile new file mode 100644 index 0000000000..34542155aa --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/Makefile @@ -0,0 +1,70 @@ +ifeq ($(subdir),math) +libm-sysdep_routines += s_floor-c s_ceil-c s_floorf-c s_ceilf-c \ + s_rint-c s_rintf-c s_nearbyint-c s_nearbyintf-c + +libm-sysdep_routines += e_exp-fma4 e_log-fma4 e_pow-fma4 s_atan-fma4 \ + e_asin-fma4 e_atan2-fma4 s_sin-fma4 s_tan-fma4 \ + mplog-fma4 mpa-fma4 slowexp-fma4 slowpow-fma4 \ + sincos32-fma4 doasin-fma4 dosincos-fma4 \ + halfulp-fma4 mpexp-fma4 \ + mpatan2-fma4 mpatan-fma4 mpsqrt-fma4 mptan-fma4 + +CFLAGS-doasin-fma4.c = -mfma4 +CFLAGS-dosincos-fma4.c = -mfma4 +CFLAGS-e_asin-fma4.c = -mfma4 +CFLAGS-e_atan2-fma4.c = -mfma4 +CFLAGS-e_exp-fma4.c = -mfma4 +CFLAGS-e_log-fma4.c = -mfma4 +CFLAGS-e_pow-fma4.c = -mfma4 $(config-cflags-nofma) +CFLAGS-halfulp-fma4.c = -mfma4 +CFLAGS-mpa-fma4.c = -mfma4 +CFLAGS-mpatan-fma4.c = -mfma4 +CFLAGS-mpatan2-fma4.c = -mfma4 +CFLAGS-mpexp-fma4.c = -mfma4 +CFLAGS-mplog-fma4.c = -mfma4 +CFLAGS-mpsqrt-fma4.c = -mfma4 +CFLAGS-mptan-fma4.c = -mfma4 +CFLAGS-s_atan-fma4.c = -mfma4 +CFLAGS-sincos32-fma4.c = -mfma4 +CFLAGS-slowexp-fma4.c = -mfma4 +CFLAGS-slowpow-fma4.c = -mfma4 +CFLAGS-s_sin-fma4.c = -mfma4 +CFLAGS-s_tan-fma4.c = -mfma4 + +libm-sysdep_routines += e_exp-avx e_log-avx s_atan-avx \ + e_atan2-avx s_sin-avx s_tan-avx \ + mplog-avx mpa-avx slowexp-avx \ + mpexp-avx + +CFLAGS-e_atan2-avx.c = -msse2avx -DSSE2AVX +CFLAGS-e_exp-avx.c = -msse2avx -DSSE2AVX +CFLAGS-e_log-avx.c = -msse2avx -DSSE2AVX +CFLAGS-mpa-avx.c = -msse2avx -DSSE2AVX +CFLAGS-mpexp-avx.c = -msse2avx -DSSE2AVX +CFLAGS-mplog-avx.c = -msse2avx -DSSE2AVX +CFLAGS-s_atan-avx.c = -msse2avx -DSSE2AVX +CFLAGS-s_sin-avx.c = -msse2avx -DSSE2AVX +CFLAGS-slowexp-avx.c = -msse2avx -DSSE2AVX +CFLAGS-s_tan-avx.c = -msse2avx -DSSE2AVX +endif + +ifeq ($(subdir),mathvec) +libmvec-sysdep_routines += svml_d_cos2_core_sse4 svml_d_cos4_core_avx2 \ + svml_d_cos8_core_avx512 svml_d_sin2_core_sse4 \ + svml_d_sin4_core_avx2 svml_d_sin8_core_avx512 \ + svml_d_log2_core_sse4 svml_d_log4_core_avx2 \ + svml_d_log8_core_avx512 svml_d_sincos2_core_sse4 \ + svml_d_sincos4_core_avx2 svml_d_sincos8_core_avx512 \ + svml_s_cosf4_core_sse4 svml_s_cosf8_core_avx2 \ + svml_s_cosf16_core_avx512 svml_s_sinf4_core_sse4 \ + svml_s_sinf8_core_avx2 svml_s_sinf16_core_avx512 \ + svml_s_logf4_core_sse4 svml_s_logf8_core_avx2 \ + svml_s_logf16_core_avx512 svml_d_exp2_core_sse4 \ + svml_d_exp4_core_avx2 svml_d_exp8_core_avx512 \ + svml_s_expf4_core_sse4 svml_s_expf8_core_avx2 \ + svml_s_expf16_core_avx512 svml_d_pow2_core_sse4 \ + svml_d_pow4_core_avx2 svml_d_pow8_core_avx512 \ + svml_s_powf4_core_sse4 svml_s_powf8_core_avx2 \ + svml_s_powf16_core_avx512 svml_s_sincosf4_core_sse4 \ + svml_s_sincosf8_core_avx2 svml_s_sincosf16_core_avx512 +endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/doasin-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/doasin-fma4.c new file mode 100644 index 0000000000..53eb419472 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/doasin-fma4.c @@ -0,0 +1,4 @@ +#define __doasin __doasin_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/doasin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/dosincos-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/dosincos-fma4.c new file mode 100644 index 0000000000..1578b2fce0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/dosincos-fma4.c @@ -0,0 +1,6 @@ +#define __docos __docos_fma4 +#define __dubcos __dubcos_fma4 +#define __dubsin __dubsin_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/dosincos.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin-fma4.c new file mode 100644 index 0000000000..2657c31f49 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin-fma4.c @@ -0,0 +1,11 @@ +#define __ieee754_acos __ieee754_acos_fma4 +#define __ieee754_asin __ieee754_asin_fma4 +#define __cos32 __cos32_fma4 +#define __doasin __doasin_fma4 +#define __docos __docos_fma4 +#define __dubcos __dubcos_fma4 +#define __dubsin __dubsin_fma4 +#define __sin32 __sin32_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/e_asin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin.c new file mode 100644 index 0000000000..111a5b99bd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_asin.c @@ -0,0 +1,26 @@ +#include <init-arch.h> +#include <math.h> +#include <math_private.h> + +extern double __ieee754_acos_sse2 (double); +extern double __ieee754_asin_sse2 (double); +extern double __ieee754_acos_fma4 (double); +extern double __ieee754_asin_fma4 (double); + +libm_ifunc (__ieee754_acos, + HAS_ARCH_FEATURE (FMA4_Usable) + ? __ieee754_acos_fma4 + : __ieee754_acos_sse2); +strong_alias (__ieee754_acos, __acos_finite) + +libm_ifunc (__ieee754_asin, + HAS_ARCH_FEATURE (FMA4_Usable) + ? __ieee754_asin_fma4 + : __ieee754_asin_sse2); +strong_alias (__ieee754_asin, __asin_finite) + +#define __ieee754_acos __ieee754_acos_sse2 +#define __ieee754_asin __ieee754_asin_sse2 + + +#include <sysdeps/ieee754/dbl-64/e_asin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-avx.c new file mode 100644 index 0000000000..3012afac37 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-avx.c @@ -0,0 +1,9 @@ +#define __ieee754_atan2 __ieee754_atan2_avx +#define __add __add_avx +#define __dbl_mp __dbl_mp_avx +#define __dvd __dvd_avx +#define __mul __mul_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/e_atan2.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-fma4.c new file mode 100644 index 0000000000..f4e986293e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2-fma4.c @@ -0,0 +1,10 @@ +#define __ieee754_atan2 __ieee754_atan2_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __dvd __dvd_fma4 +#define __mpatan2 __mpatan2_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/e_atan2.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2.c new file mode 100644 index 0000000000..9ca3c02a44 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_atan2.c @@ -0,0 +1,18 @@ +#include <init-arch.h> +#include <math.h> +#include <math_private.h> + +extern double __ieee754_atan2_sse2 (double, double); +extern double __ieee754_atan2_avx (double, double); +extern double __ieee754_atan2_fma4 (double, double); + +libm_ifunc (__ieee754_atan2, + HAS_ARCH_FEATURE (FMA4_Usable) ? __ieee754_atan2_fma4 + : (HAS_ARCH_FEATURE (AVX_Usable) + ? __ieee754_atan2_avx : __ieee754_atan2_sse2)); +strong_alias (__ieee754_atan2, __atan2_finite) + +#define __ieee754_atan2 __ieee754_atan2_sse2 + + +#include <sysdeps/ieee754/dbl-64/e_atan2.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-avx.c new file mode 100644 index 0000000000..ee5dd6d2dc --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-avx.c @@ -0,0 +1,6 @@ +#define __ieee754_exp __ieee754_exp_avx +#define __exp1 __exp1_avx +#define __slowexp __slowexp_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/e_exp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c new file mode 100644 index 0000000000..ae6eb67603 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c @@ -0,0 +1,6 @@ +#define __ieee754_exp __ieee754_exp_fma4 +#define __exp1 __exp1_fma4 +#define __slowexp __slowexp_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/e_exp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp.c new file mode 100644 index 0000000000..b7d7b5ff27 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_exp.c @@ -0,0 +1,18 @@ +#include <init-arch.h> +#include <math.h> +#include <math_private.h> + +extern double __ieee754_exp_sse2 (double); +extern double __ieee754_exp_avx (double); +extern double __ieee754_exp_fma4 (double); + +libm_ifunc (__ieee754_exp, + HAS_ARCH_FEATURE (FMA4_Usable) ? __ieee754_exp_fma4 + : (HAS_ARCH_FEATURE (AVX_Usable) + ? __ieee754_exp_avx : __ieee754_exp_sse2)); +strong_alias (__ieee754_exp, __exp_finite) + +#define __ieee754_exp __ieee754_exp_sse2 + + +#include <sysdeps/ieee754/dbl-64/e_exp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-avx.c new file mode 100644 index 0000000000..c669019bc2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-avx.c @@ -0,0 +1,8 @@ +#define __ieee754_log __ieee754_log_avx +#define __mplog __mplog_avx +#define __add __add_avx +#define __dbl_mp __dbl_mp_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/e_log.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-fma4.c new file mode 100644 index 0000000000..a2346cc618 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log-fma4.c @@ -0,0 +1,8 @@ +#define __ieee754_log __ieee754_log_fma4 +#define __mplog __mplog_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/e_log.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log.c new file mode 100644 index 0000000000..cf9533d6c0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_log.c @@ -0,0 +1,18 @@ +#include <init-arch.h> +#include <math.h> +#include <math_private.h> + +extern double __ieee754_log_sse2 (double); +extern double __ieee754_log_avx (double); +extern double __ieee754_log_fma4 (double); + +libm_ifunc (__ieee754_log, + HAS_ARCH_FEATURE (FMA4_Usable) ? __ieee754_log_fma4 + : (HAS_ARCH_FEATURE (AVX_Usable) + ? __ieee754_log_avx : __ieee754_log_sse2)); +strong_alias (__ieee754_log, __log_finite) + +#define __ieee754_log __ieee754_log_sse2 + + +#include <sysdeps/ieee754/dbl-64/e_log.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow-fma4.c new file mode 100644 index 0000000000..5b3ea8e103 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow-fma4.c @@ -0,0 +1,6 @@ +#define __ieee754_pow __ieee754_pow_fma4 +#define __exp1 __exp1_fma4 +#define __slowpow __slowpow_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/e_pow.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow.c new file mode 100644 index 0000000000..a5c5d89c3e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/e_pow.c @@ -0,0 +1,17 @@ +#include <init-arch.h> +#include <math.h> +#include <math_private.h> + +extern double __ieee754_pow_sse2 (double, double); +extern double __ieee754_pow_fma4 (double, double); + +libm_ifunc (__ieee754_pow, + HAS_ARCH_FEATURE (FMA4_Usable) + ? __ieee754_pow_fma4 + : __ieee754_pow_sse2); +strong_alias (__ieee754_pow, __pow_finite) + +#define __ieee754_pow __ieee754_pow_sse2 + + +#include <sysdeps/ieee754/dbl-64/e_pow.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/halfulp-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/halfulp-fma4.c new file mode 100644 index 0000000000..a00c17c016 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/halfulp-fma4.c @@ -0,0 +1,4 @@ +#define __halfulp __halfulp_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/halfulp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-avx.c new file mode 100644 index 0000000000..366b0b7134 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-avx.c @@ -0,0 +1,14 @@ +#define __add __add_avx +#define __mul __mul_avx +#define __sqr __sqr_avx +#define __sub __sub_avx +#define __dbl_mp __dbl_mp_avx +#define __dvd __dvd_avx + +#define NO___CPY 1 +#define NO___MP_DBL 1 +#define NO___ACR 1 +#define NO__CONST 1 +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/mpa.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-fma4.c new file mode 100644 index 0000000000..a4a759407e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpa-fma4.c @@ -0,0 +1,14 @@ +#define __add __add_fma4 +#define __mul __mul_fma4 +#define __sqr __sqr_fma4 +#define __sub __sub_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __dvd __dvd_fma4 + +#define NO___CPY 1 +#define NO___MP_DBL 1 +#define NO___ACR 1 +#define NO__CONST 1 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mpa.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan-fma4.c new file mode 100644 index 0000000000..fbd3bd49a2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan-fma4.c @@ -0,0 +1,10 @@ +#define __mpatan __mpatan_fma4 +#define __add __add_fma4 +#define __dvd __dvd_fma4 +#define __mpsqrt __mpsqrt_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define AVOID_MPATAN_H 1 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mpatan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan2-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan2-fma4.c new file mode 100644 index 0000000000..e6e44d49b0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpatan2-fma4.c @@ -0,0 +1,9 @@ +#define __mpatan2 __mpatan2_fma4 +#define __add __add_fma4 +#define __dvd __dvd_fma4 +#define __mpatan __mpatan_fma4 +#define __mpsqrt __mpsqrt_fma4 +#define __mul __mul_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mpatan2.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-avx.c new file mode 100644 index 0000000000..87f29c96c9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-avx.c @@ -0,0 +1,9 @@ +#define __mpexp __mpexp_avx +#define __add __add_avx +#define __dbl_mp __dbl_mp_avx +#define __dvd __dvd_avx +#define __mul __mul_avx +#define AVOID_MPEXP_H 1 +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/mpexp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-fma4.c new file mode 100644 index 0000000000..07ca6e9ad0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpexp-fma4.c @@ -0,0 +1,9 @@ +#define __mpexp __mpexp_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __dvd __dvd_fma4 +#define __mul __mul_fma4 +#define AVOID_MPEXP_H 1 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mpexp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-avx.c new file mode 100644 index 0000000000..fd783d9a67 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-avx.c @@ -0,0 +1,8 @@ +#define __mplog __mplog_avx +#define __add __add_avx +#define __mpexp __mpexp_avx +#define __mul __mul_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/mplog.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-fma4.c new file mode 100644 index 0000000000..b4733118d7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mplog-fma4.c @@ -0,0 +1,8 @@ +#define __mplog __mplog_fma4 +#define __add __add_fma4 +#define __mpexp __mpexp_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mplog.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpsqrt-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpsqrt-fma4.c new file mode 100644 index 0000000000..f8a1ba2d92 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mpsqrt-fma4.c @@ -0,0 +1,8 @@ +#define __mpsqrt __mpsqrt_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define AVOID_MPSQRT_H 1 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mpsqrt.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mptan-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mptan-fma4.c new file mode 100644 index 0000000000..fb4a9d48ca --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/mptan-fma4.c @@ -0,0 +1,7 @@ +#define __mptan __mptan_fma4 +#define __c32 __c32_fma4 +#define __dvd __dvd_fma4 +#define __mpranred __mpranred_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/mptan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-avx.c new file mode 100644 index 0000000000..b5cb9c3a75 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-avx.c @@ -0,0 +1,8 @@ +#define atan __atan_avx +#define __add __add_avx +#define __dbl_mp __dbl_mp_avx +#define __mul __mul_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/s_atan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-fma4.c new file mode 100644 index 0000000000..9e83e6cdab --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan-fma4.c @@ -0,0 +1,9 @@ +#define atan __atan_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mpatan __mpatan_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/s_atan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan.c new file mode 100644 index 0000000000..742e95cb96 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_atan.c @@ -0,0 +1,15 @@ +#include <init-arch.h> +#include <math.h> + +extern double __atan_sse2 (double); +extern double __atan_avx (double); +extern double __atan_fma4 (double); + +libm_ifunc (atan, (HAS_ARCH_FEATURE (FMA4_Usable) ? __atan_fma4 : + HAS_ARCH_FEATURE (AVX_Usable) + ? __atan_avx : __atan_sse2)); + +#define atan __atan_sse2 + + +#include <sysdeps/ieee754/dbl-64/s_atan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil-c.c new file mode 100644 index 0000000000..6a5ea3ff27 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil-c.c @@ -0,0 +1,2 @@ +#define __ceil __ceil_c +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_ceil.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f8eef43eff --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceil.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __ceil_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __ceil_c(%rip), %rax +2: ret +END(__ceil) +weak_alias (__ceil, ceil) + + +ENTRY(__ceil_sse41) + roundsd $10, %xmm0, %xmm0 + ret +END(__ceil_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf-c.c new file mode 100644 index 0000000000..229a6273b2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf-c.c @@ -0,0 +1,2 @@ +#define __ceilf __ceilf_c +#include <sysdeps/ieee754/flt-32/s_ceilf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..076f10f0f0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_ceilf.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __ceilf_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __ceilf_c(%rip), %rax +2: ret +END(__ceilf) +weak_alias (__ceilf, ceilf) + + +ENTRY(__ceilf_sse41) + roundss $10, %xmm0, %xmm0 + ret +END(__ceilf_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor-c.c new file mode 100644 index 0000000000..68733b69ef --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor-c.c @@ -0,0 +1,3 @@ +#undef __floor +#define __floor __floor_c +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_floor.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..f519ab24f4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floor.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__floor) + .type __floor, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __floor_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __floor_c(%rip), %rax +2: ret +END(__floor) +weak_alias (__floor, floor) + + +ENTRY(__floor_sse41) + roundsd $9, %xmm0, %xmm0 + ret +END(__floor_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf-c.c new file mode 100644 index 0000000000..2386362328 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf-c.c @@ -0,0 +1,3 @@ +#undef __floorf +#define __floorf __floorf_c +#include <sysdeps/ieee754/flt-32/s_floorf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..8613f73acc --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_floorf.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __floorf_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __floorf_c(%rip), %rax +2: ret +END(__floorf) +weak_alias (__floorf, floorf) + + +ENTRY(__floorf_sse41) + roundss $9, %xmm0, %xmm0 + ret +END(__floorf_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fma.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fma.c new file mode 100644 index 0000000000..3ac4fed660 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fma.c @@ -0,0 +1,50 @@ +/* FMA version of fma. + Copyright (C) 2009-2017 Free Software Foundation, Inc. + Contributed by Intel Corporation. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <config.h> +#include <math.h> +#include <init-arch.h> + +extern double __fma_sse2 (double x, double y, double z) attribute_hidden; + + +static double +__fma_fma3 (double x, double y, double z) +{ + asm ("vfmadd213sd %3, %2, %0" : "=x" (x) : "0" (x), "x" (y), "xm" (z)); + return x; +} + + +static double +__fma_fma4 (double x, double y, double z) +{ + asm ("vfmaddsd %3, %2, %1, %0" : "=x" (x) : "x" (x), "x" (y), "x" (z)); + return x; +} + + +libm_ifunc (__fma, HAS_ARCH_FEATURE (FMA_Usable) + ? __fma_fma3 : (HAS_ARCH_FEATURE (FMA4_Usable) + ? __fma_fma4 : __fma_sse2)); +weak_alias (__fma, fma) + +#define __fma __fma_sse2 + +#include <sysdeps/ieee754/dbl-64/s_fma.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fmaf.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fmaf.c new file mode 100644 index 0000000000..1ae227c1d4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_fmaf.c @@ -0,0 +1,49 @@ +/* FMA version of fmaf. + Copyright (C) 2009-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <config.h> +#include <math.h> +#include <init-arch.h> + +extern float __fmaf_sse2 (float x, float y, float z) attribute_hidden; + + +static float +__fmaf_fma3 (float x, float y, float z) +{ + asm ("vfmadd213ss %3, %2, %0" : "=x" (x) : "0" (x), "x" (y), "xm" (z)); + return x; +} + + +static float +__fmaf_fma4 (float x, float y, float z) +{ + asm ("vfmaddss %3, %2, %1, %0" : "=x" (x) : "x" (x), "x" (y), "x" (z)); + return x; +} + + +libm_ifunc (__fmaf, HAS_ARCH_FEATURE (FMA_Usable) + ? __fmaf_fma3 : (HAS_ARCH_FEATURE (FMA4_Usable) + ? __fmaf_fma4 : __fmaf_sse2)); +weak_alias (__fmaf, fmaf) + +#define __fmaf __fmaf_sse2 + +#include <sysdeps/ieee754/dbl-64/s_fmaf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint-c.c new file mode 100644 index 0000000000..f897a2a6a6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint-c.c @@ -0,0 +1,3 @@ +#undef __nearbyint +#define __nearbyint __nearbyint_c +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_nearbyint.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint.S new file mode 100644 index 0000000000..5a734f6027 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__nearbyint) + .type __nearbyint, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __nearbyint_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __nearbyint_c(%rip), %rax +2: ret +END(__nearbyint) +weak_alias (__nearbyint, nearbyint) + + +ENTRY(__nearbyint_sse41) + roundsd $0xc, %xmm0, %xmm0 + ret +END(__nearbyint_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf-c.c new file mode 100644 index 0000000000..aa7768233b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf-c.c @@ -0,0 +1,3 @@ +#undef __nearbyintf +#define __nearbyintf __nearbyintf_c +#include <sysdeps/ieee754/flt-32/s_nearbyintf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 0000000000..ad79fd6021 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__nearbyintf) + .type __nearbyintf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __nearbyintf_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __nearbyintf_c(%rip), %rax +2: ret +END(__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) + + +ENTRY(__nearbyintf_sse41) + roundss $0xc, %xmm0, %xmm0 + ret +END(__nearbyintf_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint-c.c new file mode 100644 index 0000000000..162a630ff9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint-c.c @@ -0,0 +1,3 @@ +#undef __rint +#define __rint __rint_c +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_rint.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..4f628a93a4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rint.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__rint) + .type __rint, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __rint_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __rint_c(%rip), %rax +2: ret +END(__rint) +weak_alias (__rint, rint) + + +ENTRY(__rint_sse41) + roundsd $4, %xmm0, %xmm0 + ret +END(__rint_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf-c.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf-c.c new file mode 100644 index 0000000000..8505249f34 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf-c.c @@ -0,0 +1,3 @@ +#undef __rintf +#define __rintf __rintf_c +#include <sysdeps/ieee754/flt-32/s_rintf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..dee4ad794c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_rintf.S @@ -0,0 +1,38 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@gmail.come>, 2011. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> +#include <init-arch.h> + + +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq __rintf_sse41(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jnz 2f + leaq __rintf_c(%rip), %rax +2: ret +END(__rintf) +weak_alias (__rintf, rintf) + + +ENTRY(__rintf_sse41) + roundss $4, %xmm0, %xmm0 + ret +END(__rintf_sse41) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-avx.c new file mode 100644 index 0000000000..e1c6de0259 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-avx.c @@ -0,0 +1,5 @@ +#define __cos __cos_avx +#define __sin __sin_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/s_sin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-fma4.c new file mode 100644 index 0000000000..4c35739dc9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin-fma4.c @@ -0,0 +1,11 @@ +#define __cos __cos_fma4 +#define __sin __sin_fma4 +#define __docos __docos_fma4 +#define __dubsin __dubsin_fma4 +#define __mpcos __mpcos_fma4 +#define __mpcos1 __mpcos1_fma4 +#define __mpsin __mpsin_fma4 +#define __mpsin1 __mpsin1_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/s_sin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin.c new file mode 100644 index 0000000000..8ffd3e7125 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_sin.c @@ -0,0 +1,26 @@ +#include <init-arch.h> +#include <math.h> +#undef NAN + +extern double __cos_sse2 (double); +extern double __sin_sse2 (double); +extern double __cos_avx (double); +extern double __sin_avx (double); +extern double __cos_fma4 (double); +extern double __sin_fma4 (double); + +libm_ifunc (__cos, (HAS_ARCH_FEATURE (FMA4_Usable) ? __cos_fma4 : + HAS_ARCH_FEATURE (AVX_Usable) + ? __cos_avx : __cos_sse2)); +weak_alias (__cos, cos) + +libm_ifunc (__sin, (HAS_ARCH_FEATURE (FMA4_Usable) ? __sin_fma4 : + HAS_ARCH_FEATURE (AVX_Usable) + ? __sin_avx : __sin_sse2)); +weak_alias (__sin, sin) + +#define __cos __cos_sse2 +#define __sin __sin_sse2 + + +#include <sysdeps/ieee754/dbl-64/s_sin.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-avx.c new file mode 100644 index 0000000000..53de5d3c98 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-avx.c @@ -0,0 +1,6 @@ +#define tan __tan_avx +#define __dbl_mp __dbl_mp_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/s_tan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-fma4.c new file mode 100644 index 0000000000..a805440b46 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan-fma4.c @@ -0,0 +1,8 @@ +#define tan __tan_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mpranred __mpranred_fma4 +#define __mptan __mptan_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/s_tan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan.c new file mode 100644 index 0000000000..25f3bca07e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/s_tan.c @@ -0,0 +1,15 @@ +#include <init-arch.h> +#include <math.h> + +extern double __tan_sse2 (double); +extern double __tan_avx (double); +extern double __tan_fma4 (double); + +libm_ifunc (tan, (HAS_ARCH_FEATURE (FMA4_Usable) ? __tan_fma4 : + HAS_ARCH_FEATURE (AVX_Usable) + ? __tan_avx : __tan_sse2)); + +#define tan __tan_sse2 + + +#include <sysdeps/ieee754/dbl-64/s_tan.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/sincos32-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/sincos32-fma4.c new file mode 100644 index 0000000000..ebbfa18cca --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/sincos32-fma4.c @@ -0,0 +1,15 @@ +#define __cos32 __cos32_fma4 +#define __sin32 __sin32_fma4 +#define __c32 __c32_fma4 +#define __mpsin __mpsin_fma4 +#define __mpsin1 __mpsin1_fma4 +#define __mpcos __mpcos_fma4 +#define __mpcos1 __mpcos1_fma4 +#define __mpranred __mpranred_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/sincos32.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-avx.c new file mode 100644 index 0000000000..d01c6d71a4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-avx.c @@ -0,0 +1,9 @@ +#define __slowexp __slowexp_avx +#define __add __add_avx +#define __dbl_mp __dbl_mp_avx +#define __mpexp __mpexp_avx +#define __mul __mul_avx +#define __sub __sub_avx +#define SECTION __attribute__ ((section (".text.avx"))) + +#include <sysdeps/ieee754/dbl-64/slowexp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c new file mode 100644 index 0000000000..3bcde84233 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c @@ -0,0 +1,9 @@ +#define __slowexp __slowexp_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mpexp __mpexp_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/slowexp.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowpow-fma4.c b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowpow-fma4.c new file mode 100644 index 0000000000..69d69823bb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/slowpow-fma4.c @@ -0,0 +1,11 @@ +#define __slowpow __slowpow_fma4 +#define __add __add_fma4 +#define __dbl_mp __dbl_mp_fma4 +#define __mpexp __mpexp_fma4 +#define __mplog __mplog_fma4 +#define __mul __mul_fma4 +#define __sub __sub_fma4 +#define __halfulp __halfulp_fma4 +#define SECTION __attribute__ ((section (".text.fma4"))) + +#include <sysdeps/ieee754/dbl-64/slowpow.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S new file mode 100644 index 0000000000..b209492442 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized cos, vector length is 2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2v_cos) + .type _ZGVbN2v_cos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_cos_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2v_cos_sse2(%rip), %rax + ret +END (_ZGVbN2v_cos) +libmvec_hidden_def (_ZGVbN2v_cos) + +#define _ZGVbN2v_cos _ZGVbN2v_cos_sse2 +#include "../svml_d_cos2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core_sse4.S new file mode 100644 index 0000000000..858dc6532f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core_sse4.S @@ -0,0 +1,223 @@ +/* Function cos vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVbN2v_cos_sse4) +/* ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg + Pi/2 = (N*Pi + R) + + Result calculation: + cos(arg) = sin(arg+Pi/2) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm3 + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + movups __dHalfPI(%rax), %xmm2 + +/* ARGUMENT RANGE REDUCTION: + Add Pi/2 to argument: X' = X+Pi/2 + */ + addpd %xmm3, %xmm2 + movups __dInvPI(%rax), %xmm5 + movups __dAbsMask(%rax), %xmm4 + +/* Get absolute argument value: X' = |X'| */ + andps %xmm2, %xmm4 + +/* Y = X'*InvPi + RS : right shifter add */ + mulpd %xmm5, %xmm2 + +/* Check for large arguments path */ + cmpnlepd __dRangeVal(%rax), %xmm4 + movups __dRShifter(%rax), %xmm6 + addpd %xmm6, %xmm2 + movmskpd %xmm4, %ecx + +/* N = Y - RS : right shifter sub */ + movaps %xmm2, %xmm1 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + psllq $63, %xmm2 + subpd %xmm6, %xmm1 + +/* N = N - 0.5 */ + subpd __dOneHalf(%rax), %xmm1 + movups __dPI1(%rax), %xmm7 + +/* R = X - N*Pi1 */ + mulpd %xmm1, %xmm7 + movups __dPI2(%rax), %xmm4 + +/* R = R - N*Pi2 */ + mulpd %xmm1, %xmm4 + subpd %xmm7, %xmm0 + movups __dPI3(%rax), %xmm5 + +/* R = R - N*Pi3 */ + mulpd %xmm1, %xmm5 + subpd %xmm4, %xmm0 + +/* R = R - N*Pi4 */ + movups __dPI4(%rax), %xmm6 + mulpd %xmm6, %xmm1 + subpd %xmm5, %xmm0 + subpd %xmm1, %xmm0 + +/* POLYNOMIAL APPROXIMATION: R2 = R*R */ + movaps %xmm0, %xmm4 + mulpd %xmm0, %xmm4 + movups __dC7(%rax), %xmm1 + mulpd %xmm4, %xmm1 + addpd __dC6(%rax), %xmm1 + mulpd %xmm4, %xmm1 + addpd __dC5(%rax), %xmm1 + mulpd %xmm4, %xmm1 + addpd __dC4(%rax), %xmm1 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + mulpd %xmm4, %xmm1 + addpd __dC3(%rax), %xmm1 + +/* Poly = R+R*(R2*(C1+R2*(C2+R2*Poly))) */ + mulpd %xmm4, %xmm1 + addpd __dC2(%rax), %xmm1 + mulpd %xmm4, %xmm1 + addpd __dC1(%rax), %xmm1 + mulpd %xmm1, %xmm4 + mulpd %xmm0, %xmm4 + addpd %xmm4, %xmm0 + +/* RECONSTRUCTION: + Final sign setting: Res = Poly^SignRes */ + xorps %xmm2, %xmm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm3, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 200(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 192(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2v_cos_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S new file mode 100644 index 0000000000..ff382e9c6c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized cos, vector length is 4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4v_cos) + .type _ZGVdN4v_cos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_cos_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4v_cos_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4v_cos) +libmvec_hidden_def (_ZGVdN4v_cos) + +#define _ZGVdN4v_cos _ZGVdN4v_cos_sse_wrapper +#include "../svml_d_cos4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core_avx2.S new file mode 100644 index 0000000000..4b6d09743b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core_avx2.S @@ -0,0 +1,207 @@ +/* Function cos vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVdN4v_cos_avx2) + +/* ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg + Pi/2 = (N*Pi + R) + + Result calculation: + cos(arg) = sin(arg+Pi/2) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vmovapd %ymm0, %ymm1 + vmovupd __dInvPI(%rax), %ymm4 + vmovupd __dRShifter(%rax), %ymm5 + +/* + ARGUMENT RANGE REDUCTION: + Add Pi/2 to argument: X' = X+Pi/2 + */ + vaddpd __dHalfPI(%rax), %ymm1, %ymm7 + +/* Get absolute argument value: X' = |X'| */ + vandpd __dAbsMask(%rax), %ymm7, %ymm2 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd %ymm5, %ymm4, %ymm7 + vmovupd __dC7(%rax), %ymm4 + +/* Check for large arguments path */ + vcmpnle_uqpd __dRangeVal(%rax), %ymm2, %ymm3 + +/* N = Y - RS : right shifter sub */ + vsubpd %ymm5, %ymm7, %ymm6 + vmovupd __dPI1_FMA(%rax), %ymm2 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %ymm7, %ymm7 + +/* N = N - 0.5 */ + vsubpd __dOneHalf(%rax), %ymm6, %ymm0 + vmovmskpd %ymm3, %ecx + +/* R = X - N*Pi1 */ + vmovapd %ymm1, %ymm3 + vfnmadd231pd %ymm0, %ymm2, %ymm3 + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %ymm0, %ymm3 + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %ymm3, %ymm0 + +/* POLYNOMIAL APPROXIMATION: R2 = R*R */ + vmulpd %ymm0, %ymm0, %ymm5 + vfmadd213pd __dC6(%rax), %ymm5, %ymm4 + vfmadd213pd __dC5(%rax), %ymm5, %ymm4 + vfmadd213pd __dC4(%rax), %ymm5, %ymm4 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3(%rax), %ymm5, %ymm4 + +/* Poly = R+R*(R2*(C1+R2*(C2+R2*Poly))) */ + vfmadd213pd __dC2(%rax), %ymm5, %ymm4 + vfmadd213pd __dC1(%rax), %ymm5, %ymm4 + vmulpd %ymm5, %ymm4, %ymm6 + vfmadd213pd %ymm0, %ymm0, %ymm6 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignRes */ + vxorpd %ymm7, %ymm6, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm1, 320(%rsp) + vmovupd %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 328(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(cos) + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 320(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(cos) + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4v_cos_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S new file mode 100644 index 0000000000..46d35a25d2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized cos, vector length is 8. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8v_cos) + .type _ZGVeN8v_cos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX +1: leaq _ZGVeN8v_cos_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8v_cos_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8v_cos_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8v_cos) + +#define _ZGVeN8v_cos _ZGVeN8v_cos_avx2_wrapper +#include "../svml_d_cos8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S new file mode 100644 index 0000000000..e7af83c6d5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S @@ -0,0 +1,463 @@ +/* Function cos vectorized with AVX-512, KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_cos_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_cos +#else +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg + Pi/2 = (N*Pi + R) + + Result calculation: + cos(arg) = sin(arg+Pi/2) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + +/* R = X - N*Pi1 */ + vmovaps %zmm0, %zmm7 + +/* Check for large arguments path */ + movq $-1, %rcx + +/* + ARGUMENT RANGE REDUCTION: + Add Pi/2 to argument: X' = X+Pi/2 + */ + vaddpd __dHalfPI(%rax), %zmm0, %zmm5 + vmovups __dInvPI(%rax), %zmm3 + +/* Get absolute argument value: X' = |X'| */ + vpandq __dAbsMask(%rax), %zmm5, %zmm1 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd __dRShifter(%rax), %zmm3, %zmm5 + vmovups __dPI1_FMA(%rax), %zmm6 + +/* N = Y - RS : right shifter sub */ + vsubpd __dRShifter(%rax), %zmm5, %zmm4 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm5, %zmm12 + vmovups __dC7(%rax), %zmm8 + +/* N = N - 0.5 */ + vsubpd __dOneHalf(%rax), %zmm4, %zmm10 + vcmppd $22, __dRangeVal(%rax), %zmm1, %k1 + vpbroadcastq %rcx, %zmm2{%k1}{z} + vfnmadd231pd %zmm10, %zmm6, %zmm7 + vptestmq %zmm2, %zmm2, %k0 + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm10, %zmm7 + kmovw %k0, %ecx + movzbl %cl, %ecx + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %zmm7, %zmm10 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + vmulpd %zmm10, %zmm10, %zmm9 + vfmadd213pd __dC6(%rax), %zmm9, %zmm8 + vfmadd213pd __dC5(%rax), %zmm9, %zmm8 + vfmadd213pd __dC4(%rax), %zmm9, %zmm8 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3(%rax), %zmm9, %zmm8 + +/* Poly = R+R*(R2*(C1+R2*(C2+R2*Poly))) */ + vfmadd213pd __dC2(%rax), %zmm9, %zmm8 + vfmadd213pd __dC1(%rax), %zmm9, %zmm8 + vmulpd %zmm9, %zmm8, %zmm11 + vfmadd213pd %zmm10, %zmm10, %zmm11 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignRes + */ + vpxorq %zmm12, %zmm11, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + call JUMPTARGET(cos) + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + call JUMPTARGET(cos) + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_1_7 +#endif +END (_ZGVeN8v_cos_knl) + +ENTRY (_ZGVeN8v_cos_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_cos +#else +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg + Pi/2 = (N*Pi + R) + + Result calculation: + cos(arg) = sin(arg+Pi/2) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + +/* R = X - N*Pi1 */ + vmovaps %zmm0, %zmm8 + +/* Check for large arguments path */ + vpbroadcastq .L_2il0floatpacket.16(%rip), %zmm2 + +/* + ARGUMENT RANGE REDUCTION: + Add Pi/2 to argument: X' = X+Pi/2 + */ + vaddpd __dHalfPI(%rax), %zmm0, %zmm6 + vmovups __dInvPI(%rax), %zmm3 + vmovups __dRShifter(%rax), %zmm4 + vmovups __dPI1_FMA(%rax), %zmm7 + vmovups __dC7(%rax), %zmm9 + +/* Get absolute argument value: X' = |X'| */ + vandpd __dAbsMask(%rax), %zmm6, %zmm1 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd %zmm4, %zmm3, %zmm6 + vcmppd $18, __dRangeVal(%rax), %zmm1, %k1 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm6, %zmm13 + +/* N = Y - RS : right shifter sub */ + vsubpd %zmm4, %zmm6, %zmm5 + +/* N = N - 0.5 */ + vsubpd __dOneHalf(%rax), %zmm5, %zmm11 + vfnmadd231pd %zmm11, %zmm7, %zmm8 + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm11, %zmm8 + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %zmm8, %zmm11 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + vmulpd %zmm11, %zmm11, %zmm10 + vfmadd213pd __dC6(%rax), %zmm10, %zmm9 + vfmadd213pd __dC5(%rax), %zmm10, %zmm9 + vfmadd213pd __dC4(%rax), %zmm10, %zmm9 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3(%rax), %zmm10, %zmm9 + +/* Poly = R+R*(R2*(C1+R2*(C2+R2*Poly))) */ + vfmadd213pd __dC2(%rax), %zmm10, %zmm9 + vfmadd213pd __dC1(%rax), %zmm10, %zmm9 + vmulpd %zmm10, %zmm9, %zmm12 + vfmadd213pd %zmm11, %zmm11, %zmm12 + vpandnq %zmm1, %zmm1, %zmm2{%k1} + vcmppd $3, %zmm2, %zmm2, %k0 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignRes + */ + vxorpd %zmm13, %zmm12, %zmm1 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_2_7 +#endif +END (_ZGVeN8v_cos_skx) + + .section .rodata, "a" +.L_2il0floatpacket.16: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.16,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S new file mode 100644 index 0000000000..5a17e11a0f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized exp. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2v_exp) + .type _ZGVbN2v_exp, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_exp_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2v_exp_sse2(%rip), %rax + ret +END (_ZGVbN2v_exp) +libmvec_hidden_def (_ZGVbN2v_exp) + +#define _ZGVbN2v_exp _ZGVbN2v_exp_sse2 +#include "../svml_d_exp2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core_sse4.S new file mode 100644 index 0000000000..864dc5ae9f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core_sse4.S @@ -0,0 +1,225 @@ +/* Function exp vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_exp_data.h" + + .text +ENTRY (_ZGVbN2v_exp_sse4) +/* + ALGORITHM DESCRIPTION: + + Argument representation: + N = rint(X*2^k/ln2) = 2^k*M+j + X = N*ln2/2^k + r = M*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + N = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(M*ln2 + ln2*(j/2^k) + r) + = 2^M * 2^(j/2^k) * exp(r) + 2^M is calculated by bit manipulation + 2^(j/2^k) is stored in table + exp(r) is approximated by polynomial. + + The table lookup is skipped if k = 0. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm3 + movq __svml_dexp_data@GOTPCREL(%rip), %r8 + +/* iAbsX = (int)(lX>>32), lX = *(longlong*)&X */ + pshufd $221, %xmm3, %xmm7 + movups __dbInvLn2(%r8), %xmm0 + +/* dK = X*dbInvLn2 */ + mulpd %xmm3, %xmm0 + movq __iAbsMask(%r8), %xmm5 + movq __iDomainRange(%r8), %xmm6 + +/* iAbsX = iAbsX&iAbsMask */ + pand %xmm5, %xmm7 + +/* iRangeMask = (iAbsX>iDomainRange) */ + pcmpgtd %xmm6, %xmm7 + +/* Mask = iRangeMask?1:0, set mask for overflow/underflow */ + movmskps %xmm7, %eax + +/* dN = rint(X*2^k/Ln2) */ + xorps %xmm7, %xmm7 + movups __dbLn2hi(%r8), %xmm5 + movups __dbLn2lo(%r8), %xmm6 + roundpd $0, %xmm0, %xmm7 + +/* dR = X - dN*dbLn2hi, dbLn2hi is 52-8-k hi bits of ln2/2^k */ + mulpd %xmm7, %xmm5 + +/* dR = dR - dN*dbLn2lo, dbLn2lo is 40..94 bits of lo part of ln2/2^k */ + mulpd %xmm6, %xmm7 + movups __dbShifter(%r8), %xmm4 + +/* dM = X*dbInvLn2+dbShifter */ + addpd %xmm0, %xmm4 + movaps %xmm3, %xmm0 + subpd %xmm5, %xmm0 + subpd %xmm7, %xmm0 + movups __dPC2(%r8), %xmm5 + +/* exp(r) = b0+r*(b0+r*(b1+r*b2)) */ + mulpd %xmm0, %xmm5 + addpd __dPC1(%r8), %xmm5 + mulpd %xmm0, %xmm5 + movups __dPC0(%r8), %xmm6 + addpd %xmm6, %xmm5 + mulpd %xmm5, %xmm0 + movdqu __lIndexMask(%r8), %xmm2 + +/* lIndex = (*(longlong*)&dM)&lIndexMask, lIndex is the lower K bits of lM */ + movdqa %xmm2, %xmm1 + +/* lM = (*(longlong*)&dM)&(~lIndexMask) */ + pandn %xmm4, %xmm2 + pand %xmm4, %xmm1 + +/* lM = lM<<(52-K), 2^M */ + psllq $42, %xmm2 + +/* table lookup for dT[j] = 2^(j/2^k) */ + movd %xmm1, %edx + pextrw $4, %xmm1, %ecx + addpd %xmm0, %xmm6 + shll $3, %edx + shll $3, %ecx + movq (%r8,%rdx), %xmm0 + andl $3, %eax + movhpd (%r8,%rcx), %xmm0 + +/* 2^(j/2^k) * exp(r) */ + mulpd %xmm6, %xmm0 + +/* multiply by 2^M through integer add */ + paddq %xmm2, %xmm0 + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm3, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %cl, %cl + xorl %edx, %edx + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %cl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %eax, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %edx, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 200(%rsp,%r15), %xmm0 + + call JUMPTARGET(__exp_finite) + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 192(%rsp,%r15), %xmm0 + + call JUMPTARGET(__exp_finite) + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2v_exp_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S new file mode 100644 index 0000000000..b994a794cd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized exp. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4v_exp) + .type _ZGVdN4v_exp, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_exp_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4v_exp_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4v_exp) +libmvec_hidden_def (_ZGVdN4v_exp) + +#define _ZGVdN4v_exp _ZGVdN4v_exp_sse_wrapper +#include "../svml_d_exp4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core_avx2.S new file mode 100644 index 0000000000..937b3c09a6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core_avx2.S @@ -0,0 +1,212 @@ +/* Function exp vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_exp_data.h" + + .text +ENTRY (_ZGVdN4v_exp_avx2) +/* + ALGORITHM DESCRIPTION: + + Argument representation: + N = rint(X*2^k/ln2) = 2^k*M+j + X = N*ln2/2^k + r = M*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + N = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(M*ln2 + ln2*(j/2^k) + r) + = 2^M * 2^(j/2^k) * exp(r) + 2^M is calculated by bit manipulation + 2^(j/2^k) is stored in table + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_dexp_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm2 + vmovupd __dbInvLn2(%rax), %ymm3 + vmovupd __dbShifter(%rax), %ymm1 + vmovupd __lIndexMask(%rax), %ymm4 + +/* dM = X*dbInvLn2+dbShifter, dbInvLn2 = 2^k/Ln2 */ + vfmadd213pd %ymm1, %ymm2, %ymm3 + +/* iAbsX = (int)(lX>>32), lX = *(longlong*)&X */ + vextracti128 $1, %ymm2, %xmm5 + vshufps $221, %xmm5, %xmm2, %xmm6 + +/* iAbsX = iAbsX&iAbsMask */ + vandps __iAbsMask(%rax), %xmm6, %xmm7 + +/* dN = dM-dbShifter, dN = rint(X*2^k/Ln2) */ + vsubpd %ymm1, %ymm3, %ymm6 + +/* iRangeMask = (iAbsX>iDomainRange) */ + vpcmpgtd __iDomainRange(%rax), %xmm7, %xmm0 + vmovupd __dbLn2hi(%rax), %ymm1 + vmovupd __dPC0(%rax), %ymm7 + +/* Mask = iRangeMask?1:0, set mask for overflow/underflow */ + vmovmskps %xmm0, %ecx + vmovupd __dPC2(%rax), %ymm0 + +/* dR = X - dN*dbLn2hi, dbLn2hi is 52-8-k hi bits of ln2/2^k */ + vmovdqa %ymm2, %ymm5 + vfnmadd231pd %ymm6, %ymm1, %ymm5 + +/* dR = dR - dN*dbLn2lo, dbLn2lo is 40..94 bits of lo part of ln2/2^k */ + vfnmadd132pd __dbLn2lo(%rax), %ymm5, %ymm6 + +/* exp(r) = b0+r*(b0+r*(b1+r*b2)) */ + vfmadd213pd __dPC1(%rax), %ymm6, %ymm0 + vfmadd213pd %ymm7, %ymm6, %ymm0 + vfmadd213pd %ymm7, %ymm6, %ymm0 + +/* lIndex = (*(longlong*)&dM)&lIndexMask, lIndex is the lower K bits of lM */ + vandps %ymm4, %ymm3, %ymm1 + +/* table lookup for dT[j] = 2^(j/2^k) */ + vxorpd %ymm6, %ymm6, %ymm6 + vpcmpeqd %ymm5, %ymm5, %ymm5 + vgatherqpd %ymm5, (%rax,%ymm1,8), %ymm6 + +/* lM = (*(longlong*)&dM)&(~lIndexMask) */ + vpandn %ymm3, %ymm4, %ymm3 + +/* 2^(j/2^k) * exp(r) */ + vmulpd %ymm0, %ymm6, %ymm0 + +/* lM = lM<<(52-K), 2^M */ + vpsllq $42, %ymm3, %ymm4 + +/* multiply by 2^M through integer add */ + vpaddq %ymm4, %ymm0, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm2, 320(%rsp) + vmovupd %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 328(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(__exp_finite) + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 320(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(__exp_finite) + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4v_exp_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S new file mode 100644 index 0000000000..6189080fcc --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized exp. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8v_exp) + .type _ZGVeN8v_exp, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_exp_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8v_exp_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8v_exp_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8v_exp) + +#define _ZGVeN8v_exp _ZGVeN8v_exp_avx2_wrapper +#include "../svml_d_exp8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S new file mode 100644 index 0000000000..97ba72c2a0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S @@ -0,0 +1,456 @@ +/* Function exp vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_exp_data.h" +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_exp_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_exp +#else +/* + ALGORITHM DESCRIPTION: + + Argument representation: + N = rint(X*2^k/ln2) = 2^k*M+j + X = N*ln2/2^k + r = M*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + N = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(M*ln2 + ln2*(j/2^k) + r) + = 2^M * 2^(j/2^k) * exp(r) + 2^M is calculated by bit manipulation + 2^(j/2^k) is stored in table + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dexp_data@GOTPCREL(%rip), %rax + +/* dR = X - dN*dbLn2hi, dbLn2hi is 52-8-k hi bits of ln2/2^k */ + vmovaps %zmm0, %zmm8 + +/* iAbsX = (int)(lX>>32), lX = *(longlong*)&X */ + vpsrlq $32, %zmm0, %zmm1 + +/* iAbsX = iAbsX&iAbsMask */ + movl $255, %edx + vpmovqd %zmm1, %ymm2 + kmovw %edx, %k2 + +/* iRangeMask = (iAbsX>iDomainRange) */ + movl $-1, %ecx + +/* table lookup for dT[j] = 2^(j/2^k) */ + vpxord %zmm11, %zmm11, %zmm11 + vmovups __dbInvLn2(%rax), %zmm5 + vmovups __dbLn2hi(%rax), %zmm7 + kxnorw %k3, %k3, %k3 + +/* dM = X*dbInvLn2+dbShifter, dbInvLn2 = 2^k/Ln2 */ + vfmadd213pd __dbShifter(%rax), %zmm0, %zmm5 + vmovups __dPC2(%rax), %zmm12 + +/* dN = dM-dbShifter, dN = rint(X*2^k/Ln2) */ + vsubpd __dbShifter(%rax), %zmm5, %zmm9 + vmovups __lIndexMask(%rax), %zmm4 + vfnmadd231pd %zmm9, %zmm7, %zmm8 + vpandd __iAbsMask(%rax), %zmm2, %zmm2{%k2} + +/* lIndex = (*(longlong*)&dM)&lIndexMask, lIndex is the lower K bits of lM */ + vpandq %zmm4, %zmm5, %zmm10 + vgatherqpd (%rax,%zmm10,8), %zmm11{%k3} + vpcmpgtd __iDomainRange(%rax), %zmm2, %k1{%k2} + +/* lM = (*(longlong*)&dM)&(~lIndexMask) */ + vpandnq %zmm5, %zmm4, %zmm6 + vpbroadcastd %ecx, %zmm3{%k1}{z} + +/* lM = lM<<(52-K), 2^M */ + vpsllq $42, %zmm6, %zmm14 + +/* dR = dR - dN*dbLn2lo, dbLn2lo is 40..94 bits of lo part of ln2/2^k */ + vfnmadd132pd __dbLn2lo(%rax), %zmm8, %zmm9 + +/* Mask = iRangeMask?1:0, set mask for overflow/underflow */ + vptestmd %zmm3, %zmm3, %k0{%k2} + +/* exp(r) = b0+r*(b0+r*(b1+r*b2)) */ + vfmadd213pd __dPC1(%rax), %zmm9, %zmm12 + kmovw %k0, %ecx + movzbl %cl, %ecx + vfmadd213pd __dPC0(%rax), %zmm9, %zmm12 + vfmadd213pd __dPC0(%rax), %zmm9, %zmm12 + +/* 2^(j/2^k) * exp(r) */ + vmulpd %zmm12, %zmm11, %zmm13 + +/* multiply by 2^M through integer add */ + vpaddq %zmm14, %zmm13, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + call JUMPTARGET(__exp_finite) + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + call JUMPTARGET(__exp_finite) + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_1_7 +#endif +END (_ZGVeN8v_exp_knl) + +ENTRY (_ZGVeN8v_exp_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_exp +#else +/* + ALGORITHM DESCRIPTION: + + Argument representation: + N = rint(X*2^k/ln2) = 2^k*M+j + X = N*ln2/2^k + r = M*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + N = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(M*ln2 + ln2*(j/2^k) + r) + = 2^M * 2^(j/2^k) * exp(r) + 2^M is calculated by bit manipulation + 2^(j/2^k) is stored in table + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dexp_data@GOTPCREL(%rip), %rax + +/* table lookup for dT[j] = 2^(j/2^k) */ + kxnorw %k1, %k1, %k1 + +/* iAbsX = (int)(lX>>32), lX = *(longlong*)&X */ + vpsrlq $32, %zmm0, %zmm1 + vmovups __dbInvLn2(%rax), %zmm7 + vmovups __dbShifter(%rax), %zmm5 + vmovups __lIndexMask(%rax), %zmm6 + vmovups __dbLn2hi(%rax), %zmm9 + vmovups __dPC0(%rax), %zmm12 + +/* dM = X*dbInvLn2+dbShifter, dbInvLn2 = 2^k/Ln2 */ + vfmadd213pd %zmm5, %zmm0, %zmm7 + vpmovqd %zmm1, %ymm2 + +/* dN = dM-dbShifter, dN = rint(X*2^k/Ln2) */ + vsubpd %zmm5, %zmm7, %zmm11 + +/* iAbsX = iAbsX&iAbsMask */ + vpand __iAbsMask(%rax), %ymm2, %ymm3 + +/* dR = X - dN*dbLn2hi, dbLn2hi is 52-8-k hi bits of ln2/2^k */ + vmovaps %zmm0, %zmm10 + vfnmadd231pd %zmm11, %zmm9, %zmm10 + vmovups __dPC2(%rax), %zmm9 + +/* dR = dR - dN*dbLn2lo, dbLn2lo is 40..94 bits of lo part of ln2/2^k */ + vfnmadd132pd __dbLn2lo(%rax), %zmm10, %zmm11 + +/* exp(r) = b0+r*(b0+r*(b1+r*b2)) */ + vfmadd213pd __dPC1(%rax), %zmm11, %zmm9 + vfmadd213pd %zmm12, %zmm11, %zmm9 + vfmadd213pd %zmm12, %zmm11, %zmm9 + +/* iRangeMask = (iAbsX>iDomainRange) */ + vpcmpgtd __iDomainRange(%rax), %ymm3, %ymm4 + +/* Mask = iRangeMask?1:0, set mask for overflow/underflow */ + vmovmskps %ymm4, %ecx + +/* lIndex = (*(longlong*)&dM)&lIndexMask, lIndex is the lower K bits of lM */ + vpandq %zmm6, %zmm7, %zmm13 + vpmovqd %zmm13, %ymm14 + vpxord %zmm15, %zmm15, %zmm15 + vgatherdpd (%rax,%ymm14,8), %zmm15{%k1} + +/* 2^(j/2^k) * exp(r) */ + vmulpd %zmm9, %zmm15, %zmm10 + +/* lM = (*(longlong*)&dM)&(~lIndexMask) */ + vpandnq %zmm7, %zmm6, %zmm8 + +/* lM = lM<<(52-K), 2^M */ + vpsllq $42, %zmm8, %zmm1 + +/* multiply by 2^M through integer add */ + vpaddq %zmm1, %zmm10, %zmm1 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + call JUMPTARGET(__exp_finite) + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + call JUMPTARGET(__exp_finite) + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_2_7 + +#endif +END (_ZGVeN8v_exp_skx) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S new file mode 100644 index 0000000000..5097add6b5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2v_log) + .type _ZGVbN2v_log, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_log_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2v_log_sse2(%rip), %rax + ret +END (_ZGVbN2v_log) +libmvec_hidden_def (_ZGVbN2v_log) + +#define _ZGVbN2v_log _ZGVbN2v_log_sse2 +#include "../svml_d_log2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S new file mode 100644 index 0000000000..7d4b3c8850 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S @@ -0,0 +1,229 @@ +/* Function log vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" + + .text +ENTRY (_ZGVbN2v_log_sse4) +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by rounding + HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm6 + movq __svml_dlog_data@GOTPCREL(%rip), %r8 + movaps %xmm6, %xmm3 + movaps %xmm6, %xmm2 + +/* isolate exponent bits */ + movaps %xmm6, %xmm1 + psrlq $20, %xmm1 + movups _ExpMask(%r8), %xmm5 + +/* preserve mantissa, set input exponent to 2^(-10) */ + andps %xmm6, %xmm5 + orps _Two10(%r8), %xmm5 + +/* reciprocal approximation good to at least 11 bits */ + cvtpd2ps %xmm5, %xmm7 + cmpltpd _MinNorm(%r8), %xmm3 + cmpnlepd _MaxNorm(%r8), %xmm2 + movlhps %xmm7, %xmm7 + +/* combine and get argument value range mask */ + orps %xmm2, %xmm3 + rcpps %xmm7, %xmm0 + movmskpd %xmm3, %eax + movups _HalfMask(%r8), %xmm2 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + andps %xmm5, %xmm2 + cvtps2pd %xmm0, %xmm4 + subpd %xmm2, %xmm5 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + roundpd $0, %xmm4, %xmm4 + mulpd %xmm4, %xmm2 + mulpd %xmm4, %xmm5 + subpd _One(%r8), %xmm2 + addpd %xmm2, %xmm5 + movups _Threshold(%r8), %xmm2 + +/* calculate index for table lookup */ + movaps %xmm4, %xmm3 + cmpltpd %xmm4, %xmm2 + pshufd $221, %xmm1, %xmm7 + psrlq $40, %xmm3 + +/* convert biased exponent to DP format */ + cvtdq2pd %xmm7, %xmm0 + movd %xmm3, %edx + movups _poly_coeff_1(%r8), %xmm4 + +/* polynomial computation */ + mulpd %xmm5, %xmm4 + andps _Bias(%r8), %xmm2 + orps _Bias1(%r8), %xmm2 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + subpd %xmm2, %xmm0 + addpd _poly_coeff_2(%r8), %xmm4 + +/* exponent*log(2.0) */ + mulpd _L2(%r8), %xmm0 + movaps %xmm5, %xmm2 + mulpd %xmm5, %xmm2 + movups _poly_coeff_3(%r8), %xmm7 + mulpd %xmm5, %xmm7 + mulpd %xmm2, %xmm4 + addpd _poly_coeff_4(%r8), %xmm7 + addpd %xmm4, %xmm7 + mulpd %xmm7, %xmm2 + movslq %edx, %rdx + pextrd $2, %xmm3, %ecx + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + addpd %xmm2, %xmm5 + movslq %ecx, %rcx + movsd _LogRcp_lookup(%r8,%rdx), %xmm1 + movhpd _LogRcp_lookup(%r8,%rcx), %xmm1 + addpd %xmm5, %xmm1 + addpd %xmm1, %xmm0 + testl %eax, %eax + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm6, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %cl, %cl + xorl %edx, %edx + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %cl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %eax, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %edx, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 200(%rsp,%r15), %xmm0 + + call JUMPTARGET(__log_finite) + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 192(%rsp,%r15), %xmm0 + + call JUMPTARGET(__log_finite) + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2v_log_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S new file mode 100644 index 0000000000..1e9a2f48a1 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4v_log) + .type _ZGVdN4v_log, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_log_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4v_log_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4v_log) +libmvec_hidden_def (_ZGVdN4v_log) + +#define _ZGVdN4v_log _ZGVdN4v_log_sse_wrapper +#include "../svml_d_log4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S new file mode 100644 index 0000000000..04ea9e0071 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S @@ -0,0 +1,210 @@ +/* Function log vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" + + .text +ENTRY (_ZGVdN4v_log_avx2) +/* ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by rounding + HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm5 + +/* isolate exponent bits */ + vpsrlq $20, %ymm5, %ymm0 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vandpd _ExpMask(%rax), %ymm5, %ymm6 + vorpd _Two10(%rax), %ymm6, %ymm4 + +/* reciprocal approximation good to at least 11 bits */ + vcvtpd2ps %ymm4, %xmm7 + vrcpps %xmm7, %xmm1 + vcmplt_oqpd _MinNorm(%rax), %ymm5, %ymm7 + vcvtps2pd %xmm1, %ymm3 + vcmpnle_uqpd _MaxNorm(%rax), %ymm5, %ymm1 + vextracti128 $1, %ymm0, %xmm2 + vshufps $221, %xmm2, %xmm0, %xmm6 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vroundpd $0, %ymm3, %ymm2 + +/* convert biased exponent to DP format */ + vcvtdq2pd %xmm6, %ymm0 + +/* combine and get argument value range mask */ + vorpd %ymm1, %ymm7, %ymm3 + vmovupd _One(%rax), %ymm1 + vmovmskpd %ymm3, %ecx + +/* calculate index for table lookup */ + vpsrlq $40, %ymm2, %ymm3 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %ymm1, %ymm2, %ymm4 + vcmpgt_oqpd _Threshold(%rax), %ymm2, %ymm2 + vpcmpeqd %ymm6, %ymm6, %ymm6 + vxorpd %ymm1, %ymm1, %ymm1 + vgatherqpd %ymm6, _LogRcp_lookup(%rax,%ymm3), %ymm1 + +/* exponent*log(2.0) */ + vmovupd _poly_coeff_1(%rax), %ymm6 + vmulpd %ymm4, %ymm4, %ymm3 + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rax), %ymm4, %ymm6 + vandpd _Bias(%rax), %ymm2, %ymm7 + vorpd _Bias1(%rax), %ymm7, %ymm2 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %ymm2, %ymm0, %ymm0 + vmovupd _poly_coeff_3(%rax), %ymm2 + vfmadd213pd _poly_coeff_4(%rax), %ymm4, %ymm2 + vfmadd213pd %ymm2, %ymm3, %ymm6 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %ymm4, %ymm3, %ymm6 + vaddpd %ymm1, %ymm6, %ymm4 + vfmadd132pd _L2(%rax), %ymm4, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm5, 320(%rsp) + vmovupd %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 328(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(__log_finite) + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 320(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(__log_finite) + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4v_log_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S new file mode 100644 index 0000000000..43f572d36c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized log. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8v_log) + .type _ZGVeN8v_log, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_log_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8v_log_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8v_log_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8v_log) + +#define _ZGVeN8v_log _ZGVeN8v_log_avx2_wrapper +#include "../svml_d_log8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S new file mode 100644 index 0000000000..d10d5114c6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S @@ -0,0 +1,468 @@ +/* Function log vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_log_data.h" +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_log_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, obtained by + rounding HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rdx + movq $-1, %rax + +/* isolate exponent bits */ + vpsrlq $20, %zmm0, %zmm2 + vpsrlq $32, %zmm2, %zmm3 + vpxord %zmm2, %zmm2, %zmm2 + kxnorw %k3, %k3, %k3 + vmovups _Two10(%rdx), %zmm1 + vmovups _One(%rdx), %zmm9 + vpmovqd %zmm3, %ymm4 + +/* convert biased exponent to DP format */ + vcvtdq2pd %ymm4, %zmm13 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vpternlogq $248, _ExpMask(%rdx), %zmm0, %zmm1 + vcmppd $17, _MinNorm(%rdx), %zmm0, %k1 + +/* reciprocal approximation good to at least 11 bits */ + vrcp28pd %zmm1, %zmm5 + vpbroadcastq %rax, %zmm6{%k1}{z} + vmovups _poly_coeff_3(%rdx), %zmm15 + vcmppd $22, _MaxNorm(%rdx), %zmm0, %k2 + vmovups _Bias1(%rdx), %zmm14 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm5, %zmm11 + vpbroadcastq %rax, %zmm7{%k2}{z} + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %zmm9, %zmm11, %zmm1 + +/* calculate index for table lookup */ + vpsrlq $40, %zmm11, %zmm10 + vgatherqpd _LogRcp_lookup(%rdx,%zmm10), %zmm2{%k3} + vcmppd $30, _Threshold(%rdx), %zmm11, %k1 + +/* combine and get argument value range mask */ + vporq %zmm7, %zmm6, %zmm8 + +/* exponent*log(2.0) */ + vmovups _poly_coeff_1(%rdx), %zmm11 + vmulpd %zmm1, %zmm1, %zmm10 + vptestmq %zmm8, %zmm8, %k0 + vfmadd213pd _poly_coeff_4(%rdx), %zmm1, %zmm15 + kmovw %k0, %ecx + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rdx), %zmm1, %zmm11 + movzbl %cl, %ecx + vpbroadcastq %rax, %zmm12{%k1}{z} + vfmadd213pd %zmm15, %zmm10, %zmm11 + vpternlogq $248, _Bias(%rdx), %zmm12, %zmm14 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %zmm14, %zmm13, %zmm3 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %zmm1, %zmm10, %zmm11 + vaddpd %zmm2, %zmm11, %zmm1 + vfmadd132pd _L2(%rdx), %zmm1, %zmm3 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm3, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm3, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm3 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + call JUMPTARGET(__log_finite) + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + call JUMPTARGET(__log_finite) + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_1_7 +#endif +END (_ZGVeN8v_log_knl) + +ENTRY (_ZGVeN8v_log_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = -log(Rcp) + log(Rcp*x), + where Rcp ~ 1/x (accuracy ~9 bits, + obtained by rounding HW approximation to 1+9 mantissa bits) + + Reduced argument R=Rcp*x-1 is used to approximate log(1+R) as polynomial + + log(Rcp) = exponent_Rcp*log(2) + log(mantissa_Rcp) + -log(mantissa_Rcp) is obtained from a lookup table, + accessed by a 9-bit index + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_dlog_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm3 + kxnorw %k3, %k3, %k3 + vmovups _Two10(%rax), %zmm2 + vmovups _Threshold(%rax), %zmm14 + vmovups _One(%rax), %zmm11 + vcmppd $21, _MinNorm(%rax), %zmm3, %k1 + vcmppd $18, _MaxNorm(%rax), %zmm3, %k2 + +/* isolate exponent bits */ + vpsrlq $20, %zmm3, %zmm4 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vpternlogq $248, _ExpMask(%rax), %zmm3, %zmm2 + vpbroadcastq .L_2il0floatpacket.12(%rip), %zmm1 + vpsrlq $32, %zmm4, %zmm6 + +/* reciprocal approximation good to at least 11 bits */ + vrcp14pd %zmm2, %zmm5 + +/* exponent*log(2.0) */ + vmovups _poly_coeff_1(%rax), %zmm4 + vpmovqd %zmm6, %ymm7 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm5, %zmm0 + +/* calculate index for table lookup */ + vpsrlq $40, %zmm0, %zmm12 + +/* argument reduction started: R = Mantissa*Rcp - 1 */ + vfmsub213pd %zmm11, %zmm0, %zmm2 + vpmovqd %zmm12, %ymm13 + +/* polynomial computation */ + vfmadd213pd _poly_coeff_2(%rax), %zmm2, %zmm4 + vmovaps %zmm1, %zmm8 + vmovaps %zmm1, %zmm9 + vpxord %zmm5, %zmm5, %zmm5 + vgatherdpd _LogRcp_lookup(%rax,%ymm13), %zmm5{%k3} + vmovups _Bias1(%rax), %zmm13 + vpandnq %zmm3, %zmm3, %zmm8{%k1} + vcmppd $21, %zmm0, %zmm14, %k1 + vpandnq %zmm14, %zmm14, %zmm1{%k1} + vmulpd %zmm2, %zmm2, %zmm14 + vpternlogq $248, _Bias(%rax), %zmm1, %zmm13 + vmovups _poly_coeff_3(%rax), %zmm1 + vfmadd213pd _poly_coeff_4(%rax), %zmm2, %zmm1 + vfmadd213pd %zmm1, %zmm14, %zmm4 + +/* + reconstruction: + (exponent*log(2)) + (LogRcp + (R+poly)) + */ + vfmadd213pd %zmm2, %zmm14, %zmm4 + vaddpd %zmm5, %zmm4, %zmm2 + vpandnq %zmm3, %zmm3, %zmm9{%k2} + +/* combine and get argument value range mask */ + vorpd %zmm9, %zmm8, %zmm10 + vcmppd $3, %zmm10, %zmm10, %k0 + kmovw %k0, %ecx + +/* convert biased exponent to DP format */ + vcvtdq2pd %ymm7, %zmm15 + +/* + Table stores -log(0.5*mantissa) for larger mantissas, + adjust exponent accordingly + */ + vsubpd %zmm13, %zmm15, %zmm0 + vfmadd132pd _L2(%rax), %zmm2, %zmm0 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm3, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm0 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(__log_finite) + + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(__log_finite) + + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_2_7 +#endif +END (_ZGVeN8v_log_skx) + + .section .rodata, "a" +.L_2il0floatpacket.12: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.12,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S new file mode 100644 index 0000000000..adb0872e56 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized pow. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2vv_pow) + .type _ZGVbN2vv_pow, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2vv_pow_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2vv_pow_sse2(%rip), %rax + ret +END (_ZGVbN2vv_pow) +libmvec_hidden_def (_ZGVbN2vv_pow) + +#define _ZGVbN2vv_pow _ZGVbN2vv_pow_sse2 +#include "../svml_d_pow2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S new file mode 100644 index 0000000000..ad7c215ff0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S @@ -0,0 +1,432 @@ +/* Function pow vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_pow_data.h" + + .text +ENTRY (_ZGVbN2vv_pow_sse4) +/* + ALGORITHM DESCRIPTION: + + 1) Calculating log2|x| + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where cq = X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + We get 3 parts of log2 result: HH+HL+HLL ~= log2|x|. + + 2) Calculation of y*(HH+HL+HLL). + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(PH+PL+PLL). + Mathematical idea of computing 2^(PH+PL+PLL) is the following. + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). + Hence 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + + We compute 2^(PH+PL+PLL) as follows. + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $256, %rsp + movq __svml_dpow_data@GOTPCREL(%rip), %rdx + movups %xmm14, 80(%rsp) + movups %xmm9, 176(%rsp) + movaps %xmm1, %xmm9 + pshufd $221, %xmm0, %xmm1 + movq _iIndexMask(%rdx), %xmm14 + movq _iIndexAdd(%rdx), %xmm6 + +/* i = (((Hi(x) & 0x000ffe00) + 0x00000200) >> 10); -> i = (b1..b11 + 1) / 2 */ + pand %xmm1, %xmm14 + paddd %xmm6, %xmm14 + psrld $10, %xmm14 + movups %xmm13, 96(%rsp) + +/* Index for reciprocal table */ + movdqa %xmm14, %xmm13 + pslld $3, %xmm13 + +/* Index for log2 table */ + pslld $4, %xmm14 + movd %xmm13, %eax + movups %xmm10, 160(%rsp) + movups _iMantissaMask(%rdx), %xmm10 + movslq %eax, %rax + +/* x1 = x; Hi(x1) = (Hi(x1)&0x000fffff)|0x3ff00000 */ + andps %xmm0, %xmm10 + pextrd $1, %xmm13, %ecx + movslq %ecx, %rcx + movups %xmm0, (%rsp) + movdqa %xmm1, %xmm0 + +/* k = Hi(x); k = k - 0x3fe7fe00; k = k >> 20 */ + movq _i3fe7fe00(%rdx), %xmm6 + psubd %xmm6, %xmm0 + movups _iHighMask(%rdx), %xmm6 + psrad $20, %xmm0 + movups %xmm15, 48(%rsp) + movups %xmm12, 112(%rsp) + orps _dbOne(%rdx), %xmm10 + movsd 11712(%rdx,%rax), %xmm12 + movd %xmm14, %r8d + movq _i2p20_2p19(%rdx), %xmm15 + movhpd 11712(%rdx,%rcx), %xmm12 + paddd %xmm15, %xmm0 + pextrd $1, %xmm14, %r9d + +/* x1Hi=x1; Lo(x1Hi)&=0xf8000000; x1Lo = x1-x1Hi */ + movaps %xmm6, %xmm14 + andps %xmm10, %xmm14 + movaps %xmm10, %xmm15 + subpd %xmm14, %xmm15 + +/* r1 = x1*rcp1 */ + mulpd %xmm12, %xmm10 + +/* E = -r1+__fence(x1Hi*rcp1) */ + mulpd %xmm12, %xmm14 + +/* E=E+x1Lo*rcp1 */ + mulpd %xmm15, %xmm12 + subpd %xmm10, %xmm14 + pshufd $80, %xmm0, %xmm0 + movslq %r8d, %r8 + andps _iffffffff00000000(%rdx), %xmm0 + subpd _db2p20_2p19(%rdx), %xmm0 + addpd %xmm12, %xmm14 + movslq %r9d, %r9 + +/* T_Rh_Eh = T_Rh + E */ + movaps %xmm14, %xmm15 + movups %xmm8, 208(%rsp) + movups 19968(%rdx,%r8), %xmm8 + movups %xmm11, 144(%rsp) + movaps %xmm8, %xmm11 + +/* cq = c+r1 */ + movups _LHN(%rdx), %xmm13 + movhpd 19968(%rdx,%r9), %xmm11 + addpd %xmm10, %xmm13 + +/* T = k + L1hi */ + addpd %xmm0, %xmm11 + +/* T_Rh = T + cq */ + movaps %xmm13, %xmm12 + addpd %xmm11, %xmm12 + addpd %xmm12, %xmm15 + +/* Rl = T-T_Rh; -> -Rh */ + subpd %xmm12, %xmm11 + +/* HLL = T_Rh - T_Rh_Eh; -> -Eh */ + subpd %xmm15, %xmm12 + +/* Rl=Rl+cq; */ + addpd %xmm13, %xmm11 + +/* cq = cq + E */ + addpd %xmm14, %xmm13 + +/* HLL+=E; -> El */ + addpd %xmm14, %xmm12 + +/* HLL+=Rl */ + addpd %xmm12, %xmm11 + unpckhpd 19968(%rdx,%r9), %xmm8 + +/* T_Rh_Eh_HLLhi = T_Rh_Eh + HLL */ + movaps %xmm15, %xmm14 + +/* HLL+=L1lo; */ + addpd %xmm11, %xmm8 + movups _clv_2(%rdx), %xmm11 + +/* HH = T_Rh_Eh_HLLhi; Lo(HH)&=0xf8000000 */ + movaps %xmm6, %xmm12 + +/* HLL = HLL + (((((((a7)*cq+a6)*cq+a5)*cq+a4)*cq+a3)*cq+a2)*cq+a1)*cq */ + mulpd %xmm13, %xmm11 + addpd _clv_3(%rdx), %xmm11 + mulpd %xmm13, %xmm11 + addpd _clv_4(%rdx), %xmm11 + mulpd %xmm13, %xmm11 + addpd _clv_5(%rdx), %xmm11 + mulpd %xmm13, %xmm11 + addpd _clv_6(%rdx), %xmm11 + mulpd %xmm13, %xmm11 + addpd _clv_7(%rdx), %xmm11 + mulpd %xmm11, %xmm13 + addpd %xmm13, %xmm8 + addpd %xmm8, %xmm14 + +/* + 2^(y*(HH+HL+HLL)) starts here: + yH = y; Lo(yH)&=0xf8000000 + */ + andps %xmm9, %xmm6 + +/* yL = y-yH; */ + movaps %xmm9, %xmm11 + subpd %xmm6, %xmm11 + andps %xmm14, %xmm12 + +/* HLLhi = T_Rh_Eh_HLLhi - T_Rh_Eh */ + movaps %xmm14, %xmm10 + +/* HL = T_Rh_Eh_HLLhi-HH; */ + subpd %xmm12, %xmm14 + subpd %xmm15, %xmm10 + movq _HIDELTA(%rdx), %xmm2 + +/* pH = yH*HH; */ + movaps %xmm6, %xmm13 + movq _LORANGE(%rdx), %xmm3 + paddd %xmm2, %xmm1 + pcmpgtd %xmm1, %xmm3 + +/* pL=yL*HL+yH*HL; pL+=yL*HH; */ + movaps %xmm11, %xmm1 + mulpd %xmm14, %xmm1 + mulpd %xmm14, %xmm6 + mulpd %xmm12, %xmm13 + mulpd %xmm11, %xmm12 + addpd %xmm6, %xmm1 + +/* HLL = HLL - HLLhi */ + subpd %xmm10, %xmm8 + addpd %xmm12, %xmm1 + +/* pLL = y*HLL */ + mulpd %xmm9, %xmm8 + movups _db2p45_2p44(%rdx), %xmm11 + +/* pHH = pH + *(double*)&db2p45_2p44 */ + movaps %xmm11, %xmm12 + addpd %xmm13, %xmm12 + +/* t=pL+pLL; t+=pHL */ + addpd %xmm8, %xmm1 + movq _ABSMASK(%rdx), %xmm5 + pshufd $221, %xmm9, %xmm4 + pand %xmm5, %xmm4 + movq _INF(%rdx), %xmm7 + movdqa %xmm4, %xmm2 + pcmpgtd %xmm7, %xmm2 + pcmpeqd %xmm7, %xmm4 + pshufd $136, %xmm12, %xmm7 + por %xmm4, %xmm2 + +/* pHH = pHH - *(double*)&db2p45_2p44 */ + subpd %xmm11, %xmm12 + pshufd $221, %xmm13, %xmm10 + por %xmm2, %xmm3 + +/* pHL = pH - pHH; */ + subpd %xmm12, %xmm13 + pand %xmm5, %xmm10 + movq _DOMAINRANGE(%rdx), %xmm5 + movdqa %xmm10, %xmm4 + addpd %xmm1, %xmm13 + pcmpgtd %xmm5, %xmm4 + pcmpeqd %xmm5, %xmm10 + por %xmm10, %xmm4 + movq _jIndexMask(%rdx), %xmm6 + por %xmm4, %xmm3 + movmskps %xmm3, %eax + +/* j = Lo(pHH)&0x0000007f */ + pand %xmm7, %xmm6 + movq _iOne(%rdx), %xmm3 + +/* _n = Lo(pHH); + _n = _n & 0xffffff80; + _n = _n >> 7; + Hi(_2n) = (0x3ff+_n)<<20; Lo(_2n) = 0; -> 2^n + */ + pslld $13, %xmm7 + paddd %xmm3, %xmm7 + pslld $4, %xmm6 + movups _cev_1(%rdx), %xmm3 + movaps %xmm13, %xmm4 + mulpd %xmm13, %xmm3 + +/* T1 = ((double*)exp2_tbl)[ 2*j ] */ + movd %xmm6, %r10d + pshufd $80, %xmm7, %xmm0 + andps _ifff0000000000000(%rdx), %xmm0 + addpd _cev_2(%rdx), %xmm3 + mulpd %xmm13, %xmm3 + addpd _cev_3(%rdx), %xmm3 + mulpd %xmm13, %xmm3 + movslq %r10d, %r10 + andl $3, %eax + pextrd $1, %xmm6, %r11d + movslq %r11d, %r11 + addpd _cev_4(%rdx), %xmm3 + movsd 36416(%rdx,%r10), %xmm2 + movhpd 36416(%rdx,%r11), %xmm2 + mulpd %xmm2, %xmm0 + mulpd %xmm3, %xmm13 + mulpd %xmm0, %xmm4 + addpd _cev_5(%rdx), %xmm13 + mulpd %xmm4, %xmm13 + addpd %xmm13, %xmm0 + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movups 208(%rsp), %xmm8 + movups 176(%rsp), %xmm9 + movups 160(%rsp), %xmm10 + movups 144(%rsp), %xmm11 + movups 112(%rsp), %xmm12 + movups 96(%rsp), %xmm13 + movups 80(%rsp), %xmm14 + movups 48(%rsp), %xmm15 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups (%rsp), %xmm1 + movups %xmm1, 64(%rsp) + movups %xmm9, 128(%rsp) + movups %xmm0, 192(%rsp) + je .LBL_1_2 + + xorb %cl, %cl + xorl %edx, %edx + movq %rsi, 8(%rsp) + movq %rdi, (%rsp) + movq %r12, 40(%rsp) + cfi_offset_rel_rsp (12, 40) + movb %cl, %r12b + movq %r13, 32(%rsp) + cfi_offset_rel_rsp (13, 32) + movl %eax, %r13d + movq %r14, 24(%rsp) + cfi_offset_rel_rsp (14, 24) + movl %edx, %r14d + movq %r15, 16(%rsp) + cfi_offset_rel_rsp (15, 16) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movq 8(%rsp), %rsi + movq (%rsp), %rdi + movq 40(%rsp), %r12 + cfi_restore (%r12) + movq 32(%rsp), %r13 + cfi_restore (%r13) + movq 24(%rsp), %r14 + cfi_restore (%r14) + movq 16(%rsp), %r15 + cfi_restore (%r15) + movups 192(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 72(%rsp,%r15), %xmm0 + movsd 136(%rsp,%r15), %xmm1 + + call JUMPTARGET(__pow_finite) + + movsd %xmm0, 200(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 64(%rsp,%r15), %xmm0 + movsd 128(%rsp,%r15), %xmm1 + + call JUMPTARGET(__pow_finite) + + movsd %xmm0, 192(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2vv_pow_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S new file mode 100644 index 0000000000..eea8af6638 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized pow. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4vv_pow) + .type _ZGVdN4vv_pow, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4vv_pow_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4vv_pow_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4vv_pow) +libmvec_hidden_def (_ZGVdN4vv_pow) + +#define _ZGVdN4vv_pow _ZGVdN4vv_pow_sse_wrapper +#include "../svml_d_pow4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S new file mode 100644 index 0000000000..3092328909 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S @@ -0,0 +1,387 @@ +/* Function pow vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_pow_data.h" + + .text +ENTRY (_ZGVdN4vv_pow_avx2) +/* + ALGORITHM DESCRIPTION: + + 1) Calculating log2|x| + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where cq = X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + We get 3 parts of log2 result: HH+HL+HLL ~= log2|x|. + + 2) Calculation of y*(HH+HL+HLL). + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(PH+PL+PLL). + Mathematical idea of computing 2^(PH+PL+PLL) is the following. + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). + Hence 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + + We compute 2^(PH+PL+PLL) as follows. + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_dpow_data@GOTPCREL(%rip), %rax + vmovups %ymm11, 160(%rsp) + vmovups %ymm8, 224(%rsp) + vmovups %ymm10, 352(%rsp) + vmovups %ymm9, 384(%rsp) + vmovups %ymm13, 288(%rsp) + vmovapd %ymm1, %ymm11 + vxorpd %ymm1, %ymm1, %ymm1 + vextracti128 $1, %ymm0, %xmm5 + vshufps $221, %xmm5, %xmm0, %xmm5 + +/* i = (((Hi(x) & 0x000ffe00) + 0x00000200) >> 10); -> i = (b1..b11 + 1) / 2 */ + vandps _iIndexMask(%rax), %xmm5, %xmm3 + vpaddd _iIndexAdd(%rax), %xmm3, %xmm6 + vpsrld $10, %xmm6, %xmm8 + +/* Index for reciprocal table */ + vpslld $3, %xmm8, %xmm9 + +/* Index for log2 table */ + vpslld $4, %xmm8, %xmm6 + +/* x1 = x; Hi(x1) = (Hi(x1)&0x000fffff)|0x3ff00000 */ + vandpd _iMantissaMask(%rax), %ymm0, %ymm4 + vorpd _dbOne(%rax), %ymm4, %ymm13 + vpcmpeqd %ymm4, %ymm4, %ymm4 + vpcmpeqd %ymm8, %ymm8, %ymm8 + +/* k = Hi(x); k = k - 0x3fe7fe00; k = k >> 20 */ + vpsubd _i3fe7fe00(%rax), %xmm5, %xmm3 + vpaddd _HIDELTA(%rax), %xmm5, %xmm5 + vextracti128 $1, %ymm11, %xmm7 + vshufps $221, %xmm7, %xmm11, %xmm2 + vpand _ABSMASK(%rax), %xmm2, %xmm10 + vpcmpeqd %ymm2, %ymm2, %ymm2 + vgatherdpd %ymm2, 11712(%rax,%xmm9), %ymm1 + vmovups _LORANGE(%rax), %xmm7 + vxorpd %ymm2, %ymm2, %ymm2 + vgatherdpd %ymm4, 19968(%rax,%xmm6), %ymm2 + vxorpd %ymm4, %ymm4, %ymm4 + vgatherdpd %ymm8, 19976(%rax,%xmm6), %ymm4 + vpsrad $20, %xmm3, %xmm6 + vpaddd _i2p20_2p19(%rax), %xmm6, %xmm9 + vpshufd $80, %xmm9, %xmm8 + vpshufd $250, %xmm9, %xmm3 + +/* x1Hi=x1; Lo(x1Hi)&=0xf8000000; x1Lo = x1-x1Hi */ + vandpd _iHighMask(%rax), %ymm13, %ymm9 + vinserti128 $1, %xmm3, %ymm8, %ymm6 + vandpd _iffffffff00000000(%rax), %ymm6, %ymm8 + +/* r1 = x1*rcp1 */ + vmulpd %ymm1, %ymm13, %ymm6 + vsubpd %ymm9, %ymm13, %ymm3 + vsubpd _db2p20_2p19(%rax), %ymm8, %ymm8 + +/* cq = c+r1 */ + vaddpd _LHN(%rax), %ymm6, %ymm13 + +/* E = -r1+__fence(x1Hi*rcp1) */ + vfmsub213pd %ymm6, %ymm1, %ymm9 + +/* E=E+x1Lo*rcp1 */ + vfmadd213pd %ymm9, %ymm1, %ymm3 + +/* T = k + L1hi */ + vaddpd %ymm2, %ymm8, %ymm1 + +/* T_Rh = T + cq */ + vaddpd %ymm13, %ymm1, %ymm8 + +/* Rl = T-T_Rh; -> -Rh */ + vsubpd %ymm8, %ymm1, %ymm6 + +/* Rl=Rl+cq */ + vaddpd %ymm6, %ymm13, %ymm1 + +/* T_Rh_Eh = T_Rh + E */ + vaddpd %ymm3, %ymm8, %ymm6 + +/* cq = cq + E */ + vaddpd %ymm3, %ymm13, %ymm13 + +/* HLL = T_Rh - T_Rh_Eh; -> -Eh */ + vsubpd %ymm6, %ymm8, %ymm9 + +/* HLL+=E; -> El */ + vaddpd %ymm9, %ymm3, %ymm2 + +/* HLL+=Rl */ + vaddpd %ymm1, %ymm2, %ymm8 + +/* HLL+=L1lo */ + vaddpd %ymm4, %ymm8, %ymm4 + vmovupd _clv_2(%rax), %ymm8 + +/* HLL = HLL + (((((((a7)*cq+a6)*cq+a5)*cq+a4)*cq+a3)*cq+a2)*cq+a1)*cq */ + vfmadd213pd _clv_3(%rax), %ymm13, %ymm8 + vfmadd213pd _clv_4(%rax), %ymm13, %ymm8 + vfmadd213pd _clv_5(%rax), %ymm13, %ymm8 + vfmadd213pd _clv_6(%rax), %ymm13, %ymm8 + vfmadd213pd _clv_7(%rax), %ymm13, %ymm8 + vfmadd213pd %ymm4, %ymm13, %ymm8 + +/* T_Rh_Eh_HLLhi = T_Rh_Eh + HLL */ + vaddpd %ymm8, %ymm6, %ymm9 + +/* HH = T_Rh_Eh_HLLhi; Lo(HH)&=0xf8000000 */ + vandpd _iHighMask(%rax), %ymm9, %ymm2 + +/* + 2^(y*(HH+HL+HLL)) starts here: + yH = y; Lo(yH)&=0xf8000000; + */ + vandpd _iHighMask(%rax), %ymm11, %ymm1 + +/* HLLhi = T_Rh_Eh_HLLhi - T_Rh_Eh */ + vsubpd %ymm6, %ymm9, %ymm13 + +/* HL = T_Rh_Eh_HLLhi-HH */ + vsubpd %ymm2, %ymm9, %ymm4 + +/* pH = yH*HH */ + vmulpd %ymm2, %ymm1, %ymm9 + +/* HLL = HLL - HLLhi */ + vsubpd %ymm13, %ymm8, %ymm6 + +/* yL = y-yH */ + vsubpd %ymm1, %ymm11, %ymm8 + vextracti128 $1, %ymm9, %xmm3 + vshufps $221, %xmm3, %xmm9, %xmm13 + vpand _ABSMASK(%rax), %xmm13, %xmm3 + vpcmpgtd %xmm5, %xmm7, %xmm13 + vpcmpgtd _INF(%rax), %xmm10, %xmm7 + vpcmpeqd _INF(%rax), %xmm10, %xmm10 + vpor %xmm10, %xmm7, %xmm7 + vpor %xmm7, %xmm13, %xmm5 + +/* pL=yL*HL+yH*HL; pL+=yL*HH */ + vmulpd %ymm4, %ymm8, %ymm7 + vpcmpgtd _DOMAINRANGE(%rax), %xmm3, %xmm13 + vpcmpeqd _DOMAINRANGE(%rax), %xmm3, %xmm10 + vpor %xmm10, %xmm13, %xmm3 + vpor %xmm3, %xmm5, %xmm13 + vfmadd213pd %ymm7, %ymm4, %ymm1 + +/* pLL = y*HLL; + pHH = pH + *(double*)&db2p45_2p44 + */ + vaddpd _db2p45_2p44(%rax), %ymm9, %ymm7 + vmovmskps %xmm13, %ecx + vfmadd213pd %ymm1, %ymm2, %ymm8 + +/* t=pL+pLL; t+=pHL */ + vfmadd231pd %ymm11, %ymm6, %ymm8 + vextracti128 $1, %ymm7, %xmm1 + vshufps $136, %xmm1, %xmm7, %xmm10 + +/* _n = Lo(pHH); + _n = _n & 0xffffff80; + _n = _n >> 7; + Hi(_2n) = (0x3ff+_n)<<20; Lo(_2n) = 0; -> 2^n + */ + vpslld $13, %xmm10, %xmm2 + vpaddd _iOne(%rax), %xmm2, %xmm13 + vpshufd $80, %xmm13, %xmm4 + vpshufd $250, %xmm13, %xmm1 + +/* j = Lo(pHH)&0x0000007f */ + vandps _jIndexMask(%rax), %xmm10, %xmm3 + +/* T1 = ((double*)exp2_tbl)[ 2*j ] */ + vpcmpeqd %ymm10, %ymm10, %ymm10 + vpslld $4, %xmm3, %xmm5 + +/* pHH = pHH - *(double*)&db2p45_2p44 */ + vsubpd _db2p45_2p44(%rax), %ymm7, %ymm7 + +/* pHL = pH - pHH */ + vsubpd %ymm7, %ymm9, %ymm9 + vaddpd %ymm9, %ymm8, %ymm6 + vinserti128 $1, %xmm1, %ymm4, %ymm2 + vxorpd %ymm1, %ymm1, %ymm1 + vgatherdpd %ymm10, 36416(%rax,%xmm5), %ymm1 + vandpd _ifff0000000000000(%rax), %ymm2, %ymm13 + vmovupd _cev_1(%rax), %ymm2 + vmulpd %ymm1, %ymm13, %ymm1 + vfmadd213pd _cev_2(%rax), %ymm6, %ymm2 + vmulpd %ymm6, %ymm1, %ymm8 + vfmadd213pd _cev_3(%rax), %ymm6, %ymm2 + vfmadd213pd _cev_4(%rax), %ymm6, %ymm2 + vfmadd213pd _cev_5(%rax), %ymm6, %ymm2 + vfmadd213pd %ymm1, %ymm8, %ymm2 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups 224(%rsp), %ymm8 + vmovups 384(%rsp), %ymm9 + vmovups 352(%rsp), %ymm10 + vmovups 160(%rsp), %ymm11 + vmovups 288(%rsp), %ymm13 + vmovdqa %ymm2, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm0, 192(%rsp) + vmovupd %ymm11, 256(%rsp) + vmovupd %ymm2, 320(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm12, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 104(%rsp) + movq %rdi, 96(%rsp) + movq %r12, 136(%rsp) + cfi_offset_rel_rsp (12, 136) + movb %dl, %r12b + movq %r13, 128(%rsp) + cfi_offset_rel_rsp (13, 128) + movl %ecx, %r13d + movq %r14, 120(%rsp) + cfi_offset_rel_rsp (14, 120) + movl %eax, %r14d + movq %r15, 112(%rsp) + cfi_offset_rel_rsp (15, 112) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 64(%rsp), %ymm12 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 320(%rsp), %ymm2 + movq 104(%rsp), %rsi + movq 96(%rsp), %rdi + movq 136(%rsp), %r12 + cfi_restore (%r12) + movq 128(%rsp), %r13 + cfi_restore (%r13) + movq 120(%rsp), %r14 + cfi_restore (%r14) + movq 112(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 200(%rsp,%r15), %xmm0 + vmovsd 264(%rsp,%r15), %xmm1 + vzeroupper + + call JUMPTARGET(__pow_finite) + + vmovsd %xmm0, 328(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 192(%rsp,%r15), %xmm0 + vmovsd 256(%rsp,%r15), %xmm1 + vzeroupper + + call JUMPTARGET(__pow_finite) + + vmovsd %xmm0, 320(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4vv_pow_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S new file mode 100644 index 0000000000..68f12b2848 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized pow. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8vv_pow) + .type _ZGVeN8vv_pow, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8vv_pow_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8vv_pow_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8vv_pow_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8vv_pow) + +#define _ZGVeN8vv_pow _ZGVeN8vv_pow_avx2_wrapper +#include "../svml_d_pow8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S new file mode 100644 index 0000000000..2190c1f6b4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S @@ -0,0 +1,741 @@ +/* Function pow vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_pow_data.h" +#include "svml_d_wrapper_impl.h" + +/* ALGORITHM DESCRIPTION: + + 1) Calculating log2|x| + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where cq = X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + We get 3 parts of log2 result: HH+HL+HLL ~= log2|x|. + + 2) Calculation of y*(HH+HL+HLL). + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(PH+PL+PLL). + Mathematical idea of computing 2^(PH+PL+PLL) is the following. + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). + Hence 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + + We compute 2^(PH+PL+PLL) as follows. + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + .text +ENTRY (_ZGVeN8vv_pow_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_ff _ZGVdN4vv_pow +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + vpsrlq $32, %zmm0, %zmm13 + vmovaps %zmm1, %zmm12 + movq __svml_dpow_data@GOTPCREL(%rip), %rax + movl $255, %edx + vpmovqd %zmm13, %ymm10 + vpsrlq $32, %zmm12, %zmm14 + kmovw %edx, %k1 + movl $-1, %ecx + vpmovqd %zmm14, %ymm15 + +/* x1 = x; Hi(x1) = (Hi(x1)&0x000fffff)|0x3ff00000 */ + vmovups _dbOne(%rax), %zmm6 + +/* i = (((Hi(x) & 0x000ffe00) + 0x00000200) >> 10); -> i = (b1..b11 + 1) / 2 */ + vmovaps %zmm10, %zmm5 + +/* k = Hi(x); k = k - 0x3fe7fe00; k = k >> 20 */ + vpsubd _i3fe7fe00(%rax), %zmm10, %zmm14{%k1} + vpandd _iIndexMask(%rax), %zmm10, %zmm5{%k1} + vpsrad $20, %zmm14, %zmm14{%k1} + vpxord %zmm9, %zmm9, %zmm9 + vpaddd _HIDELTA(%rax), %zmm10, %zmm3{%k1} + vpaddd _iIndexAdd(%rax), %zmm5, %zmm5{%k1} + vpxord %zmm7, %zmm7, %zmm7 + vpaddd _i2p20_2p19(%rax), %zmm14, %zmm14{%k1} + vpcmpd $1, _LORANGE(%rax), %zmm3, %k2{%k1} + vpsrld $10, %zmm5, %zmm5{%k1} + vpandd _ABSMASK(%rax), %zmm15, %zmm2{%k1} + vpbroadcastd %ecx, %zmm1{%k2}{z} + +/* Index for reciprocal table */ + vpslld $3, %zmm5, %zmm8{%k1} + kxnorw %k2, %k2, %k2 + vgatherdpd 11712(%rax,%ymm8), %zmm9{%k2} + vpmovzxdq %ymm14, %zmm10 + +/* Index for log2 table */ + vpslld $4, %zmm5, %zmm13{%k1} + kxnorw %k2, %k2, %k2 + vpsllq $32, %zmm10, %zmm3 + vpxord %zmm8, %zmm8, %zmm8 + vpcmpd $5, _INF(%rax), %zmm2, %k3{%k1} + vpbroadcastd %ecx, %zmm4{%k3}{z} + vpternlogq $248, _iMantissaMask(%rax), %zmm0, %zmm6 + kxnorw %k3, %k3, %k3 + vpternlogq $168, _iffffffff00000000(%rax), %zmm10, %zmm3 + +/* x1Hi=x1; Lo(x1Hi)&=0xf8000000; x1Lo = x1-x1Hi */ + vpandq _iHighMask(%rax), %zmm6, %zmm2 + vgatherdpd 19976(%rax,%ymm13), %zmm8{%k2} + vpord %zmm4, %zmm1, %zmm11{%k1} + vsubpd _db2p20_2p19(%rax), %zmm3, %zmm1 + vsubpd %zmm2, %zmm6, %zmm5 + +/* r1 = x1*rcp1 */ + vmulpd %zmm9, %zmm6, %zmm6 + vgatherdpd 19968(%rax,%ymm13), %zmm7{%k3} + +/* cq = c+r1 */ + vaddpd _LHN(%rax), %zmm6, %zmm4 + +/* E = -r1+__fence(x1Hi*rcp1) */ + vfmsub213pd %zmm6, %zmm9, %zmm2 + +/* T = k + L1hi */ + vaddpd %zmm7, %zmm1, %zmm7 + +/* E=E+x1Lo*rcp1 */ + vfmadd213pd %zmm2, %zmm9, %zmm5 + +/* T_Rh = T + cq */ + vaddpd %zmm4, %zmm7, %zmm3 + +/* Rl = T-T_Rh; -> -Rh */ + vsubpd %zmm3, %zmm7, %zmm9 + +/* Rl=Rl+cq */ + vaddpd %zmm9, %zmm4, %zmm6 + +/* T_Rh_Eh = T_Rh + E */ + vaddpd %zmm5, %zmm3, %zmm9 + +/* HLL = T_Rh - T_Rh_Eh; -> -Eh */ + vsubpd %zmm9, %zmm3, %zmm2 + +/* cq = cq + E; */ + vaddpd %zmm5, %zmm4, %zmm4 + +/* HLL+=E; -> El */ + vaddpd %zmm2, %zmm5, %zmm1 + vmovups _clv_2(%rax), %zmm5 + +/* HLL = HLL + (((((((a7)*cq+a6)*cq+a5)*cq+a4)*cq+a3)*cq+a2)*cq+a1)*cq */ + vfmadd213pd _clv_3(%rax), %zmm4, %zmm5 + +/* HLL+=Rl */ + vaddpd %zmm6, %zmm1, %zmm7 + +/* 2^(y*(HH+HL+HLL)) starts here: + yH = y; Lo(yH)&=0xf8000000 + */ + vpandq _iHighMask(%rax), %zmm12, %zmm6 + +/* yL = y-yH */ + vsubpd %zmm6, %zmm12, %zmm2 + vfmadd213pd _clv_4(%rax), %zmm4, %zmm5 + +/* HLL+=L1lo */ + vaddpd %zmm8, %zmm7, %zmm8 + vfmadd213pd _clv_5(%rax), %zmm4, %zmm5 + vfmadd213pd _clv_6(%rax), %zmm4, %zmm5 + vfmadd213pd _clv_7(%rax), %zmm4, %zmm5 + vfmadd213pd %zmm8, %zmm4, %zmm5 + +/* T_Rh_Eh_HLLhi = T_Rh_Eh + HLL */ + vaddpd %zmm5, %zmm9, %zmm13 + +/* HLLhi = T_Rh_Eh_HLLhi - T_Rh_Eh */ + vsubpd %zmm9, %zmm13, %zmm10 + +/* HLL = HLL - HLLhi */ + vsubpd %zmm10, %zmm5, %zmm3 + +/* HH = T_Rh_Eh_HLLhi; Lo(HH)&=0xf8000000 */ + vpandq _iHighMask(%rax), %zmm13, %zmm5 + +/* pH = yH*HH */ + vmulpd %zmm5, %zmm6, %zmm1 + +/* HL = T_Rh_Eh_HLLhi-HH */ + vsubpd %zmm5, %zmm13, %zmm4 + vpsrlq $32, %zmm1, %zmm14 + +/* pLL = y*HLL; + pHH = pH + *(double*)&db2p45_2p44 + */ + vaddpd _db2p45_2p44(%rax), %zmm1, %zmm10 + vpmovqd %zmm14, %ymm15 + vpandd _ABSMASK(%rax), %zmm15, %zmm14{%k1} + vpcmpd $5, _DOMAINRANGE(%rax), %zmm14, %k3{%k1} + +/* T1 = ((double*)exp2_tbl)[ 2*j ] */ + vpxord %zmm14, %zmm14, %zmm14 + vpbroadcastd %ecx, %zmm13{%k3}{z} + vpord %zmm13, %zmm11, %zmm11{%k1} + vptestmd %zmm11, %zmm11, %k0{%k1} + +/* pL=yL*HL+yH*HL; pL+=yL*HH */ + vmulpd %zmm4, %zmm2, %zmm11 + kmovw %k0, %ecx + vfmadd213pd %zmm11, %zmm4, %zmm6 + +/* pHH = pHH - *(double*)&db2p45_2p44 */ + vsubpd _db2p45_2p44(%rax), %zmm10, %zmm11 + vpmovqd %zmm10, %ymm4 + movzbl %cl, %ecx + +/* _n = Lo(pHH); + _n = _n & 0xffffff80; + _n = _n >> 7; + Hi(_2n) = (0x3ff+_n)<<20; Lo(_2n) = 0; -> 2^n + */ + vpslld $13, %zmm4, %zmm7{%k1} + +/* j = Lo(pHH)&0x0000007f */ + vpandd _jIndexMask(%rax), %zmm4, %zmm9{%k1} + vfmadd213pd %zmm6, %zmm5, %zmm2 + +/* pHL = pH - pHH */ + vsubpd %zmm11, %zmm1, %zmm1 + vpaddd _iOne(%rax), %zmm7, %zmm7{%k1} + +/* t=pL+pLL; t+=pHL */ + vfmadd231pd %zmm12, %zmm3, %zmm2 + vpslld $4, %zmm9, %zmm9{%k1} + kxnorw %k1, %k1, %k1 + vgatherdpd 36416(%rax,%ymm9), %zmm14{%k1} + vpmovzxdq %ymm7, %zmm8 + vaddpd %zmm1, %zmm2, %zmm2 + vmovups _cev_1(%rax), %zmm1 + vpsllq $32, %zmm8, %zmm13 + vpternlogq $168, _ifff0000000000000(%rax), %zmm8, %zmm13 + vfmadd213pd _cev_2(%rax), %zmm2, %zmm1 + vmulpd %zmm14, %zmm13, %zmm15 + vfmadd213pd _cev_3(%rax), %zmm2, %zmm1 + vmulpd %zmm2, %zmm15, %zmm3 + vfmadd213pd _cev_4(%rax), %zmm2, %zmm1 + vfmadd213pd _cev_5(%rax), %zmm2, %zmm1 + vfmadd213pd %zmm15, %zmm3, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm12, 1216(%rsp) + vmovups %zmm1, 1280(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1280(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vmovsd 1224(%rsp,%r15), %xmm1 + call JUMPTARGET(__pow_finite) + vmovsd %xmm0, 1288(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vmovsd 1216(%rsp,%r15), %xmm1 + call JUMPTARGET(__pow_finite) + vmovsd %xmm0, 1280(%rsp,%r15) + jmp .LBL_1_7 + +#endif +END (_ZGVeN8vv_pow_knl) + +ENTRY (_ZGVeN8vv_pow_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_ff _ZGVdN4vv_pow +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + vpsrlq $32, %zmm0, %zmm10 + kxnorw %k1, %k1, %k1 + kxnorw %k2, %k2, %k2 + kxnorw %k3, %k3, %k3 + vpmovqd %zmm10, %ymm7 + movq __svml_dpow_data@GOTPCREL(%rip), %rax + vmovaps %zmm1, %zmm6 + vpsrlq $32, %zmm6, %zmm13 + +/* i = (((Hi(x) & 0x000ffe00) + 0x00000200) >> 10); -> i = (b1..b11 + 1) / 2 */ + vpand _iIndexMask(%rax), %ymm7, %ymm15 + vpaddd _HIDELTA(%rax), %ymm7, %ymm2 + +/* k = Hi(x); k = k - 0x3fe7fe00; k = k >> 20 */ + vpsubd _i3fe7fe00(%rax), %ymm7, %ymm7 + vmovdqu _ABSMASK(%rax), %ymm4 + vmovdqu _LORANGE(%rax), %ymm3 + +/* x1 = x; Hi(x1) = (Hi(x1)&0x000fffff)|0x3ff00000 */ + vmovups _dbOne(%rax), %zmm11 + vmovdqu _INF(%rax), %ymm5 + vpaddd _iIndexAdd(%rax), %ymm15, %ymm12 + vpmovqd %zmm13, %ymm14 + vpternlogq $248, _iMantissaMask(%rax), %zmm0, %zmm11 + vpsrld $10, %ymm12, %ymm10 + vpsrad $20, %ymm7, %ymm13 + +/* Index for reciprocal table */ + vpslld $3, %ymm10, %ymm8 + +/* Index for log2 table */ + vpslld $4, %ymm10, %ymm1 + vpcmpgtd %ymm2, %ymm3, %ymm3 + vpand %ymm4, %ymm14, %ymm2 + vpaddd _i2p20_2p19(%rax), %ymm13, %ymm14 + vpmovzxdq %ymm14, %zmm15 + vpsllq $32, %zmm15, %zmm7 + vpternlogq $168, _iffffffff00000000(%rax), %zmm15, %zmm7 + vsubpd _db2p20_2p19(%rax), %zmm7, %zmm13 + vpxord %zmm9, %zmm9, %zmm9 + vgatherdpd 11712(%rax,%ymm8), %zmm9{%k1} + +/* T1 = ((double*)exp2_tbl)[ 2*j ] */ + kxnorw %k1, %k1, %k1 + vpxord %zmm12, %zmm12, %zmm12 + vpxord %zmm8, %zmm8, %zmm8 + vgatherdpd 19968(%rax,%ymm1), %zmm12{%k2} + vgatherdpd 19976(%rax,%ymm1), %zmm8{%k3} + vmovups _iHighMask(%rax), %zmm1 + +/* x1Hi=x1; Lo(x1Hi)&=0xf8000000; x1Lo = x1-x1Hi */ + vandpd %zmm1, %zmm11, %zmm10 + vsubpd %zmm10, %zmm11, %zmm15 + +/* r1 = x1*rcp1 */ + vmulpd %zmm9, %zmm11, %zmm11 + +/* E = -r1+__fence(x1Hi*rcp1) */ + vfmsub213pd %zmm11, %zmm9, %zmm10 + +/* cq = c+r1 */ + vaddpd _LHN(%rax), %zmm11, %zmm14 + +/* E=E+x1Lo*rcp1 */ + vfmadd213pd %zmm10, %zmm9, %zmm15 + +/* T = k + L1hi */ + vaddpd %zmm12, %zmm13, %zmm9 + +/* T_Rh = T + cq */ + vaddpd %zmm14, %zmm9, %zmm11 + +/* T_Rh_Eh = T_Rh + E */ + vaddpd %zmm15, %zmm11, %zmm13 + +/* Rl = T-T_Rh; -> -Rh */ + vsubpd %zmm11, %zmm9, %zmm12 + +/* HLL = T_Rh - T_Rh_Eh; -> -Eh */ + vsubpd %zmm13, %zmm11, %zmm9 + +/* Rl=Rl+cq */ + vaddpd %zmm12, %zmm14, %zmm10 + +/* HLL+=E; -> El */ + vaddpd %zmm9, %zmm15, %zmm7 + +/* HLL+=Rl */ + vaddpd %zmm10, %zmm7, %zmm12 + +/* 2^(y*(HH+HL+HLL)) starts here: + yH = y; Lo(yH)&=0xf8000000 + */ + vandpd %zmm1, %zmm6, %zmm7 + +/* HLL+=L1lo */ + vaddpd %zmm8, %zmm12, %zmm12 + +/* cq = cq + E */ + vaddpd %zmm15, %zmm14, %zmm8 + vmovups _clv_2(%rax), %zmm14 + +/* HLL = HLL + (((((((a7)*cq+a6)*cq+a5)*cq+a4)*cq+a3)*cq+a2)*cq+a1)*cq */ + vfmadd213pd _clv_3(%rax), %zmm8, %zmm14 + vfmadd213pd _clv_4(%rax), %zmm8, %zmm14 + vfmadd213pd _clv_5(%rax), %zmm8, %zmm14 + vfmadd213pd _clv_6(%rax), %zmm8, %zmm14 + vfmadd213pd _clv_7(%rax), %zmm8, %zmm14 + vfmadd213pd %zmm12, %zmm8, %zmm14 + +/* yL = y-yH */ + vsubpd %zmm7, %zmm6, %zmm8 + +/* T_Rh_Eh_HLLhi = T_Rh_Eh + HLL */ + vaddpd %zmm14, %zmm13, %zmm15 + +/* HH = T_Rh_Eh_HLLhi; Lo(HH)&=0xf8000000 */ + vandpd %zmm1, %zmm15, %zmm11 + +/* HLLhi = T_Rh_Eh_HLLhi - T_Rh_Eh */ + vsubpd %zmm13, %zmm15, %zmm13 + +/* pH = yH*HH */ + vmulpd %zmm11, %zmm7, %zmm9 + +/* HLL = HLL - HLLhi */ + vsubpd %zmm13, %zmm14, %zmm12 + +/* HL = T_Rh_Eh_HLLhi-HH */ + vsubpd %zmm11, %zmm15, %zmm10 + vpsrlq $32, %zmm9, %zmm1 + vmovdqu _DOMAINRANGE(%rax), %ymm13 + vpmovqd %zmm1, %ymm1 + vpand %ymm4, %ymm1, %ymm1 + vpcmpgtd %ymm5, %ymm2, %ymm4 + vpcmpeqd %ymm5, %ymm2, %ymm5 + vpternlogd $254, %ymm5, %ymm4, %ymm3 + vpcmpgtd %ymm13, %ymm1, %ymm2 + vpcmpeqd %ymm13, %ymm1, %ymm4 + vpternlogd $254, %ymm4, %ymm2, %ymm3 + +/* pLL = y*HLL */ + vmovups _db2p45_2p44(%rax), %zmm2 + +/* pHH = pH + *(double*)&db2p45_2p44 */ + vaddpd %zmm2, %zmm9, %zmm1 + vpmovqd %zmm1, %ymm5 + +/* j = Lo(pHH)&0x0000007f */ + vpand _jIndexMask(%rax), %ymm5, %ymm14 + vpslld $4, %ymm14, %ymm15 + vmovmskps %ymm3, %ecx + +/* pL=yL*HL+yH*HL; pL+=yL*HH */ + vmulpd %zmm10, %zmm8, %zmm3 + vfmadd213pd %zmm3, %zmm10, %zmm7 + vfmadd213pd %zmm7, %zmm11, %zmm8 + +/* _n = Lo(pHH) + _n = _n & 0xffffff80 + _n = _n >> 7 + Hi(_2n) = (0x3ff+_n)<<20; Lo(_2n) = 0; -> 2^n + */ + vpslld $13, %ymm5, %ymm7 + +/* t=pL+pLL; t+=pHL */ + vfmadd231pd %zmm6, %zmm12, %zmm8 + vpaddd _iOne(%rax), %ymm7, %ymm10 + vpmovzxdq %ymm10, %zmm11 + vpsllq $32, %zmm11, %zmm3 + vpternlogq $168, _ifff0000000000000(%rax), %zmm11, %zmm3 + +/* pHH = pHH - *(double*)&db2p45_2p44 */ + vsubpd %zmm2, %zmm1, %zmm11 + vmovups _cev_1(%rax), %zmm2 + +/* pHL = pH - pHH */ + vsubpd %zmm11, %zmm9, %zmm9 + vaddpd %zmm9, %zmm8, %zmm8 + vfmadd213pd _cev_2(%rax), %zmm8, %zmm2 + vfmadd213pd _cev_3(%rax), %zmm8, %zmm2 + vfmadd213pd _cev_4(%rax), %zmm8, %zmm2 + vfmadd213pd _cev_5(%rax), %zmm8, %zmm2 + vpxord %zmm4, %zmm4, %zmm4 + vgatherdpd 36416(%rax,%ymm15), %zmm4{%k1} + vmulpd %zmm4, %zmm3, %zmm1 + vmulpd %zmm8, %zmm1, %zmm12 + vfmadd213pd %zmm1, %zmm12, %zmm2 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm2, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm6, 1216(%rsp) + vmovups %zmm2, 1280(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1280(%rsp), %zmm2 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1224(%rsp,%r15), %xmm1 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(__pow_finite) + + vmovsd %xmm0, 1288(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1216(%rsp,%r15), %xmm1 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(__pow_finite) + + vmovsd %xmm0, 1280(%rsp,%r15) + jmp .LBL_2_7 + +#endif +END (_ZGVeN8vv_pow_skx) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S new file mode 100644 index 0000000000..e35654be8d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sin. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2v_sin) + .type _ZGVbN2v_sin, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_sin_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2v_sin_sse2(%rip), %rax + ret +END (_ZGVbN2v_sin) +libmvec_hidden_def (_ZGVbN2v_sin) + +#define _ZGVbN2v_sin _ZGVbN2v_sin_sse2 +#include "../svml_d_sin2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core_sse4.S new file mode 100644 index 0000000000..393ba03b76 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core_sse4.S @@ -0,0 +1,229 @@ +/* Function sin vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVbN2v_sin_sse4) +/* ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm5 + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + movups __dAbsMask(%rax), %xmm3 +/* + ARGUMENT RANGE REDUCTION: + X' = |X| + */ + movaps %xmm3, %xmm4 + +/* SignX - sign bit of X */ + andnps %xmm5, %xmm3 + movups __dInvPI(%rax), %xmm2 + andps %xmm5, %xmm4 + +/* Y = X'*InvPi + RS : right shifter add */ + mulpd %xmm4, %xmm2 + movups __dRShifter(%rax), %xmm6 + +/* R = X' - N*Pi1 */ + movaps %xmm4, %xmm0 + addpd %xmm6, %xmm2 + cmpnlepd __dRangeVal(%rax), %xmm4 + +/* N = Y - RS : right shifter sub */ + movaps %xmm2, %xmm1 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + psllq $63, %xmm2 + subpd %xmm6, %xmm1 + movmskpd %xmm4, %ecx + movups __dPI1(%rax), %xmm7 + mulpd %xmm1, %xmm7 + movups __dPI2(%rax), %xmm6 + +/* R = R - N*Pi2 */ + mulpd %xmm1, %xmm6 + subpd %xmm7, %xmm0 + movups __dPI3(%rax), %xmm7 + +/* R = R - N*Pi3 */ + mulpd %xmm1, %xmm7 + subpd %xmm6, %xmm0 + movups __dPI4(%rax), %xmm6 + +/* R = R - N*Pi4 */ + mulpd %xmm6, %xmm1 + subpd %xmm7, %xmm0 + subpd %xmm1, %xmm0 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + movaps %xmm0, %xmm1 + mulpd %xmm0, %xmm1 + +/* R = R^SignRes : update sign of reduced argument */ + xorps %xmm2, %xmm0 + movups __dC7_sin(%rax), %xmm2 + mulpd %xmm1, %xmm2 + addpd __dC6_sin(%rax), %xmm2 + mulpd %xmm1, %xmm2 + addpd __dC5_sin(%rax), %xmm2 + mulpd %xmm1, %xmm2 + addpd __dC4_sin(%rax), %xmm2 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + mulpd %xmm1, %xmm2 + addpd __dC3_sin(%rax), %xmm2 + +/* Poly = R2*(C1+R2*(C2+R2*Poly)) */ + mulpd %xmm1, %xmm2 + addpd __dC2_sin(%rax), %xmm2 + mulpd %xmm1, %xmm2 + addpd __dC1_sin(%rax), %xmm2 + mulpd %xmm2, %xmm1 + +/* Poly = Poly*R + R */ + mulpd %xmm0, %xmm1 + addpd %xmm1, %xmm0 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignX + */ + xorps %xmm3, %xmm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm5, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 200(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 192(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVbN2v_sin_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S new file mode 100644 index 0000000000..f4482d3a11 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sin, vector length is 4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4v_sin) + .type _ZGVdN4v_sin, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_sin_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4v_sin_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4v_sin) +libmvec_hidden_def (_ZGVdN4v_sin) + +#define _ZGVdN4v_sin _ZGVdN4v_sin_sse_wrapper +#include "../svml_d_sin4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core_avx2.S new file mode 100644 index 0000000000..b035fa1b15 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core_avx2.S @@ -0,0 +1,210 @@ +/* Function sin vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVdN4v_sin_avx2) +/* ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm4 + vmovupd __dAbsMask(%rax), %ymm2 + vmovupd __dInvPI(%rax), %ymm6 + vmovupd __dRShifter(%rax), %ymm5 + vmovupd __dPI1_FMA(%rax), %ymm7 +/* + ARGUMENT RANGE REDUCTION: + X' = |X| + */ + vandpd %ymm2, %ymm4, %ymm3 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd %ymm5, %ymm3, %ymm6 + +/* N = Y - RS : right shifter sub */ + vsubpd %ymm5, %ymm6, %ymm1 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %ymm6, %ymm5 + +/* R = X' - N*Pi1 */ + vmovapd %ymm3, %ymm0 + vfnmadd231pd %ymm1, %ymm7, %ymm0 + vcmpnle_uqpd __dRangeVal(%rax), %ymm3, %ymm3 + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %ymm1, %ymm0 + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %ymm0, %ymm1 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + vmulpd %ymm1, %ymm1, %ymm0 + +/* R = R^SignRes : update sign of reduced argument */ + vxorpd %ymm5, %ymm1, %ymm6 + vmovupd __dC7_sin(%rax), %ymm1 + vfmadd213pd __dC6_sin(%rax), %ymm0, %ymm1 + vfmadd213pd __dC5_sin(%rax), %ymm0, %ymm1 + vfmadd213pd __dC4_sin(%rax), %ymm0, %ymm1 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3_sin(%rax), %ymm0, %ymm1 + +/* Poly = R2*(C1+R2*(C2+R2*Poly)) */ + vfmadd213pd __dC2_sin(%rax), %ymm0, %ymm1 + vfmadd213pd __dC1_sin(%rax), %ymm0, %ymm1 + +/* SignX - sign bit of X */ + vandnpd %ymm4, %ymm2, %ymm7 + vmulpd %ymm0, %ymm1, %ymm2 + +/* Poly = Poly*R + R */ + vfmadd213pd %ymm6, %ymm6, %ymm2 + vmovmskpd %ymm3, %ecx + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignX + */ + vxorpd %ymm7, %ymm2, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm4, 320(%rsp) + vmovupd %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovupd 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 328(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(sin) + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 320(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(sin) + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4v_sin_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S new file mode 100644 index 0000000000..2b15889c71 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized sin. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8v_sin) + .type _ZGVeN8v_sin, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_sin_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8v_sin_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8v_sin_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8v_sin) + +#define _ZGVeN8v_sin _ZGVeN8v_sin_avx2_wrapper +#include "../svml_d_sin8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S new file mode 100644 index 0000000000..7580e60636 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S @@ -0,0 +1,465 @@ +/* Function sin vectorized with AVX-512, KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_sin_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_sin +#else +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + movq $-1, %rdx + vmovups __dAbsMask(%rax), %zmm6 + vmovups __dInvPI(%rax), %zmm1 + +/* + ARGUMENT RANGE REDUCTION: + X' = |X| + */ + vpandq %zmm6, %zmm0, %zmm12 + vmovups __dPI1_FMA(%rax), %zmm2 + vmovups __dC7_sin(%rax), %zmm7 + +/* SignX - sign bit of X */ + vpandnq %zmm0, %zmm6, %zmm11 + +/* R = X' - N*Pi1 */ + vmovaps %zmm12, %zmm3 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd __dRShifter(%rax), %zmm12, %zmm1 + vcmppd $22, __dRangeVal(%rax), %zmm12, %k1 + vpbroadcastq %rdx, %zmm13{%k1}{z} + +/* N = Y - RS : right shifter sub */ + vsubpd __dRShifter(%rax), %zmm1, %zmm4 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm1, %zmm5 + vptestmq %zmm13, %zmm13, %k0 + vfnmadd231pd %zmm4, %zmm2, %zmm3 + kmovw %k0, %ecx + movzbl %cl, %ecx + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm4, %zmm3 + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %zmm3, %zmm4 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + vmulpd %zmm4, %zmm4, %zmm8 + +/* R = R^SignRes : update sign of reduced argument */ + vpxorq %zmm5, %zmm4, %zmm9 + vfmadd213pd __dC6_sin(%rax), %zmm8, %zmm7 + vfmadd213pd __dC5_sin(%rax), %zmm8, %zmm7 + vfmadd213pd __dC4_sin(%rax), %zmm8, %zmm7 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3_sin(%rax), %zmm8, %zmm7 + +/* Poly = R2*(C1+R2*(C2+R2*Poly)) */ + vfmadd213pd __dC2_sin(%rax), %zmm8, %zmm7 + vfmadd213pd __dC1_sin(%rax), %zmm8, %zmm7 + vmulpd %zmm8, %zmm7, %zmm10 + +/* Poly = Poly*R + R */ + vfmadd213pd %zmm9, %zmm9, %zmm10 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignX + */ + vpxorq %zmm11, %zmm10, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + call JUMPTARGET(sin) + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + call JUMPTARGET(sin) + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_1_7 +#endif +END (_ZGVeN8v_sin_knl) + +ENTRY (_ZGVeN8v_sin_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN4v_sin +#else +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + sin(R) is approximated by corresponding polynomial + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vpbroadcastq .L_2il0floatpacket.14(%rip), %zmm14 + vmovups __dAbsMask(%rax), %zmm7 + vmovups __dInvPI(%rax), %zmm2 + vmovups __dRShifter(%rax), %zmm1 + vmovups __dPI1_FMA(%rax), %zmm3 + vmovups __dC7_sin(%rax), %zmm8 + +/* + ARGUMENT RANGE REDUCTION: + X' = |X| + */ + vandpd %zmm7, %zmm0, %zmm13 + +/* SignX - sign bit of X */ + vandnpd %zmm0, %zmm7, %zmm12 + +/* Y = X'*InvPi + RS : right shifter add */ + vfmadd213pd %zmm1, %zmm13, %zmm2 + vcmppd $18, __dRangeVal(%rax), %zmm13, %k1 + +/* SignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm2, %zmm6 + +/* N = Y - RS : right shifter sub */ + vsubpd %zmm1, %zmm2, %zmm5 + +/* R = X' - N*Pi1 */ + vmovaps %zmm13, %zmm4 + vfnmadd231pd %zmm5, %zmm3, %zmm4 + +/* R = R - N*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm5, %zmm4 + +/* R = R - N*Pi3 */ + vfnmadd132pd __dPI3_FMA(%rax), %zmm4, %zmm5 + +/* + POLYNOMIAL APPROXIMATION: + R2 = R*R + */ + vmulpd %zmm5, %zmm5, %zmm9 + +/* R = R^SignRes : update sign of reduced argument */ + vxorpd %zmm6, %zmm5, %zmm10 + vfmadd213pd __dC6_sin(%rax), %zmm9, %zmm8 + vfmadd213pd __dC5_sin(%rax), %zmm9, %zmm8 + vfmadd213pd __dC4_sin(%rax), %zmm9, %zmm8 + +/* Poly = C3+R2*(C4+R2*(C5+R2*(C6+R2*C7))) */ + vfmadd213pd __dC3_sin(%rax), %zmm9, %zmm8 + +/* Poly = R2*(C1+R2*(C2+R2*Poly)) */ + vfmadd213pd __dC2_sin(%rax), %zmm9, %zmm8 + vfmadd213pd __dC1_sin(%rax), %zmm9, %zmm8 + vmulpd %zmm9, %zmm8, %zmm11 + +/* Poly = Poly*R + R */ + vfmadd213pd %zmm10, %zmm10, %zmm11 + +/* + RECONSTRUCTION: + Final sign setting: Res = Poly^SignX + */ + vxorpd %zmm12, %zmm11, %zmm1 + vpandnq %zmm13, %zmm13, %zmm14{%k1} + vcmppd $3, %zmm14, %zmm14, %k0 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1224(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1216(%rsp,%r15) + jmp .LBL_2_7 +#endif +END (_ZGVeN8v_sin_skx) + + .section .rodata, "a" +.L_2il0floatpacket.14: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.14,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S new file mode 100644 index 0000000000..13279e3fb7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sincos. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN2vvv_sincos) + .type _ZGVbN2vvv_sincos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2vvv_sincos_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN2vvv_sincos_sse2(%rip), %rax + ret +END (_ZGVbN2vvv_sincos) +libmvec_hidden_def (_ZGVbN2vvv_sincos) + +#define _ZGVbN2vvv_sincos _ZGVbN2vvv_sincos_sse2 +#include "../svml_d_sincos2_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S new file mode 100644 index 0000000000..c46109f35d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S @@ -0,0 +1,368 @@ +/* Function sincos vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVbN2vl8l8_sincos_sse4) +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + arg + Pi/2 = (N'*Pi + R') + cos(arg) = sin(arg+Pi/2) = sin(N'*Pi + R') = (-1)^N' * sin(R') + sin(R), sin(R') are approximated by corresponding polynomial. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + movups %xmm11, 160(%rsp) + movups %xmm12, 144(%rsp) + movups __dSignMask(%rax), %xmm11 + +/* ARGUMENT RANGE REDUCTION: + Absolute argument: X' = |X| */ + movaps %xmm11, %xmm4 + +/* Grab sign bit from argument */ + movaps %xmm11, %xmm7 + movups __dInvPI(%rax), %xmm5 + andnps %xmm0, %xmm4 + +/* SinY = X'*InvPi + RS : right shifter add */ + mulpd %xmm4, %xmm5 + addpd __dRShifter(%rax), %xmm5 + +/* SinSignRes = Y<<63 : shift LSB to MSB place for result sign */ + movaps %xmm5, %xmm12 + andps %xmm0, %xmm7 + +/* SinN = Y - RS : right shifter sub */ + subpd __dRShifter(%rax), %xmm5 + movups %xmm10, 176(%rsp) + psllq $63, %xmm12 + movups __dPI1(%rax), %xmm10 + +/* SinR = X' - SinN*Pi1 */ + movaps %xmm10, %xmm1 + mulpd %xmm5, %xmm1 + movups __dPI2(%rax), %xmm6 + +/* SinR = SinR - SinN*Pi1 */ + movaps %xmm6, %xmm2 + mulpd %xmm5, %xmm2 + movups %xmm13, 112(%rsp) + movaps %xmm4, %xmm13 + subpd %xmm1, %xmm13 + subpd %xmm2, %xmm13 + +/* Sine result sign: SinRSign = SignMask & SinR */ + movaps %xmm11, %xmm2 + +/* CosR = SinX - CosN*Pi1 */ + movaps %xmm4, %xmm1 + movups __dOneHalf(%rax), %xmm3 + andps %xmm13, %xmm2 + +/* Set SinRSign to 0.5 */ + orps %xmm2, %xmm3 + +/* Update CosRSign and CosSignRes signs */ + xorps %xmm11, %xmm2 + +/* CosN = SinN +(-)0.5 */ + addpd %xmm5, %xmm3 + cmpnlepd __dRangeVal(%rax), %xmm4 + mulpd %xmm3, %xmm10 + +/* CosR = CosR - CosN*Pi2 */ + mulpd %xmm3, %xmm6 + subpd %xmm10, %xmm1 + movmskpd %xmm4, %ecx + movups __dPI3(%rax), %xmm10 + xorps %xmm12, %xmm2 + subpd %xmm6, %xmm1 + +/* SinR = SinR - SinN*Pi3 */ + movaps %xmm10, %xmm6 + +/* Final reconstruction. + Combine Sin result's sign */ + xorps %xmm7, %xmm12 + mulpd %xmm5, %xmm6 + +/* CosR = CosR - CosN*Pi3 */ + mulpd %xmm3, %xmm10 + subpd %xmm6, %xmm13 + subpd %xmm10, %xmm1 + movups __dPI4(%rax), %xmm6 + +/* SinR = SinR - SinN*Pi4 */ + mulpd %xmm6, %xmm5 + +/* CosR = CosR - CosN*Pi4 */ + mulpd %xmm6, %xmm3 + subpd %xmm5, %xmm13 + subpd %xmm3, %xmm1 + +/* SinR2 = SinR^2 */ + movaps %xmm13, %xmm6 + +/* CosR2 = CosR^2 */ + movaps %xmm1, %xmm10 + mulpd %xmm13, %xmm6 + mulpd %xmm1, %xmm10 + +/* Polynomial approximation */ + movups __dC7(%rax), %xmm5 + movaps %xmm5, %xmm3 + mulpd %xmm6, %xmm3 + mulpd %xmm10, %xmm5 + addpd __dC6(%rax), %xmm3 + addpd __dC6(%rax), %xmm5 + mulpd %xmm6, %xmm3 + mulpd %xmm10, %xmm5 + addpd __dC5(%rax), %xmm3 + addpd __dC5(%rax), %xmm5 + mulpd %xmm6, %xmm3 + mulpd %xmm10, %xmm5 + addpd __dC4(%rax), %xmm3 + addpd __dC4(%rax), %xmm5 + +/* SinPoly = C3 + SinR2*(C4 + SinR2*(C5 + SinR2*(C6 + SinR2*C7))) */ + mulpd %xmm6, %xmm3 + +/* CosPoly = C3 + CosR2*(C4 + CosR2*(C5 + CosR2*(C6 + CosR2*C7))) */ + mulpd %xmm10, %xmm5 + addpd __dC3(%rax), %xmm3 + addpd __dC3(%rax), %xmm5 + +/* SinPoly = C2 + SinR2*SinPoly */ + mulpd %xmm6, %xmm3 + +/* CosPoly = C2 + CosR2*CosPoly */ + mulpd %xmm10, %xmm5 + addpd __dC2(%rax), %xmm3 + addpd __dC2(%rax), %xmm5 + +/* SinPoly = C1 + SinR2*SinPoly */ + mulpd %xmm6, %xmm3 + +/* CosPoly = C1 + CosR2*CosPoly */ + mulpd %xmm10, %xmm5 + addpd __dC1(%rax), %xmm3 + addpd __dC1(%rax), %xmm5 + +/* SinPoly = SinR2*SinPoly */ + mulpd %xmm3, %xmm6 + +/* CosPoly = CosR2*CosPoly */ + mulpd %xmm5, %xmm10 + +/* SinPoly = SinR*SinPoly */ + mulpd %xmm13, %xmm6 + +/* CosPoly = CosR*CosPoly */ + mulpd %xmm1, %xmm10 + addpd %xmm6, %xmm13 + addpd %xmm10, %xmm1 + +/* Update Sin result's sign */ + xorps %xmm12, %xmm13 + +/* Update Cos result's sign */ + xorps %xmm2, %xmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movups 176(%rsp), %xmm10 + movaps %xmm13, (%rdi) + movups 160(%rsp), %xmm11 + movups 144(%rsp), %xmm12 + movups 112(%rsp), %xmm13 + movups %xmm1, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm0, 128(%rsp) + movups %xmm13, 192(%rsp) + movups %xmm1, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 48(%rsp) + movups %xmm9, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 64(%rsp) + movq %r12, 104(%rsp) + cfi_offset_rel_rsp (12, 104) + movb %dl, %r12b + movq %r13, 96(%rsp) + cfi_offset_rel_rsp (13, 96) + movl %eax, %r13d + movq %r14, 88(%rsp) + cfi_offset_rel_rsp (14, 88) + movl %ecx, %r14d + movq %r15, 80(%rsp) + cfi_offset_rel_rsp (15, 80) + movq %rbx, 72(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 48(%rsp), %xmm8 + movq %rbx, %rdi + movups 32(%rsp), %xmm9 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 64(%rsp), %rsi + movq 104(%rsp), %r12 + cfi_restore (%r12) + movq 96(%rsp), %r13 + cfi_restore (%r13) + movq 88(%rsp), %r14 + cfi_restore (%r14) + movq 80(%rsp), %r15 + cfi_restore (%r15) + movq 72(%rsp), %rbx + movups 192(%rsp), %xmm13 + movups 256(%rsp), %xmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 136(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + movsd %xmm0, 200(%rsp,%r15) + movsd 136(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + movsd %xmm0, 264(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + shlq $4, %r15 + movsd 128(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + movsd %xmm0, 192(%rsp,%r15) + movsd 128(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + movsd %xmm0, 256(%rsp,%r15) + jmp .LBL_1_7 +END (_ZGVbN2vl8l8_sincos_sse4) +libmvec_hidden_def(_ZGVbN2vl8l8_sincos_sse4) + +/* vvv version implemented with wrapper to vl8l8 variant. */ +ENTRY (_ZGVbN2vvv_sincos_sse4) +#ifndef __ILP32__ + subq $72, %rsp + .cfi_def_cfa_offset 80 + movdqu %xmm1, 32(%rsp) + lea (%rsp), %rdi + movdqu %xmm2, 48(%rdi) + lea 16(%rsp), %rsi + call HIDDEN_JUMPTARGET(_ZGVbN2vl8l8_sincos_sse4) + movq 32(%rsp), %rdx + movq 48(%rsp), %rsi + movq 40(%rsp), %r8 + movq 56(%rsp), %r10 + movq (%rsp), %rax + movq 16(%rsp), %rcx + movq 8(%rsp), %rdi + movq 24(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq %rdi, (%r8) + movq %r9, (%r10) + addq $72, %rsp + .cfi_def_cfa_offset 8 + ret +#else + subl $72, %esp + .cfi_def_cfa_offset 80 + leal 48(%rsp), %esi + movaps %xmm1, 16(%esp) + leal 32(%rsp), %edi + movaps %xmm2, (%esp) + call HIDDEN_JUMPTARGET(_ZGVbN2vl8l8_sincos_sse4) + movdqa 16(%esp), %xmm1 + movsd 32(%esp), %xmm0 + movq %xmm1, %rax + movdqa (%esp), %xmm2 + movsd %xmm0, (%eax) + movsd 40(%esp), %xmm0 + pextrd $1, %xmm1, %eax + movsd %xmm0, (%eax) + movsd 48(%esp), %xmm0 + movq %xmm2, %rax + movsd %xmm0, (%eax) + movsd 56(%esp), %xmm0 + pextrd $1, %xmm2, %eax + movsd %xmm0, (%eax) + addl $72, %esp + .cfi_def_cfa_offset 8 + ret +#endif +END (_ZGVbN2vvv_sincos_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S new file mode 100644 index 0000000000..8aacb8e76a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sincos. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN4vvv_sincos) + .type _ZGVdN4vvv_sincos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4vvv_sincos_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN4vvv_sincos_sse_wrapper(%rip), %rax + ret +END (_ZGVdN4vvv_sincos) +libmvec_hidden_def (_ZGVdN4vvv_sincos) + +#define _ZGVdN4vvv_sincos _ZGVdN4vvv_sincos_sse_wrapper +#include "../svml_d_sincos4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S new file mode 100644 index 0000000000..a6318c5ca6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S @@ -0,0 +1,373 @@ +/* Function sincos vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" + + .text +ENTRY (_ZGVdN4vl8l8_sincos_avx2) +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + arg + Pi/2 = (N'*Pi + R') + cos(arg) = sin(arg+Pi/2) = sin(N'*Pi + R') = (-1)^N' * sin(R') + sin(R), sin(R') are approximated by corresponding polynomial. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vmovups %ymm14, 288(%rsp) + vmovups %ymm8, 352(%rsp) + vmovupd __dSignMask(%rax), %ymm6 + vmovupd __dInvPI(%rax), %ymm2 + vmovupd __dPI1_FMA(%rax), %ymm5 + vmovups %ymm9, 224(%rsp) + +/* ARGUMENT RANGE REDUCTION: + Absolute argument: X' = |X| */ + vandnpd %ymm0, %ymm6, %ymm1 + +/* SinY = X'*InvPi + RS : right shifter add */ + vfmadd213pd __dRShifter(%rax), %ymm1, %ymm2 + +/* SinSignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %ymm2, %ymm4 + +/* SinN = Y - RS : right shifter sub */ + vsubpd __dRShifter(%rax), %ymm2, %ymm2 + +/* SinR = X' - SinN*Pi1 */ + vmovdqa %ymm1, %ymm14 + vfnmadd231pd %ymm2, %ymm5, %ymm14 + +/* SinR = SinR - SinN*Pi1 */ + vfnmadd231pd __dPI2_FMA(%rax), %ymm2, %ymm14 + +/* Sine result sign: SinRSign = SignMask & SinR */ + vandpd %ymm14, %ymm6, %ymm7 + +/* Set SinRSign to 0.5 */ + vorpd __dOneHalf(%rax), %ymm7, %ymm3 + +/* CosN = SinN +(-)0.5 */ + vaddpd %ymm3, %ymm2, %ymm3 + +/* CosR = SinX - CosN*Pi1 */ + vmovdqa %ymm1, %ymm8 + vfnmadd231pd %ymm3, %ymm5, %ymm8 + vmovupd __dPI3_FMA(%rax), %ymm5 + vcmpnle_uqpd __dRangeVal(%rax), %ymm1, %ymm1 + +/* CosR = CosR - CosN*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %ymm3, %ymm8 + +/* SinR = SinR - SinN*Pi3 */ + vfnmadd213pd %ymm14, %ymm5, %ymm2 + +/* CosR = CosR - CosN*Pi3 */ + vfnmadd213pd %ymm8, %ymm5, %ymm3 + vmovupd __dC6(%rax), %ymm8 + +/* SinR2 = SinR^2 */ + vmulpd %ymm2, %ymm2, %ymm14 + +/* CosR2 = CosR^2 */ + vmulpd %ymm3, %ymm3, %ymm5 + +/* Grab SignX */ + vandpd %ymm0, %ymm6, %ymm9 + +/* Update CosRSign and CosSignRes signs */ + vxorpd %ymm6, %ymm7, %ymm6 + vxorpd %ymm6, %ymm4, %ymm7 + +/* Update sign SinSignRes */ + vxorpd %ymm9, %ymm4, %ymm6 + +/* Polynomial approximation */ + vmovupd __dC7(%rax), %ymm4 + vmovdqa %ymm8, %ymm9 + vfmadd231pd __dC7(%rax), %ymm14, %ymm9 + vfmadd213pd %ymm8, %ymm5, %ymm4 + vfmadd213pd __dC5(%rax), %ymm14, %ymm9 + vfmadd213pd __dC5(%rax), %ymm5, %ymm4 + vfmadd213pd __dC4(%rax), %ymm14, %ymm9 + vfmadd213pd __dC4(%rax), %ymm5, %ymm4 + +/* SinPoly = C3 + SinR2*(C4 + SinR2*(C5 + SinR2*(C6 + SinR2*C7))) */ + vfmadd213pd __dC3(%rax), %ymm14, %ymm9 + +/* CosPoly = C3 + CosR2*(C4 + CosR2*(C5 + CosR2*(C6 + CosR2*C7))) */ + vfmadd213pd __dC3(%rax), %ymm5, %ymm4 + +/* SinPoly = C2 + SinR2*SinPoly */ + vfmadd213pd __dC2(%rax), %ymm14, %ymm9 + +/* CosPoly = C2 + CosR2*CosPoly */ + vfmadd213pd __dC2(%rax), %ymm5, %ymm4 + +/* SinPoly = C1 + SinR2*SinPoly */ + vfmadd213pd __dC1(%rax), %ymm14, %ymm9 + +/* CosPoly = C1 + CosR2*CosPoly */ + vfmadd213pd __dC1(%rax), %ymm5, %ymm4 + +/* SinPoly = SinR2*SinPoly */ + vmulpd %ymm14, %ymm9, %ymm8 + +/* CosPoly = CosR2*CosPoly */ + vmulpd %ymm5, %ymm4, %ymm4 + +/* SinPoly = SinR*SinPoly */ + vfmadd213pd %ymm2, %ymm2, %ymm8 + +/* CosPoly = CosR*CosPoly */ + vfmadd213pd %ymm3, %ymm3, %ymm4 + vmovmskpd %ymm1, %ecx + +/* Final reconstruction + Update Sin result's sign */ + vxorpd %ymm6, %ymm8, %ymm3 + +/* Update Cos result's sign */ + vxorpd %ymm7, %ymm4, %ymm2 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups 352(%rsp), %ymm8 + vmovups 224(%rsp), %ymm9 + vmovups 288(%rsp), %ymm14 + vmovupd %ymm2, (%rsi) + vmovdqa %ymm3, (%rdi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovupd %ymm0, 256(%rsp) + vmovupd %ymm3, 320(%rsp) + vmovupd %ymm2, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm10, 128(%rsp) + vmovups %ymm11, 96(%rsp) + vmovups %ymm12, 64(%rsp) + vmovups %ymm13, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 160(%rsp) + movq %r12, 200(%rsp) + cfi_offset_rel_rsp (12, 200) + movb %dl, %r12b + movq %r13, 192(%rsp) + cfi_offset_rel_rsp (13, 192) + movl %eax, %r13d + movq %r14, 184(%rsp) + cfi_offset_rel_rsp (14, 184) + movl %ecx, %r14d + movq %r15, 176(%rsp) + cfi_offset_rel_rsp (15, 176) + movq %rbx, 168(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 128(%rsp), %ymm10 + movq %rbx, %rdi + vmovups 96(%rsp), %ymm11 + vmovups 64(%rsp), %ymm12 + vmovups 32(%rsp), %ymm13 + vmovups (%rsp), %ymm15 + vmovupd 320(%rsp), %ymm3 + vmovupd 384(%rsp), %ymm2 + movq 160(%rsp), %rsi + movq 200(%rsp), %r12 + cfi_restore (%r12) + movq 192(%rsp), %r13 + cfi_restore (%r13) + movq 184(%rsp), %r14 + cfi_restore (%r14) + movq 176(%rsp), %r15 + cfi_restore (%r15) + movq 168(%rsp), %rbx + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 264(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(sin) + + vmovsd %xmm0, 328(%rsp,%r15) + vmovsd 264(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 392(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 256(%rsp,%r15), %xmm0 + vzeroupper + + call JUMPTARGET(sin) + + vmovsd %xmm0, 320(%rsp,%r15) + vmovsd 256(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 384(%rsp,%r15) + jmp .LBL_1_7 + +END (_ZGVdN4vl8l8_sincos_avx2) +libmvec_hidden_def(_ZGVdN4vl8l8_sincos_avx2) + +/* vvv version implemented with wrapper to vl8l8 variant. */ +ENTRY (_ZGVdN4vvv_sincos_avx2) +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $128, %rsp + vmovdqu %ymm1, 64(%rsp) + lea (%rsp), %rdi + vmovdqu %ymm2, 96(%rdi) + lea 32(%rsp), %rsi + call HIDDEN_JUMPTARGET(_ZGVdN4vl8l8_sincos_avx2) + movq 64(%rsp), %rdx + movq 96(%rsp), %rsi + movq 72(%rsp), %r8 + movq 104(%rsp), %r10 + movq (%rsp), %rax + movq 32(%rsp), %rcx + movq 8(%rsp), %rdi + movq 40(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq 80(%rsp), %rax + movq 112(%rsp), %rcx + movq %rdi, (%r8) + movq %r9, (%r10) + movq 88(%rsp), %rdi + movq 120(%rsp), %r9 + movq 16(%rsp), %r11 + movq 48(%rsp), %rdx + movq 24(%rsp), %rsi + movq 56(%rsp), %r8 + movq %r11, (%rax) + movq %rdx, (%rcx) + movq %rsi, (%rdi) + movq %r8, (%r9) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x78,0x6 + leal -48(%rbp), %esi + leal -80(%rbp), %edi + subl $104, %esp + vmovaps %xmm1, -96(%ebp) + vmovaps %xmm2, -112(%ebp) + call HIDDEN_JUMPTARGET(_ZGVdN4vl8l8_sincos_avx2) + movl -96(%ebp), %eax + vmovsd -80(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -92(%ebp), %eax + vmovsd -72(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -88(%ebp), %eax + vmovsd -64(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -84(%ebp), %eax + vmovsd -56(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -112(%ebp), %eax + vmovsd -48(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -108(%ebp), %eax + vmovsd -40(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -104(%ebp), %eax + vmovsd -32(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -100(%ebp), %eax + vmovsd -24(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + addl $104, %esp + popq %r10 + .cfi_def_cfa 10, 0 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +END (_ZGVdN4vvv_sincos_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S new file mode 100644 index 0000000000..3c0abc379e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized sincos. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN8vvv_sincos) + .type _ZGVeN8vvv_sincos, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8vvv_sincos_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN8vvv_sincos_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN8vvv_sincos_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN8vvv_sincos) + +#define _ZGVeN8vvv_sincos _ZGVeN8vvv_sincos_avx2_wrapper +#include "../svml_d_sincos8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S new file mode 100644 index 0000000000..c9207558c5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S @@ -0,0 +1,763 @@ +/* Function sincos vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_trig_data.h" +#include "svml_d_wrapper_impl.h" + +/* + ALGORITHM DESCRIPTION: + + ( low accuracy ( < 4ulp ) or enhanced performance + ( half of correct mantissa ) implementation ) + + Argument representation: + arg = N*Pi + R + + Result calculation: + sin(arg) = sin(N*Pi + R) = (-1)^N * sin(R) + arg + Pi/2 = (N'*Pi + R') + cos(arg) = sin(arg+Pi/2) = sin(N'*Pi + R') = (-1)^N' * sin(R') + sin(R), sin(R') are approximated by corresponding polynomial. */ + + .text +ENTRY (_ZGVeN8vl8l8_sincos_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_fFF _ZGVdN4vl8l8_sincos +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm4 + movq $-1, %rdx + vmovups __dSignMask(%rax), %zmm12 + vmovups __dInvPI(%rax), %zmm5 + +/* ARGUMENT RANGE REDUCTION: + Absolute argument: X' = |X| */ + vpandnq %zmm4, %zmm12, %zmm3 + vmovups __dPI1_FMA(%rax), %zmm7 + vmovups __dPI3_FMA(%rax), %zmm9 + +/* SinR = X' - SinN*Pi1 */ + vmovaps %zmm3, %zmm8 + +/* CosR = SinX - CosN*Pi1 */ + vmovaps %zmm3, %zmm10 + +/* SinY = X'*InvPi + RS : right shifter add */ + vfmadd213pd __dRShifter(%rax), %zmm3, %zmm5 + vmovups __dC6(%rax), %zmm13 + +/* SinN = Y - RS : right shifter sub */ + vsubpd __dRShifter(%rax), %zmm5, %zmm1 + vmovaps %zmm13, %zmm14 + +/* SinSignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm5, %zmm2 + vcmppd $22, __dRangeVal(%rax), %zmm3, %k1 + +/* Update CosRSign and CosSignRes signs */ + vmovaps %zmm12, %zmm5 + vfnmadd231pd %zmm1, %zmm7, %zmm8 + +/* SinR = SinR - SinN*Pi1 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm1, %zmm8 + +/* Sine result sign: SinRSign = SignMask & SinR */ + vpandq %zmm8, %zmm12, %zmm11 + +/* Set SinRSign to 0.5 */ + vporq __dOneHalf(%rax), %zmm11, %zmm6 + vpternlogq $150, %zmm2, %zmm11, %zmm5 + +/* Update sign SinSignRes */ + vpternlogq $120, %zmm4, %zmm12, %zmm2 + +/* Polynomial approximation */ + vmovups __dC7(%rax), %zmm11 + +/* CosN = SinN +(-)0.5 */ + vaddpd %zmm6, %zmm1, %zmm0 + +/* SinR = SinR - SinN*Pi3 */ + vfnmadd213pd %zmm8, %zmm9, %zmm1 + vfnmadd231pd %zmm0, %zmm7, %zmm10 + +/* SinR2 = SinR^2 */ + vmulpd %zmm1, %zmm1, %zmm15 + +/* Grab SignX + CosR = CosR - CosN*Pi2 */ + vfnmadd231pd __dPI2_FMA(%rax), %zmm0, %zmm10 + vfmadd231pd __dC7(%rax), %zmm15, %zmm14 + +/* CosR = CosR - CosN*Pi3 */ + vfnmadd213pd %zmm10, %zmm9, %zmm0 + vfmadd213pd __dC5(%rax), %zmm15, %zmm14 + +/* CosR2 = CosR^2 */ + vmulpd %zmm0, %zmm0, %zmm12 + vfmadd213pd __dC4(%rax), %zmm15, %zmm14 + vfmadd213pd %zmm13, %zmm12, %zmm11 + +/* SinPoly = C3 + SinR2*(C4 + SinR2*(C5 + SinR2*(C6 + SinR2*C7))) */ + vfmadd213pd __dC3(%rax), %zmm15, %zmm14 + vfmadd213pd __dC5(%rax), %zmm12, %zmm11 + +/* SinPoly = C2 + SinR2*SinPoly */ + vfmadd213pd __dC2(%rax), %zmm15, %zmm14 + vfmadd213pd __dC4(%rax), %zmm12, %zmm11 + +/* SinPoly = C1 + SinR2*SinPoly */ + vfmadd213pd __dC1(%rax), %zmm15, %zmm14 + +/* CosPoly = C3 + CosR2*(C4 + CosR2*(C5 + CosR2*(C6 + CosR2*C7))) */ + vfmadd213pd __dC3(%rax), %zmm12, %zmm11 + +/* SinPoly = SinR2*SinPoly */ + vmulpd %zmm15, %zmm14, %zmm13 + +/* CosPoly = C2 + CosR2*CosPoly */ + vfmadd213pd __dC2(%rax), %zmm12, %zmm11 + +/* SinPoly = SinR*SinPoly */ + vfmadd213pd %zmm1, %zmm1, %zmm13 + vpbroadcastq %rdx, %zmm1{%k1}{z} + +/* CosPoly = C1 + CosR2*CosPoly */ + vfmadd213pd __dC1(%rax), %zmm12, %zmm11 + vptestmq %zmm1, %zmm1, %k0 + kmovw %k0, %ecx + +/* CosPoly = CosR2*CosPoly */ + vmulpd %zmm12, %zmm11, %zmm14 + movzbl %cl, %ecx + +/* CosPoly = CosR*CosPoly */ + vfmadd213pd %zmm0, %zmm0, %zmm14 + +/* Final reconstruction. + Update Sin result's sign */ + vpxorq %zmm2, %zmm13, %zmm0 + +/* Update Cos result's sign */ + vpxorq %zmm5, %zmm14, %zmm2 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups %zmm0, (%rdi) + vmovups %zmm2, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm4, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + vmovups %zmm2, 1280(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %eax, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %ecx, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + movq %rbx, 1064(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + movq %rbx, %rdi + kmovw 1048(%rsp), %k4 + movq 1056(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + kmovw 1032(%rsp), %k6 + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + movq 1064(%rsp), %rbx + vmovups 1216(%rsp), %zmm0 + vmovups 1280(%rsp), %zmm2 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1224(%rsp,%r15) + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1288(%rsp,%r15) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1216(%rsp,%r15) + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1280(%rsp,%r15) + jmp .LBL_1_7 + +#endif +END (_ZGVeN8vl8l8_sincos_knl) +libmvec_hidden_def(_ZGVeN8vl8l8_sincos_knl) + +ENTRY (_ZGVeN8vl8l8_sincos_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_fFF _ZGVdN4vl8l8_sincos +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_d_trig_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm8 + vmovups __dSignMask(%rax), %zmm4 + vmovups __dInvPI(%rax), %zmm9 + vmovups __dRShifter(%rax), %zmm10 + vmovups __dPI1_FMA(%rax), %zmm13 + vmovups __dPI2_FMA(%rax), %zmm14 + vmovups __dOneHalf(%rax), %zmm11 + vmovups __dPI3_FMA(%rax), %zmm2 + +/* ARGUMENT RANGE REDUCTION: + Absolute argument: X' = |X| */ + vandnpd %zmm8, %zmm4, %zmm7 + +/* SinY = X'*InvPi + RS : right shifter add */ + vfmadd213pd %zmm10, %zmm7, %zmm9 + vcmppd $18, __dRangeVal(%rax), %zmm7, %k1 + +/* SinSignRes = Y<<63 : shift LSB to MSB place for result sign */ + vpsllq $63, %zmm9, %zmm6 + +/* SinN = Y - RS : right shifter sub */ + vsubpd %zmm10, %zmm9, %zmm5 + vmovups __dC5(%rax), %zmm9 + vmovups __dC4(%rax), %zmm10 + +/* SinR = X' - SinN*Pi1 */ + vmovaps %zmm7, %zmm15 + vfnmadd231pd %zmm5, %zmm13, %zmm15 + +/* SinR = SinR - SinN*Pi1 */ + vfnmadd231pd %zmm5, %zmm14, %zmm15 + +/* Sine result sign: SinRSign = SignMask & SinR */ + vandpd %zmm15, %zmm4, %zmm1 + +/* Set SinRSign to 0.5 */ + vorpd %zmm1, %zmm11, %zmm12 + vmovups __dC3(%rax), %zmm11 + +/* CosN = SinN +(-)0.5 */ + vaddpd %zmm12, %zmm5, %zmm3 + +/* SinR = SinR - SinN*Pi3 */ + vfnmadd213pd %zmm15, %zmm2, %zmm5 + vmovups __dC2(%rax), %zmm12 + +/* SinR2 = SinR^2 */ + vmulpd %zmm5, %zmm5, %zmm15 + +/* CosR = SinX - CosN*Pi1 */ + vmovaps %zmm7, %zmm0 + vfnmadd231pd %zmm3, %zmm13, %zmm0 + vmovups __dC1(%rax), %zmm13 + +/* Grab SignX + CosR = CosR - CosN*Pi2 */ + vfnmadd231pd %zmm3, %zmm14, %zmm0 + +/* CosR = CosR - CosN*Pi3 */ + vfnmadd213pd %zmm0, %zmm2, %zmm3 + +/* Polynomial approximation */ + vmovups __dC7(%rax), %zmm0 + +/* Update CosRSign and CosSignRes signs */ + vmovaps %zmm4, %zmm2 + vpternlogq $150, %zmm6, %zmm1, %zmm2 + +/* Update sign SinSignRes */ + vpternlogq $120, %zmm8, %zmm4, %zmm6 + +/* CosR2 = CosR^2 */ + vmulpd %zmm3, %zmm3, %zmm1 + vmovups __dC6(%rax), %zmm4 + vmovaps %zmm0, %zmm14 + vfmadd213pd %zmm4, %zmm1, %zmm0 + vfmadd213pd %zmm4, %zmm15, %zmm14 + vfmadd213pd %zmm9, %zmm1, %zmm0 + vfmadd213pd %zmm9, %zmm15, %zmm14 + vfmadd213pd %zmm10, %zmm1, %zmm0 + vfmadd213pd %zmm10, %zmm15, %zmm14 + +/* CosPoly = C3 + CosR2*(C4 + CosR2*(C5 + CosR2*(C6 + CosR2*C7))) */ + vfmadd213pd %zmm11, %zmm1, %zmm0 + +/* SinPoly = C3 + SinR2*(C4 + SinR2*(C5 + SinR2*(C6 + SinR2*C7))) */ + vfmadd213pd %zmm11, %zmm15, %zmm14 + +/* CosPoly = C2 + CosR2*CosPoly */ + vfmadd213pd %zmm12, %zmm1, %zmm0 + +/* SinPoly = C2 + SinR2*SinPoly */ + vfmadd213pd %zmm12, %zmm15, %zmm14 + +/* CosPoly = C1 + CosR2*CosPoly */ + vfmadd213pd %zmm13, %zmm1, %zmm0 + +/* SinPoly = C1 + SinR2*SinPoly */ + vfmadd213pd %zmm13, %zmm15, %zmm14 + +/* CosPoly = CosR2*CosPoly */ + vmulpd %zmm1, %zmm0, %zmm1 + +/* SinPoly = SinR2*SinPoly */ + vmulpd %zmm15, %zmm14, %zmm4 + +/* CosPoly = CosR*CosPoly */ + vfmadd213pd %zmm3, %zmm3, %zmm1 + +/* SinPoly = SinR*SinPoly */ + vfmadd213pd %zmm5, %zmm5, %zmm4 + vpbroadcastq .L_2il0floatpacket.15(%rip), %zmm3 + +/* Update Cos result's sign */ + vxorpd %zmm2, %zmm1, %zmm1 + +/* Final reconstruction. + Update Sin result's sign */ + vxorpd %zmm6, %zmm4, %zmm0 + vpandnq %zmm7, %zmm7, %zmm3{%k1} + vcmppd $3, %zmm3, %zmm3, %k0 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovups %zmm0, (%rdi) + vmovups %zmm1, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm8, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + vmovups %zmm1, 1280(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %eax, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %ecx, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + movq %rbx, 1064(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_2_6: + btl %r13d, %r14d + jc .LBL_2_13 + +.LBL_2_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + movq %rbx, %rdi + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm0 + vmovups 1280(%rsp), %zmm1 + movq 1056(%rsp), %rsi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + movq 1064(%rsp), %rbx + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1160(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1224(%rsp,%r15) + vmovsd 1160(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1288(%rsp,%r15) + jmp .LBL_2_8 + +.LBL_2_13: + movzbl %r12b, %r15d + shlq $4, %r15 + vmovsd 1152(%rsp,%r15), %xmm0 + vzeroupper + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(sin) + + vmovsd %xmm0, 1216(%rsp,%r15) + vmovsd 1152(%rsp,%r15), %xmm0 + + call JUMPTARGET(cos) + + vmovsd %xmm0, 1280(%rsp,%r15) + jmp .LBL_2_7 + +#endif +END (_ZGVeN8vl8l8_sincos_skx) +libmvec_hidden_def(_ZGVeN8vl8l8_sincos_skx) + +/* Wrapper between vvv and vl8l8 vector variants. */ +.macro WRAPPER_AVX512_vvv_vl8l8 callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $256, %rsp + /* Encoding for vmovups %zmm1, 128(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4c + .byte 0x24 + .byte 0x02 + lea (%rsp), %rdi + /* Encoding for vmovups %zmm2, 192(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x57 + .byte 0x03 + lea 64(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 128(%rsp), %rdx + movq 136(%rsp), %rsi + movq 144(%rsp), %r8 + movq 152(%rsp), %r10 + movq (%rsp), %rax + movq 8(%rsp), %rcx + movq 16(%rsp), %rdi + movq 24(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq 160(%rsp), %rax + movq 168(%rsp), %rcx + movq %rdi, (%r8) + movq %r9, (%r10) + movq 176(%rsp), %rdi + movq 184(%rsp), %r9 + movq 32(%rsp), %r11 + movq 40(%rsp), %rdx + movq 48(%rsp), %rsi + movq 56(%rsp), %r8 + movq %r11, (%rax) + movq %rdx, (%rcx) + movq 192(%rsp), %r11 + movq 200(%rsp), %rdx + movq %rsi, (%rdi) + movq %r8, (%r9) + movq 208(%rsp), %rsi + movq 216(%rsp), %r8 + movq 64(%rsp), %r10 + movq 72(%rsp), %rax + movq 80(%rsp), %rcx + movq 88(%rsp), %rdi + movq %r10, (%r11) + movq %rax, (%rdx) + movq 224(%rsp), %r10 + movq 232(%rsp), %rax + movq %rcx, (%rsi) + movq %rdi, (%r8) + movq 240(%rsp), %rcx + movq 248(%rsp), %rdi + movq 96(%rsp), %r9 + movq 104(%rsp), %r11 + movq 112(%rsp), %rdx + movq 120(%rsp), %rsi + movq %r9, (%r10) + movq %r11, (%rax) + movq %rdx, (%rcx) + movq %rsi, (%rdi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-64, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x78,0x6 + leal -112(%rbp), %esi + leal -176(%rbp), %edi + subl $232, %esp + vmovdqa %ymm1, -208(%ebp) + vmovdqa %ymm2, -240(%ebp) + call HIDDEN_JUMPTARGET(\callee) + vmovdqa -208(%ebp), %xmm0 + vmovq %xmm0, %rax + vmovsd -176(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -168(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -200(%ebp), %rax + vmovsd -160(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -152(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -192(%ebp), %rax + vmovsd -144(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -136(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -184(%ebp), %rax + vmovsd -128(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -120(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovdqa -240(%ebp), %xmm0 + vmovq %xmm0, %rax + vmovsd -112(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -104(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -232(%ebp), %rax + vmovsd -96(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -88(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -224(%ebp), %rax + vmovsd -80(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -72(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movq -216(%ebp), %rax + vmovsd -64(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + shrq $32, %rax + vmovsd -56(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + addl $232, %esp + popq %r10 + .cfi_def_cfa 10, 0 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVeN8vvv_sincos_knl) +WRAPPER_AVX512_vvv_vl8l8 _ZGVeN8vl8l8_sincos_knl +END (_ZGVeN8vvv_sincos_knl) + +ENTRY (_ZGVeN8vvv_sincos_skx) +WRAPPER_AVX512_vvv_vl8l8 _ZGVeN8vl8l8_sincos_skx +END (_ZGVeN8vvv_sincos_skx) + + .section .rodata, "a" +.L_2il0floatpacket.15: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.15,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S new file mode 100644 index 0000000000..cd67665972 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized cosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16v_cosf) + .type _ZGVeN16v_cosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_cosf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16v_cosf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16v_cosf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16v_cosf) + +#define _ZGVeN16v_cosf _ZGVeN16v_cosf_avx2_wrapper +#include "../svml_s_cosf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S new file mode 100644 index 0000000000..611bb5dd2d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S @@ -0,0 +1,460 @@ +/* Function cosf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_cosf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_cosf +#else +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) We remove sign using AND operation + b) Add Pi/2 value to argument X for Cos to Sin transformation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Subtract "Right Shifter" value + g) Subtract 0.5 from result for octant correction + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ..... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rdx + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 + */ + vmovaps %zmm0, %zmm6 + movl $-1, %eax + +/* b) Add Pi/2 value to argument X for Cos to Sin transformation */ + vaddps __sHalfPI(%rdx), %zmm0, %zmm2 + vmovups __sRShifter(%rdx), %zmm3 + +/* + 1) Range reduction to [-Pi/2; +Pi/2] interval + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" (0x4B000000) value + */ + vfmadd132ps __sInvPI(%rdx), %zmm3, %zmm2 + vmovups __sPI1_FMA(%rdx), %zmm5 + +/* f) Subtract "Right Shifter" (0x4B000000) value */ + vsubps %zmm3, %zmm2, %zmm4 + vmovups __sA9_FMA(%rdx), %zmm9 + +/* Check for large and special arguments */ + vpandd __sAbsMask(%rdx), %zmm0, %zmm1 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position (S << 31) + */ + vpslld $31, %zmm2, %zmm8 + vcmpps $22, __sRangeReductionVal(%rdx), %zmm1, %k1 + vpbroadcastd %eax, %zmm12{%k1}{z} + +/* g) Subtract 0.5 from result for octant correction */ + vsubps __sOneHalf(%rdx), %zmm4, %zmm7 + vptestmd %zmm12, %zmm12, %k0 + vfnmadd231ps %zmm7, %zmm5, %zmm6 + kmovw %k0, %ecx + vfnmadd231ps __sPI2_FMA(%rdx), %zmm7, %zmm6 + vfnmadd132ps __sPI3_FMA(%rdx), %zmm6, %zmm7 + +/* a) Calculate X^2 = X * X */ + vmulps %zmm7, %zmm7, %zmm10 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vpxord %zmm8, %zmm7, %zmm11 + +/* + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9)))); + */ + vfmadd213ps __sA7_FMA(%rdx), %zmm10, %zmm9 + vfmadd213ps __sA5_FMA(%rdx), %zmm10, %zmm9 + vfmadd213ps __sA3(%rdx), %zmm10, %zmm9 + vmulps %zmm10, %zmm9, %zmm1 + vfmadd213ps %zmm11, %zmm11, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + call JUMPTARGET(cosf) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + call JUMPTARGET(cosf) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_1_7 +#endif +END (_ZGVeN16v_cosf_knl) + +ENTRY (_ZGVeN16v_cosf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_cosf +#else +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) We remove sign using AND operation + b) Add Pi/2 value to argument X for Cos to Sin transformation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Subtract "Right Shifter" value + g) Subtract 0.5 from result for octant correction + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ..... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 + */ + vmovaps %zmm0, %zmm6 + vmovups .L_2il0floatpacket.13(%rip), %zmm12 + vmovups __sRShifter(%rax), %zmm3 + vmovups __sPI1_FMA(%rax), %zmm5 + vmovups __sA9_FMA(%rax), %zmm9 + +/* b) Add Pi/2 value to argument X for Cos to Sin transformation */ + vaddps __sHalfPI(%rax), %zmm0, %zmm2 + +/* Check for large and special arguments */ + vandps __sAbsMask(%rax), %zmm0, %zmm1 + +/* + 1) Range reduction to [-Pi/2; +Pi/2] interval + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" (0x4B000000) value + */ + vfmadd132ps __sInvPI(%rax), %zmm3, %zmm2 + vcmpps $18, __sRangeReductionVal(%rax), %zmm1, %k1 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position (S << 31) + */ + vpslld $31, %zmm2, %zmm8 + +/* f) Subtract "Right Shifter" (0x4B000000) value */ + vsubps %zmm3, %zmm2, %zmm4 + +/* g) Subtract 0.5 from result for octant correction */ + vsubps __sOneHalf(%rax), %zmm4, %zmm7 + vfnmadd231ps %zmm7, %zmm5, %zmm6 + vfnmadd231ps __sPI2_FMA(%rax), %zmm7, %zmm6 + vfnmadd132ps __sPI3_FMA(%rax), %zmm6, %zmm7 + +/* a) Calculate X^2 = X * X */ + vmulps %zmm7, %zmm7, %zmm10 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vxorps %zmm8, %zmm7, %zmm11 + +/* + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9)))); + */ + vfmadd213ps __sA7_FMA(%rax), %zmm10, %zmm9 + vfmadd213ps __sA5_FMA(%rax), %zmm10, %zmm9 + vfmadd213ps __sA3(%rax), %zmm10, %zmm9 + vpandnd %zmm1, %zmm1, %zmm12{%k1} + vmulps %zmm10, %zmm9, %zmm1 + vptestmd %zmm12, %zmm12, %k0 + vfmadd213ps %zmm11, %zmm11, %zmm1 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1156(%rsp,%r15,8), %xmm0 + call JUMPTARGET(cosf) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_2_8 +.LBL_2_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1152(%rsp,%r15,8), %xmm0 + call JUMPTARGET(cosf) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_2_7 +#endif +END (_ZGVeN16v_cosf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.13: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.13,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S new file mode 100644 index 0000000000..d73d7c7e3f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized cosf, vector length is 4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4v_cosf) + .type _ZGVbN4v_cosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_cosf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4v_cosf_sse2(%rip), %rax + ret +END (_ZGVbN4v_cosf) +libmvec_hidden_def (_ZGVbN4v_cosf) + +#define _ZGVbN4v_cosf _ZGVbN4v_cosf_sse2 +#include "../svml_s_cosf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S new file mode 100644 index 0000000000..73797e1a93 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S @@ -0,0 +1,227 @@ +/* Function cosf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY (_ZGVbN4v_cosf_sse4) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) We remove sign using AND operation + b) Add Pi/2 value to argument X for Cos to Sin transformation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Subtract "Right Shifter" value + g) Subtract 0.5 from result for octant correction + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ..... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm4 + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + movups __sHalfPI(%rax), %xmm1 + movups __sRShifter(%rax), %xmm5 + +/* b) Add Pi/2 value to argument X for Cos to Sin transformation */ + addps %xmm4, %xmm1 + +/* + 1) Range reduction to [-Pi/2; +Pi/2] interval + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" (0x4B000000) value + */ + mulps __sInvPI(%rax), %xmm1 + movups __sPI1(%rax), %xmm6 + addps %xmm5, %xmm1 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position (S << 31) + */ + movaps %xmm1, %xmm2 + +/* f) Subtract "Right Shifter" (0x4B000000) value */ + subps %xmm5, %xmm1 + movups __sPI2(%rax), %xmm7 + pslld $31, %xmm2 + movups __sPI3(%rax), %xmm5 + movups __sAbsMask(%rax), %xmm3 + +/* Check for large and special arguments */ + andps %xmm4, %xmm3 + +/* g) Subtract 0.5 from result for octant correction */ + subps __sOneHalf(%rax), %xmm1 + cmpnleps __sRangeReductionVal(%rax), %xmm3 + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + */ + mulps %xmm1, %xmm6 + mulps %xmm1, %xmm7 + mulps %xmm1, %xmm5 + subps %xmm6, %xmm0 + movmskps %xmm3, %ecx + movups __sPI4(%rax), %xmm6 + subps %xmm7, %xmm0 + mulps %xmm6, %xmm1 + subps %xmm5, %xmm0 + subps %xmm1, %xmm0 + +/* a) Calculate X^2 = X * X */ + movaps %xmm0, %xmm1 + mulps %xmm0, %xmm1 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + xorps %xmm2, %xmm0 + movups __sA9(%rax), %xmm2 + +/* + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9)))); + */ + mulps %xmm1, %xmm2 + addps __sA7(%rax), %xmm2 + mulps %xmm1, %xmm2 + addps __sA5(%rax), %xmm2 + mulps %xmm1, %xmm2 + addps __sA3(%rax), %xmm2 + mulps %xmm2, %xmm1 + mulps %xmm0, %xmm1 + addps %xmm1, %xmm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm4, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 196(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + movss %xmm0, 260(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + movss 192(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + movss %xmm0, 256(%rsp,%r15,8) + jmp .LBL_1_7 +END (_ZGVbN4v_cosf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S new file mode 100644 index 0000000000..f7530c138a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized cosf, vector length is 8. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8v_cosf) + .type _ZGVdN8v_cosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_cosf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8v_cosf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8v_cosf) +libmvec_hidden_def (_ZGVdN8v_cosf) + +#define _ZGVdN8v_cosf _ZGVdN8v_cosf_sse_wrapper +#include "../svml_s_cosf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S new file mode 100644 index 0000000000..c61add3bb9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S @@ -0,0 +1,215 @@ +/* Function cosf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY (_ZGVdN8v_cosf_avx2) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) We remove sign using AND operation + b) Add Pi/2 value to argument X for Cos to Sin transformation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Subtract "Right Shifter" value + g) Subtract 0.5 from result for octant correction + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ..... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + vmovaps %ymm0, %ymm2 + vmovups __sRShifter(%rax), %ymm5 + vmovups __sPI1_FMA(%rax), %ymm7 + +/* b) Add Pi/2 value to argument X for Cos to Sin transformation */ + vaddps __sHalfPI(%rax), %ymm2, %ymm4 + +/* + 1) Range reduction to [-Pi/2; +Pi/2] interval + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" (0x4B000000) value + */ + vfmadd132ps __sInvPI(%rax), %ymm5, %ymm4 + +/* f) Subtract "Right Shifter" (0x4B000000) value */ + vsubps %ymm5, %ymm4, %ymm6 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position (S << 31) + */ + vpslld $31, %ymm4, %ymm0 + +/* g) Subtract 0.5 from result for octant correction */ + vsubps __sOneHalf(%rax), %ymm6, %ymm4 + +/* Check for large and special arguments */ + vandps __sAbsMask(%rax), %ymm2, %ymm3 + vcmpnle_uqps __sRangeReductionVal(%rax), %ymm3, %ymm1 + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 + */ + vmovaps %ymm2, %ymm3 + vfnmadd231ps %ymm4, %ymm7, %ymm3 + vfnmadd231ps __sPI2_FMA(%rax), %ymm4, %ymm3 + vfnmadd132ps __sPI3_FMA(%rax), %ymm3, %ymm4 + +/* a) Calculate X^2 = X * X */ + vmulps %ymm4, %ymm4, %ymm5 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vxorps %ymm0, %ymm4, %ymm6 + vmovups __sA9_FMA(%rax), %ymm0 + +/* + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9)))) + */ + vfmadd213ps __sA7_FMA(%rax), %ymm5, %ymm0 + vfmadd213ps __sA5_FMA(%rax), %ymm5, %ymm0 + vfmadd213ps __sA3(%rax), %ymm5, %ymm0 + vmulps %ymm5, %ymm0, %ymm0 + vmovmskps %ymm1, %ecx + vfmadd213ps %ymm6, %ymm6, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm2, 320(%rsp) + vmovups %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovups 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 324(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(cosf) + + vmovss %xmm0, 388(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 320(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(cosf) + + vmovss %xmm0, 384(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVdN8v_cosf_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S new file mode 100644 index 0000000000..3998f616aa --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized expf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16v_expf) + .type _ZGVeN16v_expf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_expf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16v_expf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16v_expf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16v_expf) + +#define _ZGVeN16v_expf _ZGVeN16v_expf_avx2_wrapper +#include "../svml_s_expf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S new file mode 100644 index 0000000000..e80b2be1a7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S @@ -0,0 +1,447 @@ +/* Function expf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_expf_data.h" +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_expf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_expf +#else +/* + ALGORITHM DESCRIPTION: + + Argument representation: + M = rint(X*2^k/ln2) = 2^k*N+j + X = M*ln2/2^k + r = N*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + M = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(N*ln2 + ln2*(j/2^k) + r) + = 2^N * 2^(j/2^k) * exp(r) + 2^N is calculated by bit manipulation + 2^(j/2^k) is computed from table lookup + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. + For low accuracy approximation, exp(r) ~ 1 or 1+r. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_sexp_data@GOTPCREL(%rip), %rax + +/* r = x-n*ln2_hi/2^k */ + vmovaps %zmm0, %zmm6 + +/* compare against threshold */ + movl $-1, %ecx + vmovups __sInvLn2(%rax), %zmm3 + vmovups __sLn2hi(%rax), %zmm5 + +/* m = x*2^k/ln2 + shifter */ + vfmadd213ps __sShifter(%rax), %zmm0, %zmm3 + vmovups __sPC5(%rax), %zmm9 + +/* n = m - shifter = rint(x*2^k/ln2) */ + vsubps __sShifter(%rax), %zmm3, %zmm7 + +/* remove sign of x by "and" operation */ + vpandd __iAbsMask(%rax), %zmm0, %zmm1 + vpaddd __iBias(%rax), %zmm3, %zmm4 + vpcmpgtd __iDomainRange(%rax), %zmm1, %k1 + +/* compute 2^N with "shift" */ + vpslld $23, %zmm4, %zmm8 + vfnmadd231ps %zmm7, %zmm5, %zmm6 + vpbroadcastd %ecx, %zmm2{%k1}{z} + +/* r = r-n*ln2_lo/2^k = x - n*ln2/2^k */ + vfnmadd132ps __sLn2lo(%rax), %zmm6, %zmm7 + +/* set mask for overflow/underflow */ + vptestmd %zmm2, %zmm2, %k0 + kmovw %k0, %ecx + +/* c5*r+c4 */ + vfmadd213ps __sPC4(%rax), %zmm7, %zmm9 + +/* (c5*r+c4)*r+c3 */ + vfmadd213ps __sPC3(%rax), %zmm7, %zmm9 + +/* ((c5*r+c4)*r+c3)*r+c2 */ + vfmadd213ps __sPC2(%rax), %zmm7, %zmm9 + +/* (((c5*r+c4)*r+c3)*r+c2)*r+c1 */ + vfmadd213ps __sPC1(%rax), %zmm7, %zmm9 + +/* exp(r) = ((((c5*r+c4)*r+c3)*r+c2)*r+c1)*r+c0 */ + vfmadd213ps __sPC0(%rax), %zmm7, %zmm9 + +/* 2^N*exp(r) */ + vmulps %zmm9, %zmm8, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__expf_finite) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__expf_finite) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_1_7 + +#endif +END (_ZGVeN16v_expf_knl) + +ENTRY (_ZGVeN16v_expf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_expf +#else +/* + ALGORITHM DESCRIPTION: + + Argument representation: + M = rint(X*2^k/ln2) = 2^k*N+j + X = M*ln2/2^k + r = N*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + M = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(N*ln2 + ln2*(j/2^k) + r) + = 2^N * 2^(j/2^k) * exp(r) + 2^N is calculated by bit manipulation + 2^(j/2^k) is computed from table lookup + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. + For low accuracy approximation, exp(r) ~ 1 or 1+r. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_sexp_data@GOTPCREL(%rip), %rax + +/* r = x-n*ln2_hi/2^k */ + vmovaps %zmm0, %zmm7 + +/* compare against threshold */ + vmovups .L_2il0floatpacket.13(%rip), %zmm3 + vmovups __sInvLn2(%rax), %zmm4 + vmovups __sShifter(%rax), %zmm1 + vmovups __sLn2hi(%rax), %zmm6 + vmovups __sPC5(%rax), %zmm10 + +/* m = x*2^k/ln2 + shifter */ + vfmadd213ps %zmm1, %zmm0, %zmm4 + +/* n = m - shifter = rint(x*2^k/ln2) */ + vsubps %zmm1, %zmm4, %zmm8 + vpaddd __iBias(%rax), %zmm4, %zmm5 + vfnmadd231ps %zmm8, %zmm6, %zmm7 + +/* compute 2^N with "shift" */ + vpslld $23, %zmm5, %zmm9 + +/* r = r-n*ln2_lo/2^k = x - n*ln2/2^k */ + vfnmadd132ps __sLn2lo(%rax), %zmm7, %zmm8 + +/* c5*r+c4 */ + vfmadd213ps __sPC4(%rax), %zmm8, %zmm10 + +/* (c5*r+c4)*r+c3 */ + vfmadd213ps __sPC3(%rax), %zmm8, %zmm10 + +/* ((c5*r+c4)*r+c3)*r+c2 */ + vfmadd213ps __sPC2(%rax), %zmm8, %zmm10 + +/* (((c5*r+c4)*r+c3)*r+c2)*r+c1 */ + vfmadd213ps __sPC1(%rax), %zmm8, %zmm10 + +/* exp(r) = ((((c5*r+c4)*r+c3)*r+c2)*r+c1)*r+c0 */ + vfmadd213ps __sPC0(%rax), %zmm8, %zmm10 + +/* 2^N*exp(r) */ + vmulps %zmm10, %zmm9, %zmm1 + +/* remove sign of x by "and" operation */ + vpandd __iAbsMask(%rax), %zmm0, %zmm2 + vpcmpd $2, __iDomainRange(%rax), %zmm2, %k1 + vpandnd %zmm2, %zmm2, %zmm3{%k1} + +/* set mask for overflow/underflow */ + vptestmd %zmm3, %zmm3, %k0 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__expf_finite) + + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__expf_finite) + + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_2_7 + +#endif +END (_ZGVeN16v_expf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.13: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.13,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S new file mode 100644 index 0000000000..8051720ec2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized expf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4v_expf) + .type _ZGVbN4v_expf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_expf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4v_expf_sse2(%rip), %rax + ret +END (_ZGVbN4v_expf) +libmvec_hidden_def (_ZGVbN4v_expf) + +#define _ZGVbN4v_expf _ZGVbN4v_expf_sse2 +#include "../svml_s_expf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core_sse4.S new file mode 100644 index 0000000000..2bc510bbf7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core_sse4.S @@ -0,0 +1,212 @@ +/* Function expf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_expf_data.h" + + .text +ENTRY (_ZGVbN4v_expf_sse4) +/* + ALGORITHM DESCRIPTION: + + Argument representation: + M = rint(X*2^k/ln2) = 2^k*N+j + X = M*ln2/2^k + r = N*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + M = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(N*ln2 + ln2*(j/2^k) + r) + = 2^N * 2^(j/2^k) * exp(r) + 2^N is calculated by bit manipulation + 2^(j/2^k) is computed from table lookup + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. + For low accuracy approximation, exp(r) ~ 1 or 1+r. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm5 + movq __svml_sexp_data@GOTPCREL(%rip), %rax + movups __sInvLn2(%rax), %xmm0 + +/* m = x*2^k/ln2 + shifter */ + mulps %xmm5, %xmm0 + movups __sShifter(%rax), %xmm6 + movups __sLn2hi(%rax), %xmm4 + addps %xmm6, %xmm0 + +/* n = m - shifter = rint(x*2^k/ln2) */ + movaps %xmm0, %xmm2 + +/* remove sign of x by "and" operation */ + movdqu __iAbsMask(%rax), %xmm7 + subps %xmm6, %xmm2 + +/* r = x-n*ln2_hi/2^k */ + mulps %xmm2, %xmm4 + pand %xmm5, %xmm7 + +/* compare against threshold */ + pcmpgtd __iDomainRange(%rax), %xmm7 + movups __sLn2lo(%rax), %xmm1 + +/* set mask for overflow/underflow */ + movmskps %xmm7, %ecx + movaps %xmm5, %xmm7 + movups __sPC5(%rax), %xmm3 + subps %xmm4, %xmm7 + +/* r = r-n*ln2_lo/2^k = x - n*ln2/2^k */ + mulps %xmm1, %xmm2 + +/* compute 2^N with "shift" */ + movdqu __iBias(%rax), %xmm6 + subps %xmm2, %xmm7 + +/* c5*r+c4 */ + mulps %xmm7, %xmm3 + paddd %xmm6, %xmm0 + pslld $23, %xmm0 + addps __sPC4(%rax), %xmm3 + +/* (c5*r+c4)*r+c3 */ + mulps %xmm7, %xmm3 + addps __sPC3(%rax), %xmm3 + +/* ((c5*r+c4)*r+c3)*r+c2 */ + mulps %xmm7, %xmm3 + addps __sPC2(%rax), %xmm3 + +/* (((c5*r+c4)*r+c3)*r+c2)*r+c1 */ + mulps %xmm7, %xmm3 + addps __sPC1(%rax), %xmm3 + +/* exp(r) = ((((c5*r+c4)*r+c3)*r+c2)*r+c1)*r+c0 */ + mulps %xmm3, %xmm7 + addps __sPC0(%rax), %xmm7 + +/* 2^N*exp(r) */ + mulps %xmm7, %xmm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm5, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 196(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__expf_finite) + + movss %xmm0, 260(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + movss 192(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__expf_finite) + + movss %xmm0, 256(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVbN4v_expf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S new file mode 100644 index 0000000000..6ffb1fd784 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized expf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8v_expf) + .type _ZGVdN8v_expf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_expf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8v_expf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8v_expf) +libmvec_hidden_def (_ZGVdN8v_expf) + +#define _ZGVdN8v_expf _ZGVdN8v_expf_sse_wrapper +#include "../svml_s_expf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core_avx2.S new file mode 100644 index 0000000000..b4a070ac86 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core_avx2.S @@ -0,0 +1,202 @@ +/* Function expf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_expf_data.h" + + .text +ENTRY(_ZGVdN8v_expf_avx2) +/* + ALGORITHM DESCRIPTION: + + Argument representation: + M = rint(X*2^k/ln2) = 2^k*N+j + X = M*ln2/2^k + r = N*ln2 + ln2*(j/2^k) + r + then -ln2/2^(k+1) < r < ln2/2^(k+1) + Alternatively: + M = trunc(X*2^k/ln2) + then 0 < r < ln2/2^k + + Result calculation: + exp(X) = exp(N*ln2 + ln2*(j/2^k) + r) + = 2^N * 2^(j/2^k) * exp(r) + 2^N is calculated by bit manipulation + 2^(j/2^k) is computed from table lookup + exp(r) is approximated by polynomial + + The table lookup is skipped if k = 0. + For low accuracy approximation, exp(r) ~ 1 or 1+r. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_sexp_data@GOTPCREL(%rip), %rax + vmovaps %ymm0, %ymm2 + vmovups __sInvLn2(%rax), %ymm7 + vmovups __sShifter(%rax), %ymm4 + vmovups __sLn2hi(%rax), %ymm3 + vmovups __sPC5(%rax), %ymm1 + +/* m = x*2^k/ln2 + shifter */ + vfmadd213ps %ymm4, %ymm2, %ymm7 + +/* n = m - shifter = rint(x*2^k/ln2) */ + vsubps %ymm4, %ymm7, %ymm0 + vpaddd __iBias(%rax), %ymm7, %ymm4 + +/* remove sign of x by "and" operation */ + vandps __iAbsMask(%rax), %ymm2, %ymm5 + +/* compare against threshold */ + vpcmpgtd __iDomainRange(%rax), %ymm5, %ymm6 + +/* r = x-n*ln2_hi/2^k */ + vmovaps %ymm2, %ymm5 + vfnmadd231ps %ymm0, %ymm3, %ymm5 + +/* r = r-n*ln2_lo/2^k = x - n*ln2/2^k */ + vfnmadd132ps __sLn2lo(%rax), %ymm5, %ymm0 + +/* c5*r+c4 */ + vfmadd213ps __sPC4(%rax), %ymm0, %ymm1 + +/* (c5*r+c4)*r+c3 */ + vfmadd213ps __sPC3(%rax), %ymm0, %ymm1 + +/* ((c5*r+c4)*r+c3)*r+c2 */ + vfmadd213ps __sPC2(%rax), %ymm0, %ymm1 + +/* (((c5*r+c4)*r+c3)*r+c2)*r+c1 */ + vfmadd213ps __sPC1(%rax), %ymm0, %ymm1 + +/* exp(r) = ((((c5*r+c4)*r+c3)*r+c2)*r+c1)*r+c0 */ + vfmadd213ps __sPC0(%rax), %ymm0, %ymm1 + +/* set mask for overflow/underflow */ + vmovmskps %ymm6, %ecx + +/* compute 2^N with "shift" */ + vpslld $23, %ymm4, %ymm6 + +/* 2^N*exp(r) */ + vmulps %ymm1, %ymm6, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm2, 320(%rsp) + vmovups %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovups 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 324(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(__expf_finite) + + vmovss %xmm0, 388(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 320(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(__expf_finite) + + vmovss %xmm0, 384(%rsp,%r15,8) + jmp .LBL_1_7 + +END(_ZGVdN8v_expf_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S new file mode 100644 index 0000000000..8ab03195c6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized logf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16v_logf) + .type _ZGVeN16v_logf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_logf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16v_logf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16v_logf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16v_logf) + +#define _ZGVeN16v_logf _ZGVeN16v_logf_avx2_wrapper +#include "../svml_s_logf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S new file mode 100644 index 0000000000..7ff6fff848 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S @@ -0,0 +1,416 @@ +/* Function logf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_logf_data.h" +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_logf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_logf +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = exponent_x*log(2) + log(mantissa_x), if mantissa_x<4/3 + log(x) = (exponent_x+1)*log(2) + log(0.5*mantissa_x), if mantissa_x>4/3 + + R = mantissa_x - 1, if mantissa_x<4/3 + R = 0.5*mantissa_x - 1, if mantissa_x>4/3 + |R|< 1/3 + + log(1+R) is approximated as a polynomial: degree 9 for 1-ulp, + degree 7 for 4-ulp, degree 3 for half-precision. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_slog_data@GOTPCREL(%rip), %rax + movl $-1, %ecx + +/* reduction: compute r,n */ + vpsubd _iBrkValue(%rax), %zmm0, %zmm2 + vmovups _sPoly_7(%rax), %zmm7 + vpandd _iOffExpoMask(%rax), %zmm2, %zmm3 + +/* exponent_x (mantissa_x<4/3) or exponent_x+1 (mantissa_x>4/3) */ + vpsrad $23, %zmm2, %zmm4 + +/* check for working range, + set special argument mask (denormals/zero/Inf/NaN) + */ + vpaddd _iHiDelta(%rax), %zmm0, %zmm1 + +/* mantissa_x (mantissa_x<4/3), or 0.5*mantissa_x (mantissa_x>4/3) */ + vpaddd _iBrkValue(%rax), %zmm3, %zmm6 + vpcmpd $1, _iLoRange(%rax), %zmm1, %k1 + vcvtdq2ps {rn-sae}, %zmm4, %zmm1 + +/* reduced argument R */ + vsubps _sOne(%rax), %zmm6, %zmm8 + vpbroadcastd %ecx, %zmm5{%k1}{z} + +/* polynomial evaluation starts here */ + vfmadd213ps _sPoly_6(%rax), %zmm8, %zmm7 + vptestmd %zmm5, %zmm5, %k0 + kmovw %k0, %ecx + vfmadd213ps _sPoly_5(%rax), %zmm8, %zmm7 + vfmadd213ps _sPoly_4(%rax), %zmm8, %zmm7 + vfmadd213ps _sPoly_3(%rax), %zmm8, %zmm7 + vfmadd213ps _sPoly_2(%rax), %zmm8, %zmm7 + vfmadd213ps _sPoly_1(%rax), %zmm8, %zmm7 + vmulps %zmm8, %zmm7, %zmm9 + +/* polynomial evaluation end */ + vfmadd213ps %zmm8, %zmm8, %zmm9 + +/* + final reconstruction: + add exponent_value*log2 to polynomial result + */ + vfmadd132ps _sLn2(%rax), %zmm9, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__logf_finite) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__logf_finite) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_1_7 +#endif +END (_ZGVeN16v_logf_knl) + +ENTRY (_ZGVeN16v_logf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_logf +#else +/* + ALGORITHM DESCRIPTION: + + log(x) = exponent_x*log(2) + log(mantissa_x), if mantissa_x<4/3 + log(x) = (exponent_x+1)*log(2) + log(0.5*mantissa_x), if mantissa_x>4/3 + + R = mantissa_x - 1, if mantissa_x<4/3 + R = 0.5*mantissa_x - 1, if mantissa_x>4/3 + |R|< 1/3 + + log(1+R) is approximated as a polynomial: degree 9 for 1-ulp, + degree 7 for 4-ulp, degree 3 for half-precision. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_slog_data@GOTPCREL(%rip), %rax + vmovups .L_2il0floatpacket.7(%rip), %zmm6 + vmovups _iBrkValue(%rax), %zmm4 + vmovups _sPoly_7(%rax), %zmm8 + +/* + check for working range, + set special argument mask (denormals/zero/Inf/NaN) + */ + vpaddd _iHiDelta(%rax), %zmm0, %zmm1 + +/* reduction: compute r,n */ + vpsubd %zmm4, %zmm0, %zmm2 + vpcmpd $5, _iLoRange(%rax), %zmm1, %k1 + +/* exponent_x (mantissa_x<4/3) or exponent_x+1 (mantissa_x>4/3) */ + vpsrad $23, %zmm2, %zmm5 + vpandd _iOffExpoMask(%rax), %zmm2, %zmm3 + +/* mantissa_x (mantissa_x<4/3), or 0.5*mantissa_x (mantissa_x>4/3) */ + vpaddd %zmm4, %zmm3, %zmm7 + +/* reduced argument R */ + vsubps _sOne(%rax), %zmm7, %zmm9 + +/* polynomial evaluation starts here */ + vfmadd213ps _sPoly_6(%rax), %zmm9, %zmm8 + vfmadd213ps _sPoly_5(%rax), %zmm9, %zmm8 + vfmadd213ps _sPoly_4(%rax), %zmm9, %zmm8 + vfmadd213ps _sPoly_3(%rax), %zmm9, %zmm8 + vfmadd213ps _sPoly_2(%rax), %zmm9, %zmm8 + vfmadd213ps _sPoly_1(%rax), %zmm9, %zmm8 + vmulps %zmm9, %zmm8, %zmm10 + +/* polynomial evaluation end */ + vfmadd213ps %zmm9, %zmm9, %zmm10 + vpandnd %zmm1, %zmm1, %zmm6{%k1} + vptestmd %zmm6, %zmm6, %k0 + vcvtdq2ps {rn-sae}, %zmm5, %zmm1 + kmovw %k0, %ecx + +/* + final reconstruction: + add exponent_value*log2 to polynomial result + */ + vfmadd132ps _sLn2(%rax), %zmm10, %zmm1 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__logf_finite) + + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__logf_finite) + + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_2_7 + +#endif +END (_ZGVeN16v_logf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.7: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.7,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S new file mode 100644 index 0000000000..4e0e36d5bd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized logf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4v_logf) + .type _ZGVbN4v_logf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_logf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4v_logf_sse2(%rip), %rax + ret +END (_ZGVbN4v_logf) +libmvec_hidden_def (_ZGVbN4v_logf) + +#define _ZGVbN4v_logf _ZGVbN4v_logf_sse2 +#include "../svml_s_logf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core_sse4.S new file mode 100644 index 0000000000..156face181 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core_sse4.S @@ -0,0 +1,194 @@ +/* Function logf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_logf_data.h" + + .text +ENTRY (_ZGVbN4v_logf_sse4) +/* + ALGORITHM DESCRIPTION: + + log(x) = exponent_x*log(2) + log(mantissa_x), if mantissa_x<4/3 + log(x) = (exponent_x+1)*log(2) + log(0.5*mantissa_x), if mantissa_x>4/3 + + R = mantissa_x - 1, if mantissa_x<4/3 + R = 0.5*mantissa_x - 1, if mantissa_x>4/3 + |R|< 1/3 + + log(1+R) is approximated as a polynomial: degree 9 for 1-ulp, + degree 7 for 4-ulp, degree 3 for half-precision. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + +/* reduction: compute r,n */ + movaps %xmm0, %xmm2 + +/* check for working range, + set special argument mask (denormals/zero/Inf/NaN) */ + movq __svml_slog_data@GOTPCREL(%rip), %rax + movdqu _iHiDelta(%rax), %xmm1 + movdqu _iLoRange(%rax), %xmm4 + paddd %xmm0, %xmm1 + movdqu _iBrkValue(%rax), %xmm3 + pcmpgtd %xmm1, %xmm4 + movdqu _iOffExpoMask(%rax), %xmm1 + psubd %xmm3, %xmm2 + pand %xmm2, %xmm1 + +/* exponent_x (mantissa_x<4/3) or exponent_x+1 (mantissa_x>4/3) */ + psrad $23, %xmm2 + paddd %xmm3, %xmm1 + movups _sPoly_7(%rax), %xmm5 + +/* mantissa_x (mantissa_x<4/3), or 0.5*mantissa_x (mantissa_x>4/3) */ + cvtdq2ps %xmm2, %xmm6 + +/* reduced argument R */ + subps _sOne(%rax), %xmm1 + movmskps %xmm4, %ecx + +/* final reconstruction: + add exponent_value*log2 to polynomial result */ + mulps _sLn2(%rax), %xmm6 + +/* polynomial evaluation starts here */ + mulps %xmm1, %xmm5 + addps _sPoly_6(%rax), %xmm5 + mulps %xmm1, %xmm5 + addps _sPoly_5(%rax), %xmm5 + mulps %xmm1, %xmm5 + addps _sPoly_4(%rax), %xmm5 + mulps %xmm1, %xmm5 + addps _sPoly_3(%rax), %xmm5 + mulps %xmm1, %xmm5 + addps _sPoly_2(%rax), %xmm5 + mulps %xmm1, %xmm5 + addps _sPoly_1(%rax), %xmm5 + mulps %xmm1, %xmm5 + +/* polynomial evaluation end */ + mulps %xmm1, %xmm5 + addps %xmm5, %xmm1 + addps %xmm6, %xmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movdqa %xmm1, %xmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm0, 192(%rsp) + movups %xmm1, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 196(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__logf_finite) + + movss %xmm0, 260(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + movss 192(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(__logf_finite) + + movss %xmm0, 256(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVbN4v_logf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S new file mode 100644 index 0000000000..f4b82de3d4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized logf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8v_logf) + .type _ZGVdN8v_logf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_logf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8v_logf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8v_logf) +libmvec_hidden_def (_ZGVdN8v_logf) + +#define _ZGVdN8v_logf _ZGVdN8v_logf_sse_wrapper +#include "../svml_s_logf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core_avx2.S new file mode 100644 index 0000000000..994af91ffe --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core_avx2.S @@ -0,0 +1,184 @@ +/* Function logf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_logf_data.h" + + .text +ENTRY(_ZGVdN8v_logf_avx2) +/* + ALGORITHM DESCRIPTION: + + log(x) = exponent_x*log(2) + log(mantissa_x), if mantissa_x<4/3 + log(x) = (exponent_x+1)*log(2) + log(0.5*mantissa_x), if mantissa_x>4/3 + + R = mantissa_x - 1, if mantissa_x<4/3 + R = 0.5*mantissa_x - 1, if mantissa_x>4/3 + |R|< 1/3 + + log(1+R) is approximated as a polynomial: degree 9 for 1-ulp, + degree 7 for 4-ulp, degree 3 for half-precision. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_slog_data@GOTPCREL(%rip), %rax + vmovaps %ymm0, %ymm2 + vmovups _iBrkValue(%rax), %ymm6 + vmovups _iLoRange(%rax), %ymm1 +/* check for working range, + set special argument mask (denormals/zero/Inf/NaN) */ + vpaddd _iHiDelta(%rax), %ymm2, %ymm7 + +/* reduction: compute r,n */ + vpsubd %ymm6, %ymm2, %ymm4 + +/* exponent_x (mantissa_x<4/3) or exponent_x+1 (mantissa_x>4/3) */ + vpsrad $23, %ymm4, %ymm3 + vpand _iOffExpoMask(%rax), %ymm4, %ymm5 + vmovups _sPoly_7(%rax), %ymm4 + vcvtdq2ps %ymm3, %ymm0 + +/* mantissa_x (mantissa_x<4/3), or 0.5*mantissa_x (mantissa_x>4/3) */ + vpaddd %ymm6, %ymm5, %ymm3 + +/* reduced argument R */ + vsubps _sOne(%rax), %ymm3, %ymm5 + +/* polynomial evaluation starts here */ + vfmadd213ps _sPoly_6(%rax), %ymm5, %ymm4 + vfmadd213ps _sPoly_5(%rax), %ymm5, %ymm4 + vfmadd213ps _sPoly_4(%rax), %ymm5, %ymm4 + vfmadd213ps _sPoly_3(%rax), %ymm5, %ymm4 + vfmadd213ps _sPoly_2(%rax), %ymm5, %ymm4 + vfmadd213ps _sPoly_1(%rax), %ymm5, %ymm4 + vmulps %ymm5, %ymm4, %ymm6 + +/* polynomial evaluation end */ + vfmadd213ps %ymm5, %ymm5, %ymm6 + vpcmpgtd %ymm7, %ymm1, %ymm1 + vmovmskps %ymm1, %ecx + +/* final reconstruction: + add exponent_value*log2 to polynomial result */ + vfmadd132ps _sLn2(%rax), %ymm6, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm2, 320(%rsp) + vmovups %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovups 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 324(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(__logf_finite) + + vmovss %xmm0, 388(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 320(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(__logf_finite) + + vmovss %xmm0, 384(%rsp,%r15,8) + jmp .LBL_1_7 + +END(_ZGVdN8v_logf_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S new file mode 100644 index 0000000000..6d10c7576f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized powf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16vv_powf) + .type _ZGVeN16vv_powf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16vv_powf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16vv_powf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16vv_powf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16vv_powf) + +#define _ZGVeN16vv_powf _ZGVeN16vv_powf_avx2_wrapper +#include "../svml_s_powf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S new file mode 100644 index 0000000000..fc91a092b0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S @@ -0,0 +1,653 @@ +/* Function powf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_powf_data.h" +#include "svml_s_wrapper_impl.h" + +/* + ALGORITHM DESCRIPTION: + + We are using the next identity : pow(x,y) = 2^(y * log2(x)). + + 1) log2(x) calculation + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where + cq=X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + Log2 result is split by three parts: HH+HL+HLL + + 2) Calculation of y*log2(x) + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(y*log2(x)) + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). Hence + 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + We compute 2^(PH+PL+PLL) as follows: + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + .text +ENTRY (_ZGVeN16vv_powf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_ff _ZGVdN8vv_powf +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_spow_data@GOTPCREL(%rip), %rdx + vmovaps %zmm1, %zmm9 + vshuff32x4 $238, %zmm0, %zmm0, %zmm7 + kxnorw %k3, %k3, %k3 + vcvtps2pd %ymm0, %zmm14 + vcvtps2pd %ymm7, %zmm10 + movl $-1, %eax + movq $-1, %rcx + vpandd _ABSMASK(%rdx), %zmm9, %zmm4 + vmovups _ExpMask(%rdx), %zmm6 + +/* exponent bits selection */ + vpsrlq $20, %zmm14, %zmm13 + vshuff32x4 $238, %zmm9, %zmm9, %zmm8 + vpcmpd $5, _INF(%rdx), %zmm4, %k2 + vpsrlq $32, %zmm13, %zmm15 + vcvtps2pd %ymm8, %zmm2 + vmovups _Two10(%rdx), %zmm4 + vpmovqd %zmm15, %ymm12 + vcvtps2pd %ymm9, %zmm1 + vpsubd _NMINNORM(%rdx), %zmm0, %zmm3 + vpbroadcastd %eax, %zmm8{%k2}{z} + vpcmpd $5, _NMAXVAL(%rdx), %zmm3, %k1 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vmovaps %zmm6, %zmm3 + vpternlogq $248, %zmm6, %zmm10, %zmm4 + vpsrlq $20, %zmm10, %zmm10 + vpternlogq $234, _Two10(%rdx), %zmm14, %zmm3 + +/* reciprocal approximation good to at least 11 bits */ + vrcp28pd %zmm4, %zmm11 + vpsrlq $32, %zmm10, %zmm14 + vpbroadcastd %eax, %zmm7{%k1}{z} + kxnorw %k1, %k1, %k1 + vrcp28pd %zmm3, %zmm5 + vpmovqd %zmm14, %ymm6 + vshufi32x4 $68, %zmm6, %zmm12, %zmm13 + vmovups _One(%rdx), %zmm6 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm5, %zmm14 + +/* biased exponent in DP format */ + vshuff32x4 $238, %zmm13, %zmm13, %zmm5 + vrndscalepd $8, %zmm11, %zmm11 + vcmppd $30, _Threshold(%rdx), %zmm14, %k2 + vcvtdq2pd %ymm13, %zmm10 + vcvtdq2pd %ymm5, %zmm15 + +/* table lookup */ + vpsrlq $40, %zmm14, %zmm13 + vpxord %zmm5, %zmm5, %zmm5 + vgatherqpd _Log2Rcp_lookup(%rdx,%zmm13), %zmm5{%k3} + vfmsub213pd %zmm6, %zmm14, %zmm3 + vfmsub213pd %zmm6, %zmm11, %zmm4 + vcmppd $30, _Threshold(%rdx), %zmm11, %k3 + vpbroadcastq %rcx, %zmm14{%k2}{z} + +/* dpP= _dbT+lJ*T_ITEM_GRAN */ + kxnorw %k2, %k2, %k2 + vpsrlq $40, %zmm11, %zmm12 + vpxord %zmm6, %zmm6, %zmm6 + vpbroadcastq %rcx, %zmm11{%k3}{z} + kxnorw %k3, %k3, %k3 + vgatherqpd _Log2Rcp_lookup(%rdx,%zmm12), %zmm6{%k1} + vmovups _Bias1(%rdx), %zmm12 + vpternlogq $236, _Bias(%rdx), %zmm12, %zmm14 + vpternlogq $248, _Bias(%rdx), %zmm11, %zmm12 + vsubpd %zmm14, %zmm10, %zmm13 + vsubpd %zmm12, %zmm15, %zmm10 + vmovups _poly_coeff_3(%rdx), %zmm11 + vmovups _poly_coeff_4(%rdx), %zmm15 + vfmadd213pd %zmm15, %zmm4, %zmm11 + vmulpd %zmm4, %zmm4, %zmm12 + vmovaps %zmm15, %zmm14 + vmulpd %zmm3, %zmm3, %zmm15 + vfmadd231pd _poly_coeff_3(%rdx), %zmm3, %zmm14 + +/* reconstruction */ + vfmadd213pd %zmm4, %zmm12, %zmm11 + vfmadd213pd %zmm3, %zmm15, %zmm14 + vaddpd %zmm6, %zmm11, %zmm11 + vaddpd %zmm5, %zmm14, %zmm3 + vfmadd231pd _L2(%rdx), %zmm10, %zmm11 + vfmadd132pd _L2(%rdx), %zmm3, %zmm13 + vmulpd %zmm2, %zmm11, %zmm12 + vmulpd %zmm1, %zmm13, %zmm10 + vmulpd __dbInvLn2(%rdx), %zmm12, %zmm6 + +/* hi bits */ + vpsrlq $32, %zmm12, %zmm12 + vmulpd __dbInvLn2(%rdx), %zmm10, %zmm1 + +/* to round down; if dR is an integer we will get R = 1, which is ok */ + vsubpd __dbHALF(%rdx), %zmm6, %zmm4 + vpsrlq $32, %zmm10, %zmm11 + vpmovqd %zmm11, %ymm3 + vsubpd __dbHALF(%rdx), %zmm1, %zmm2 + vaddpd __dbShifter(%rdx), %zmm4, %zmm14 + vpmovqd %zmm12, %ymm4 + vshufi32x4 $68, %zmm4, %zmm3, %zmm5 + vpxord %zmm4, %zmm4, %zmm4 + vaddpd __dbShifter(%rdx), %zmm2, %zmm2 + +/* iAbsX = iAbsX&iAbsMask; */ + vpandd __iAbsMask(%rdx), %zmm5, %zmm11 + vpxord %zmm5, %zmm5, %zmm5 + vsubpd __dbShifter(%rdx), %zmm14, %zmm13 + +/* iRangeMask = (iAbsX>iDomainRange) */ + vpcmpgtd __iDomainRange(%rdx), %zmm11, %k1 + vsubpd __dbShifter(%rdx), %zmm2, %zmm15 + vpbroadcastd %eax, %zmm10{%k1}{z} + vpternlogd $254, %zmm8, %zmm7, %zmm10 + +/* [0..1) */ + vsubpd %zmm15, %zmm1, %zmm1 + +/* low K bits */ + vpandq __lbLOWKBITS(%rdx), %zmm14, %zmm11 + vgatherqpd 13952(%rdx,%zmm11,8), %zmm5{%k3} + vsubpd %zmm13, %zmm6, %zmm7 + vptestmd %zmm10, %zmm10, %k0 + vpandq __lbLOWKBITS(%rdx), %zmm2, %zmm10 + vmulpd __dbC1(%rdx), %zmm1, %zmm1 + vmulpd __dbC1(%rdx), %zmm7, %zmm3 + vpsrlq $11, %zmm2, %zmm8 + vpsrlq $11, %zmm14, %zmm2 + +/* NB : including +/- sign for the exponent!! */ + vpsllq $52, %zmm8, %zmm8 + kmovw %k0, %ecx + vpsllq $52, %zmm2, %zmm6 + vfmadd213pd %zmm5, %zmm3, %zmm5 + vgatherqpd 13952(%rdx,%zmm10,8), %zmm4{%k2} + vfmadd213pd %zmm4, %zmm1, %zmm4 + vpaddq %zmm6, %zmm5, %zmm10 + vcvtpd2ps %zmm10, %ymm12 + vpaddq %zmm8, %zmm4, %zmm7 + vcvtpd2ps %zmm7, %ymm11 + vshuff32x4 $68, %zmm12, %zmm11, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm9, 1216(%rsp) + vmovups %zmm1, 1280(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1280(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vmovss 1220(%rsp,%r15,8), %xmm1 + call JUMPTARGET(__powf_finite) + vmovss %xmm0, 1284(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vmovss 1216(%rsp,%r15,8), %xmm1 + call JUMPTARGET(__powf_finite) + vmovss %xmm0, 1280(%rsp,%r15,8) + jmp .LBL_1_7 +#endif +END (_ZGVeN16vv_powf_knl) + +ENTRY (_ZGVeN16vv_powf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_ff _ZGVdN8vv_powf +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_spow_data@GOTPCREL(%rip), %rax + vextractf32x8 $1, %zmm1, %ymm14 + vextractf32x8 $1, %zmm0, %ymm15 + vpsubd _NMINNORM(%rax), %zmm0, %zmm9 + vmovups %zmm26, 1280(%rsp) + vmovups _ExpMask(%rax), %zmm6 + vpcmpd $1, _NMAXVAL(%rax), %zmm9, %k1 + vcvtps2pd %ymm0, %zmm5 + vcvtps2pd %ymm1, %zmm12 + kxnorw %k3, %k3, %k3 + +/* exponent bits selection */ + vpsrlq $20, %zmm5, %zmm3 + vpsrlq $32, %zmm3, %zmm2 + vpmovqd %zmm2, %ymm11 + vcvtps2pd %ymm14, %zmm13 + vmovups .L_2il0floatpacket.23(%rip), %zmm14 + vmovaps %zmm14, %zmm26 + vpandd _ABSMASK(%rax), %zmm1, %zmm8 + vpcmpd $1, _INF(%rax), %zmm8, %k2 + vpandnd %zmm9, %zmm9, %zmm26{%k1} + vmovups _Two10(%rax), %zmm9 + kxnorw %k1, %k1, %k1 + vcvtps2pd %ymm15, %zmm4 + vmovaps %zmm14, %zmm15 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vpternlogq $248, %zmm6, %zmm4, %zmm9 + vpsrlq $20, %zmm4, %zmm4 + +/* reciprocal approximation good to at least 11 bits */ + vrcp14pd %zmm9, %zmm10 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vrndscalepd $8, %zmm10, %zmm3 + vmovups _One(%rax), %zmm10 + vfmsub213pd %zmm10, %zmm3, %zmm9 + vpandnd %zmm8, %zmm8, %zmm15{%k2} + vmovaps %zmm6, %zmm8 + vpternlogq $234, _Two10(%rax), %zmm5, %zmm8 + vpsrlq $32, %zmm4, %zmm5 + vrcp14pd %zmm8, %zmm7 + vpmovqd %zmm5, %ymm6 + vrndscalepd $8, %zmm7, %zmm2 + vfmsub213pd %zmm10, %zmm2, %zmm8 + +/* table lookup */ + vpsrlq $40, %zmm2, %zmm10 + vinserti32x8 $1, %ymm6, %zmm11, %zmm4 + vpsrlq $40, %zmm3, %zmm11 + +/* biased exponent in DP format */ + vextracti32x8 $1, %zmm4, %ymm7 + vcvtdq2pd %ymm4, %zmm6 + vpmovqd %zmm10, %ymm4 + vpmovqd %zmm11, %ymm5 + vpxord %zmm10, %zmm10, %zmm10 + vgatherdpd _Log2Rcp_lookup(%rax,%ymm4), %zmm10{%k3} + vpbroadcastq .L_2il0floatpacket.24(%rip), %zmm4 + vpxord %zmm11, %zmm11, %zmm11 + vcvtdq2pd %ymm7, %zmm7 + vgatherdpd _Log2Rcp_lookup(%rax,%ymm5), %zmm11{%k1} + vmovups _Threshold(%rax), %zmm5 + vcmppd $21, %zmm2, %zmm5, %k2 + vcmppd $21, %zmm3, %zmm5, %k3 + vmovups _Bias1(%rax), %zmm3 + vmovaps %zmm4, %zmm2 + vpandnq %zmm5, %zmm5, %zmm2{%k2} + vpternlogq $236, _Bias(%rax), %zmm3, %zmm2 + +/* dpP= _dbT+lJ*T_ITEM_GRAN */ + kxnorw %k2, %k2, %k2 + vpandnq %zmm5, %zmm5, %zmm4{%k3} + vpternlogq $248, _Bias(%rax), %zmm4, %zmm3 + vsubpd %zmm2, %zmm6, %zmm4 + vmovups _poly_coeff_3(%rax), %zmm6 + vmovups _poly_coeff_4(%rax), %zmm2 + vsubpd %zmm3, %zmm7, %zmm5 + vmulpd %zmm8, %zmm8, %zmm7 + vfmadd213pd %zmm2, %zmm9, %zmm6 + kxnorw %k3, %k3, %k3 + vmovaps %zmm2, %zmm3 + vmulpd %zmm9, %zmm9, %zmm2 + vfmadd231pd _poly_coeff_3(%rax), %zmm8, %zmm3 + +/* reconstruction */ + vfmadd213pd %zmm9, %zmm2, %zmm6 + vfmadd213pd %zmm8, %zmm7, %zmm3 + vaddpd %zmm11, %zmm6, %zmm8 + vaddpd %zmm10, %zmm3, %zmm9 + vfmadd231pd _L2(%rax), %zmm5, %zmm8 + vfmadd132pd _L2(%rax), %zmm9, %zmm4 + vmulpd %zmm13, %zmm8, %zmm13 + vmulpd %zmm12, %zmm4, %zmm3 + vmulpd __dbInvLn2(%rax), %zmm13, %zmm10 + vmulpd __dbInvLn2(%rax), %zmm3, %zmm8 + +/* hi bits */ + vpsrlq $32, %zmm3, %zmm4 + vpsrlq $32, %zmm13, %zmm13 + +/* to round down; if dR is an integer we will get R = 1, which is ok */ + vsubpd __dbHALF(%rax), %zmm8, %zmm12 + vpmovqd %zmm4, %ymm5 + vpmovqd %zmm13, %ymm2 + vsubpd __dbHALF(%rax), %zmm10, %zmm9 + vaddpd __dbShifter(%rax), %zmm12, %zmm7 + vaddpd __dbShifter(%rax), %zmm9, %zmm9 + vsubpd __dbShifter(%rax), %zmm7, %zmm11 + vsubpd __dbShifter(%rax), %zmm9, %zmm12 + vinserti32x8 $1, %ymm2, %zmm5, %zmm3 + +/* iAbsX = iAbsX&iAbsMask */ + vpandd __iAbsMask(%rax), %zmm3, %zmm4 + +/* iRangeMask = (iAbsX>iDomainRange) */ + vpcmpd $2, __iDomainRange(%rax), %zmm4, %k1 + vpandnd %zmm4, %zmm4, %zmm14{%k1} + vpternlogd $254, %zmm15, %zmm26, %zmm14 + +/* [0..1) */ + vsubpd %zmm11, %zmm8, %zmm15 + vsubpd %zmm12, %zmm10, %zmm26 + vptestmd %zmm14, %zmm14, %k0 + vpsrlq $11, %zmm7, %zmm8 + vpsrlq $11, %zmm9, %zmm10 + vmulpd __dbC1(%rax), %zmm26, %zmm26 + vmulpd __dbC1(%rax), %zmm15, %zmm15 + +/* NB : including +/- sign for the exponent!! */ + vpsllq $52, %zmm10, %zmm13 + vpsllq $52, %zmm8, %zmm12 + kmovw %k0, %ecx + +/* low K bits */ + vpandq __lbLOWKBITS(%rax), %zmm9, %zmm14 + vpandq __lbLOWKBITS(%rax), %zmm7, %zmm6 + vpmovqd %zmm14, %ymm7 + vpmovqd %zmm6, %ymm9 + vpxord %zmm2, %zmm2, %zmm2 + vgatherdpd 13952(%rax,%ymm7,8), %zmm2{%k3} + vfmadd213pd %zmm2, %zmm26, %zmm2 + vpaddq %zmm13, %zmm2, %zmm2 + vcvtpd2ps %zmm2, %ymm4 + vpxord %zmm11, %zmm11, %zmm11 + vgatherdpd 13952(%rax,%ymm9,8), %zmm11{%k2} + vfmadd213pd %zmm11, %zmm15, %zmm11 + vpaddq %zmm12, %zmm11, %zmm3 + vcvtpd2ps %zmm3, %ymm5 + vinsertf32x8 $1, %ymm4, %zmm5, %zmm2 + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovups 1280(%rsp), %zmm26 + vmovaps %zmm2, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1088(%rsp) + vmovups %zmm1, 1152(%rsp) + vmovups %zmm2, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 984(%rsp) + kmovw %k5, 976(%rsp) + kmovw %k6, 968(%rsp) + kmovw %k7, 960(%rsp) + vmovups %zmm16, 896(%rsp) + vmovups %zmm17, 832(%rsp) + vmovups %zmm18, 768(%rsp) + vmovups %zmm19, 704(%rsp) + vmovups %zmm20, 640(%rsp) + vmovups %zmm21, 576(%rsp) + vmovups %zmm22, 512(%rsp) + vmovups %zmm23, 448(%rsp) + vmovups %zmm24, 384(%rsp) + vmovups %zmm25, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1000(%rsp) + movq %rdi, 992(%rsp) + movq %r12, 1032(%rsp) + cfi_offset_rel_rsp (12, 1032) + movb %dl, %r12b + movq %r13, 1024(%rsp) + cfi_offset_rel_rsp (13, 1024) + movl %ecx, %r13d + movq %r14, 1016(%rsp) + cfi_offset_rel_rsp (14, 1016) + movl %eax, %r14d + movq %r15, 1008(%rsp) + cfi_offset_rel_rsp (15, 1008) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 984(%rsp), %k4 + kmovw 976(%rsp), %k5 + kmovw 968(%rsp), %k6 + kmovw 960(%rsp), %k7 + vmovups 896(%rsp), %zmm16 + vmovups 832(%rsp), %zmm17 + vmovups 768(%rsp), %zmm18 + vmovups 704(%rsp), %zmm19 + vmovups 640(%rsp), %zmm20 + vmovups 576(%rsp), %zmm21 + vmovups 512(%rsp), %zmm22 + vmovups 448(%rsp), %zmm23 + vmovups 384(%rsp), %zmm24 + vmovups 320(%rsp), %zmm25 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm2 + movq 1000(%rsp), %rsi + movq 992(%rsp), %rdi + movq 1032(%rsp), %r12 + cfi_restore (%r12) + movq 1024(%rsp), %r13 + cfi_restore (%r13) + movq 1016(%rsp), %r14 + cfi_restore (%r14) + movq 1008(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm1 + vzeroupper + vmovss 1092(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__powf_finite) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm1 + vzeroupper + vmovss 1088(%rsp,%r15,8), %xmm0 + call JUMPTARGET(__powf_finite) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_2_7 +#endif +END (_ZGVeN16vv_powf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.23: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.23,@object +.L_2il0floatpacket.24: + .long 0xffffffff,0xffffffff + .type .L_2il0floatpacket.24,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S new file mode 100644 index 0000000000..785b549882 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized powf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4vv_powf) + .type _ZGVbN4vv_powf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4vv_powf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4vv_powf_sse2(%rip), %rax + ret +END (_ZGVbN4vv_powf) +libmvec_hidden_def (_ZGVbN4vv_powf) + +#define _ZGVbN4vv_powf _ZGVbN4vv_powf_sse2 +#include "../svml_s_powf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core_sse4.S new file mode 100644 index 0000000000..8b1b4e74bb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core_sse4.S @@ -0,0 +1,374 @@ +/* Function powf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_powf_data.h" + + .text +ENTRY (_ZGVbN4vv_powf_sse4) +/* + ALGORITHM DESCRIPTION: + + We are using the next identity: pow(x,y) = 2^(y * log2(x)). + + 1) log2(x) calculation + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where + cq=X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + Log2 result is split by three parts: HH+HL+HLL + + 2) Calculation of y*log2(x) + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(y*log2(x)) + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). Hence + 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + We compute 2^(PH+PL+PLL) as follows: + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $256, %rsp + movaps %xmm0, %xmm3 + movhlps %xmm0, %xmm3 + movaps %xmm1, %xmm5 + movups %xmm8, 112(%rsp) + movaps %xmm5, %xmm2 + cvtps2pd %xmm3, %xmm8 + cvtps2pd %xmm5, %xmm7 + movups %xmm9, 96(%rsp) + movaps %xmm0, %xmm4 + cvtps2pd %xmm0, %xmm9 + movq __svml_spow_data@GOTPCREL(%rip), %rdx + movups %xmm10, 176(%rsp) + movups %xmm13, 48(%rsp) + movups _ExpMask(%rdx), %xmm6 + +/* preserve mantissa, set input exponent to 2^(-10) */ + movaps %xmm6, %xmm10 + andps %xmm8, %xmm6 + andps %xmm9, %xmm10 + +/* exponent bits selection */ + psrlq $20, %xmm9 + orps _Two10(%rdx), %xmm6 + psrlq $20, %xmm8 + orps _Two10(%rdx), %xmm10 + +/* reciprocal approximation good to at least 11 bits */ + cvtpd2ps %xmm6, %xmm13 + cvtpd2ps %xmm10, %xmm1 + movlhps %xmm13, %xmm13 + movhlps %xmm5, %xmm2 + movlhps %xmm1, %xmm1 + movups %xmm12, 208(%rsp) + rcpps %xmm13, %xmm12 + movups %xmm11, 80(%rsp) + cvtps2pd %xmm2, %xmm11 + rcpps %xmm1, %xmm2 + movups %xmm14, 144(%rsp) + cvtps2pd %xmm12, %xmm14 + movups %xmm15, 160(%rsp) + cvtps2pd %xmm2, %xmm15 + shufps $221, %xmm8, %xmm9 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + roundpd $0, %xmm14, %xmm14 + +/* biased exponent in DP format */ + pshufd $238, %xmm9, %xmm8 + roundpd $0, %xmm15, %xmm15 + cvtdq2pd %xmm8, %xmm1 + mulpd %xmm15, %xmm10 + mulpd %xmm14, %xmm6 + cvtdq2pd %xmm9, %xmm2 + subpd _One(%rdx), %xmm10 + subpd _One(%rdx), %xmm6 + +/* table lookup */ + movaps %xmm14, %xmm8 + movaps %xmm15, %xmm9 + psrlq $40, %xmm8 + psrlq $40, %xmm9 + movd %xmm8, %r8d + movd %xmm9, %eax + psubd _NMINNORM(%rdx), %xmm4 + movdqu _ABSMASK(%rdx), %xmm3 + pextrd $2, %xmm8, %r9d + pand %xmm5, %xmm3 + movups _Threshold(%rdx), %xmm8 + pextrd $2, %xmm9, %ecx + movaps %xmm8, %xmm9 + cmpltpd %xmm15, %xmm9 + cmpltpd %xmm14, %xmm8 + andps _Bias(%rdx), %xmm9 + movaps %xmm10, %xmm14 + andps _Bias(%rdx), %xmm8 + movaps %xmm6, %xmm15 + orps _Bias1(%rdx), %xmm9 + orps _Bias1(%rdx), %xmm8 + subpd %xmm9, %xmm2 + subpd %xmm8, %xmm1 + mulpd %xmm10, %xmm14 + mulpd %xmm6, %xmm15 + mulpd _L2(%rdx), %xmm2 + mulpd _L2(%rdx), %xmm1 + movups _poly_coeff_3(%rdx), %xmm9 + movaps %xmm9, %xmm8 + mulpd %xmm10, %xmm8 + mulpd %xmm6, %xmm9 + addpd _poly_coeff_4(%rdx), %xmm8 + addpd _poly_coeff_4(%rdx), %xmm9 + mulpd %xmm14, %xmm8 + mulpd %xmm15, %xmm9 + +/* reconstruction */ + addpd %xmm8, %xmm10 + addpd %xmm9, %xmm6 + movslq %eax, %rax + movslq %r8d, %r8 + movslq %ecx, %rcx + movslq %r9d, %r9 + movsd _Log2Rcp_lookup(%rdx,%rax), %xmm13 + movsd _Log2Rcp_lookup(%rdx,%r8), %xmm12 + movhpd _Log2Rcp_lookup(%rdx,%rcx), %xmm13 + movhpd _Log2Rcp_lookup(%rdx,%r9), %xmm12 + addpd %xmm10, %xmm13 + addpd %xmm6, %xmm12 + addpd %xmm13, %xmm2 + addpd %xmm12, %xmm1 + mulpd %xmm7, %xmm2 + mulpd %xmm11, %xmm1 + movups __dbInvLn2(%rdx), %xmm11 + movdqa %xmm4, %xmm12 + movaps %xmm11, %xmm10 + mulpd %xmm2, %xmm10 + mulpd %xmm1, %xmm11 + +/* to round down; if dR is an integer we will get R = 1, which is ok */ + movaps %xmm10, %xmm8 + movaps %xmm11, %xmm9 + subpd __dbHALF(%rdx), %xmm8 + subpd __dbHALF(%rdx), %xmm9 + addpd __dbShifter(%rdx), %xmm8 + addpd __dbShifter(%rdx), %xmm9 + movaps %xmm8, %xmm6 + movaps %xmm9, %xmm7 + subpd __dbShifter(%rdx), %xmm6 + subpd __dbShifter(%rdx), %xmm7 + +/* [0..1) */ + subpd %xmm6, %xmm10 + subpd %xmm7, %xmm11 + mulpd __dbC1(%rdx), %xmm10 + mulpd __dbC1(%rdx), %xmm11 + +/* hi bits */ + shufps $221, %xmm1, %xmm2 + movdqu _NMAXVAL(%rdx), %xmm1 + pcmpgtd %xmm1, %xmm12 + pcmpeqd %xmm1, %xmm4 + por %xmm4, %xmm12 + movdqa %xmm3, %xmm1 + movdqu _INF(%rdx), %xmm4 + pcmpgtd %xmm4, %xmm1 + pcmpeqd %xmm4, %xmm3 + +/* iAbsX = iAbsX&iAbsMask */ + pand __iAbsMask(%rdx), %xmm2 + por %xmm3, %xmm1 + +/* iRangeMask = (iAbsX>iDomainRange) */ + pcmpgtd __iDomainRange(%rdx), %xmm2 + por %xmm1, %xmm12 + movups __lbLOWKBITS(%rdx), %xmm3 + por %xmm2, %xmm12 + +/* low K bits */ + movaps %xmm3, %xmm2 + andps %xmm9, %xmm3 + andps %xmm8, %xmm2 + psrlq $11, %xmm8 + +/* dpP= _dbT+lJ*T_ITEM_GRAN */ + movd %xmm2, %r10d + psrlq $11, %xmm9 + movd %xmm3, %ecx + +/* NB : including +/- sign for the exponent!! */ + psllq $52, %xmm8 + psllq $52, %xmm9 + pextrw $4, %xmm2, %r11d + pextrw $4, %xmm3, %r8d + movmskps %xmm12, %eax + shll $3, %r10d + shll $3, %ecx + shll $3, %r11d + shll $3, %r8d + movq 13952(%rdx,%r10), %xmm6 + movq 13952(%rdx,%rcx), %xmm7 + movhpd 13952(%rdx,%r11), %xmm6 + movhpd 13952(%rdx,%r8), %xmm7 + mulpd %xmm6, %xmm10 + mulpd %xmm7, %xmm11 + addpd %xmm10, %xmm6 + addpd %xmm11, %xmm7 + paddq %xmm8, %xmm6 + paddq %xmm9, %xmm7 + cvtpd2ps %xmm6, %xmm1 + cvtpd2ps %xmm7, %xmm4 + movlhps %xmm4, %xmm1 + testl %eax, %eax + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movups 112(%rsp), %xmm8 + movaps %xmm1, %xmm0 + movups 96(%rsp), %xmm9 + movups 176(%rsp), %xmm10 + movups 80(%rsp), %xmm11 + movups 208(%rsp), %xmm12 + movups 48(%rsp), %xmm13 + movups 144(%rsp), %xmm14 + movups 160(%rsp), %xmm15 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm0, 64(%rsp) + movups %xmm5, 128(%rsp) + movups %xmm1, 192(%rsp) + je .LBL_1_2 + + xorb %cl, %cl + xorl %edx, %edx + movq %rsi, 8(%rsp) + movq %rdi, (%rsp) + movq %r12, 40(%rsp) + cfi_offset_rel_rsp (12, 40) + movb %cl, %r12b + movq %r13, 32(%rsp) + cfi_offset_rel_rsp (13, 32) + movl %eax, %r13d + movq %r14, 24(%rsp) + cfi_offset_rel_rsp (14, 24) + movl %edx, %r14d + movq %r15, 16(%rsp) + cfi_offset_rel_rsp (15, 16) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movq 8(%rsp), %rsi + movq (%rsp), %rdi + movq 40(%rsp), %r12 + cfi_restore (%r12) + movq 32(%rsp), %r13 + cfi_restore (%r13) + movq 24(%rsp), %r14 + cfi_restore (%r14) + movq 16(%rsp), %r15 + cfi_restore (%r15) + movups 192(%rsp), %xmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 68(%rsp,%r15,8), %xmm0 + movss 132(%rsp,%r15,8), %xmm1 + + call JUMPTARGET(__powf_finite) + + movss %xmm0, 196(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + movss 64(%rsp,%r15,8), %xmm0 + movss 128(%rsp,%r15,8), %xmm1 + + call JUMPTARGET(__powf_finite) + + movss %xmm0, 192(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVbN4vv_powf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S new file mode 100644 index 0000000000..1f6a07315e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized powf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8vv_powf) + .type _ZGVdN8vv_powf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8vv_powf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8vv_powf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8vv_powf) +libmvec_hidden_def (_ZGVdN8vv_powf) + +#define _ZGVdN8vv_powf _ZGVdN8vv_powf_sse_wrapper +#include "../svml_s_powf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core_avx2.S new file mode 100644 index 0000000000..683932f410 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core_avx2.S @@ -0,0 +1,357 @@ +/* Function powf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_powf_data.h" + + .text +ENTRY(_ZGVdN8vv_powf_avx2) +/* + ALGORITHM DESCRIPTION: + + We are using the next identity : pow(x,y) = 2^(y * log2(x)). + + 1) log2(x) calculation + Here we use the following formula. + Let |x|=2^k1*X1, where k1 is integer, 1<=X1<2. + Let C ~= 1/ln(2), + Rcp1 ~= 1/X1, X2=Rcp1*X1, + Rcp2 ~= 1/X2, X3=Rcp2*X2, + Rcp3 ~= 1/X3, Rcp3C ~= C/X3. + Then + log2|x| = k1 + log2(1/Rcp1) + log2(1/Rcp2) + log2(C/Rcp3C) + + log2(X1*Rcp1*Rcp2*Rcp3C/C), + where X1*Rcp1*Rcp2*Rcp3C = C*(1+q), q is very small. + + The values of Rcp1, log2(1/Rcp1), Rcp2, log2(1/Rcp2), + Rcp3C, log2(C/Rcp3C) are taken from tables. + Values of Rcp1, Rcp2, Rcp3C are such that RcpC=Rcp1*Rcp2*Rcp3C + is exactly represented in target precision. + + log2(X1*Rcp1*Rcp2*Rcp3C/C) = log2(1+q) = ln(1+q)/ln2 = + = 1/(ln2)*q - 1/(2ln2)*q^2 + 1/(3ln2)*q^3 - ... = + = 1/(C*ln2)*cq - 1/(2*C^2*ln2)*cq^2 + 1/(3*C^3*ln2)*cq^3 - ... = + = (1 + a1)*cq + a2*cq^2 + a3*cq^3 + ..., + where + cq=X1*Rcp1*Rcp2*Rcp3C-C, + a1=1/(C*ln(2))-1 is small, + a2=1/(2*C^2*ln2), + a3=1/(3*C^3*ln2), + ... + Log2 result is split by three parts: HH+HL+HLL + + 2) Calculation of y*log2(x) + Split y into YHi+YLo. + Get high PH and medium PL parts of y*log2|x|. + Get low PLL part of y*log2|x|. + Now we have PH+PL+PLL ~= y*log2|x|. + + 3) Calculation of 2^(y*log2(x)) + Let's represent PH+PL+PLL in the form N + j/2^expK + Z, + where expK=7 in this implementation, N and j are integers, + 0<=j<=2^expK-1, |Z|<2^(-expK-1). Hence + 2^(PH+PL+PLL) ~= 2^N * 2^(j/2^expK) * 2^Z, + where 2^(j/2^expK) is stored in a table, and + 2^Z ~= 1 + B1*Z + B2*Z^2 ... + B5*Z^5. + We compute 2^(PH+PL+PLL) as follows: + Break PH into PHH + PHL, where PHH = N + j/2^expK. + Z = PHL + PL + PLL + Exp2Poly = B1*Z + B2*Z^2 ... + B5*Z^5 + Get 2^(j/2^expK) from table in the form THI+TLO. + Now we have 2^(PH+PL+PLL) ~= 2^N * (THI + TLO) * (1 + Exp2Poly). + Get significand of 2^(PH+PL+PLL) in the form ResHi+ResLo: + ResHi := THI + ResLo := THI * Exp2Poly + TLO + Get exponent ERes of the result: + Res := ResHi + ResLo: + Result := ex(Res) + N. */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + lea __VPACK_ODD_ind.6357.0.1(%rip), %rcx + vmovups %ymm14, 320(%rsp) + +/* hi bits */ + lea __VPACK_ODD_ind.6358.0.1(%rip), %rax + vmovups %ymm12, 256(%rsp) + vmovups %ymm9, 96(%rsp) + vmovups %ymm13, 224(%rsp) + vmovups %ymm15, 352(%rsp) + vmovups %ymm11, 384(%rsp) + vmovups %ymm10, 288(%rsp) + vmovups (%rcx), %ymm10 + vmovups %ymm8, 160(%rsp) + vmovdqa %ymm1, %ymm9 + movq __svml_spow_data@GOTPCREL(%rip), %rdx + vextractf128 $1, %ymm0, %xmm7 + vcvtps2pd %xmm0, %ymm14 + vcvtps2pd %xmm7, %ymm12 + vpsubd _NMINNORM(%rdx), %ymm0, %ymm7 + +/* preserve mantissa, set input exponent to 2^(-10) */ + vandpd _ExpMask(%rdx), %ymm14, %ymm3 + vandpd _ExpMask(%rdx), %ymm12, %ymm13 + +/* exponent bits selection */ + vpsrlq $20, %ymm12, %ymm12 + vpsrlq $20, %ymm14, %ymm14 + vextractf128 $1, %ymm9, %xmm2 + vcvtps2pd %xmm9, %ymm1 + vpand _ABSMASK(%rdx), %ymm9, %ymm8 + vcvtps2pd %xmm2, %ymm6 + vorpd _Two10(%rdx), %ymm3, %ymm2 + vorpd _Two10(%rdx), %ymm13, %ymm3 + +/* reciprocal approximation good to at least 11 bits */ + vcvtpd2ps %ymm2, %xmm5 + vcvtpd2ps %ymm3, %xmm15 + vrcpps %xmm5, %xmm4 + vrcpps %xmm15, %xmm11 + vcvtps2pd %xmm4, %ymm13 + vcvtps2pd %xmm11, %ymm4 + vpermps %ymm12, %ymm10, %ymm11 + +/* round reciprocal to nearest integer, will have 1+9 mantissa bits */ + vroundpd $0, %ymm13, %ymm12 + vpermps %ymm14, %ymm10, %ymm5 + vroundpd $0, %ymm4, %ymm14 + vmovupd _One(%rdx), %ymm4 + +/* table lookup */ + vpsrlq $40, %ymm12, %ymm10 + vfmsub213pd %ymm4, %ymm12, %ymm2 + vfmsub213pd %ymm4, %ymm14, %ymm3 + vcmpgt_oqpd _Threshold(%rdx), %ymm12, %ymm12 + vxorpd %ymm4, %ymm4, %ymm4 + vandpd _Bias(%rdx), %ymm12, %ymm12 + +/* biased exponent in DP format */ + vcvtdq2pd %xmm11, %ymm13 + vpcmpeqd %ymm11, %ymm11, %ymm11 + vgatherqpd %ymm11, _Log2Rcp_lookup(%rdx,%ymm10), %ymm4 + vpsrlq $40, %ymm14, %ymm10 + vcmpgt_oqpd _Threshold(%rdx), %ymm14, %ymm14 + vpcmpeqd %ymm11, %ymm11, %ymm11 + vandpd _Bias(%rdx), %ymm14, %ymm14 + vcvtdq2pd %xmm5, %ymm15 + vxorpd %ymm5, %ymm5, %ymm5 + vgatherqpd %ymm11, _Log2Rcp_lookup(%rdx,%ymm10), %ymm5 + vorpd _Bias1(%rdx), %ymm12, %ymm11 + vorpd _Bias1(%rdx), %ymm14, %ymm10 + vsubpd %ymm11, %ymm15, %ymm11 + vsubpd %ymm10, %ymm13, %ymm14 + vmovupd _poly_coeff_4(%rdx), %ymm15 + vmovupd _poly_coeff_3(%rdx), %ymm13 + vmulpd %ymm3, %ymm3, %ymm10 + vfmadd213pd %ymm15, %ymm3, %ymm13 + vmovdqa %ymm15, %ymm12 + vfmadd231pd _poly_coeff_3(%rdx), %ymm2, %ymm12 + vmulpd %ymm2, %ymm2, %ymm15 + +/* reconstruction */ + vfmadd213pd %ymm3, %ymm10, %ymm13 + vfmadd213pd %ymm2, %ymm15, %ymm12 + vaddpd %ymm5, %ymm13, %ymm13 + vaddpd %ymm4, %ymm12, %ymm2 + vfmadd231pd _L2(%rdx), %ymm14, %ymm13 + vfmadd132pd _L2(%rdx), %ymm2, %ymm11 + vmulpd %ymm6, %ymm13, %ymm2 + vmulpd %ymm1, %ymm11, %ymm10 + vmulpd __dbInvLn2(%rdx), %ymm2, %ymm6 + vmulpd __dbInvLn2(%rdx), %ymm10, %ymm15 + +/* to round down; if dR is an integer we will get R = 1, which is ok */ + vsubpd __dbHALF(%rdx), %ymm6, %ymm3 + vsubpd __dbHALF(%rdx), %ymm15, %ymm1 + vaddpd __dbShifter(%rdx), %ymm3, %ymm13 + vaddpd __dbShifter(%rdx), %ymm1, %ymm14 + vsubpd __dbShifter(%rdx), %ymm13, %ymm12 + vmovups (%rax), %ymm1 + vsubpd __dbShifter(%rdx), %ymm14, %ymm11 + +/* [0..1) */ + vsubpd %ymm12, %ymm6, %ymm6 + vpermps %ymm10, %ymm1, %ymm3 + vpermps %ymm2, %ymm1, %ymm10 + vpcmpgtd _NMAXVAL(%rdx), %ymm7, %ymm4 + vpcmpgtd _INF(%rdx), %ymm8, %ymm1 + vpcmpeqd _NMAXVAL(%rdx), %ymm7, %ymm7 + vpcmpeqd _INF(%rdx), %ymm8, %ymm8 + vpor %ymm7, %ymm4, %ymm2 + vpor %ymm8, %ymm1, %ymm1 + vsubpd %ymm11, %ymm15, %ymm7 + vinsertf128 $1, %xmm10, %ymm3, %ymm10 + vpor %ymm1, %ymm2, %ymm3 + +/* iAbsX = iAbsX&iAbsMask */ + vandps __iAbsMask(%rdx), %ymm10, %ymm10 + +/* iRangeMask = (iAbsX>iDomainRange) */ + vpcmpgtd __iDomainRange(%rdx), %ymm10, %ymm4 + vpor %ymm4, %ymm3, %ymm5 + vmulpd __dbC1(%rdx), %ymm7, %ymm4 + vmovmskps %ymm5, %ecx + vmulpd __dbC1(%rdx), %ymm6, %ymm5 + +/* low K bits */ + vandps __lbLOWKBITS(%rdx), %ymm14, %ymm6 + +/* dpP= _dbT+lJ*T_ITEM_GRAN */ + vxorpd %ymm7, %ymm7, %ymm7 + vpcmpeqd %ymm1, %ymm1, %ymm1 + vandps __lbLOWKBITS(%rdx), %ymm13, %ymm2 + vxorpd %ymm10, %ymm10, %ymm10 + vpcmpeqd %ymm3, %ymm3, %ymm3 + vgatherqpd %ymm1, 13952(%rdx,%ymm6,8), %ymm7 + vgatherqpd %ymm3, 13952(%rdx,%ymm2,8), %ymm10 + vpsrlq $11, %ymm14, %ymm14 + vpsrlq $11, %ymm13, %ymm13 + vfmadd213pd %ymm7, %ymm4, %ymm7 + vfmadd213pd %ymm10, %ymm5, %ymm10 + +/* NB : including +/- sign for the exponent!! */ + vpsllq $52, %ymm14, %ymm8 + vpsllq $52, %ymm13, %ymm11 + vpaddq %ymm8, %ymm7, %ymm12 + vpaddq %ymm11, %ymm10, %ymm1 + vcvtpd2ps %ymm12, %xmm15 + vcvtpd2ps %ymm1, %xmm2 + vinsertf128 $1, %xmm2, %ymm15, %ymm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups 160(%rsp), %ymm8 + vmovups 96(%rsp), %ymm9 + vmovups 288(%rsp), %ymm10 + vmovups 384(%rsp), %ymm11 + vmovups 256(%rsp), %ymm12 + vmovups 224(%rsp), %ymm13 + vmovups 320(%rsp), %ymm14 + vmovups 352(%rsp), %ymm15 + vmovdqa %ymm1, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm0, 64(%rsp) + vmovups %ymm9, 128(%rsp) + vmovups %ymm1, 192(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movq %rsi, 8(%rsp) + movq %rdi, (%rsp) + movq %r12, 40(%rsp) + cfi_offset_rel_rsp (12, 40) + movb %dl, %r12b + movq %r13, 32(%rsp) + cfi_offset_rel_rsp (13, 32) + movl %ecx, %r13d + movq %r14, 24(%rsp) + cfi_offset_rel_rsp (14, 24) + movl %eax, %r14d + movq %r15, 16(%rsp) + cfi_offset_rel_rsp (15, 16) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movq 8(%rsp), %rsi + movq (%rsp), %rdi + movq 40(%rsp), %r12 + cfi_restore (%r12) + movq 32(%rsp), %r13 + cfi_restore (%r13) + movq 24(%rsp), %r14 + cfi_restore (%r14) + movq 16(%rsp), %r15 + cfi_restore (%r15) + vmovups 192(%rsp), %ymm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 68(%rsp,%r15,8), %xmm0 + vmovss 132(%rsp,%r15,8), %xmm1 + vzeroupper + + call JUMPTARGET(__powf_finite) + + vmovss %xmm0, 196(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 64(%rsp,%r15,8), %xmm0 + vmovss 128(%rsp,%r15,8), %xmm1 + vzeroupper + + call JUMPTARGET(__powf_finite) + + vmovss %xmm0, 192(%rsp,%r15,8) + jmp .LBL_1_7 + +END(_ZGVdN8vv_powf_avx2) + + .section .rodata, "a" +__VPACK_ODD_ind.6357.0.1: + .long 1 + .long 3 + .long 5 + .long 7 + .long 0 + .long 0 + .long 0 + .long 0 + .space 32, 0x00 +__VPACK_ODD_ind.6358.0.1: + .long 1 + .long 3 + .long 5 + .long 7 + .long 0 + .long 0 + .long 0 + .long 0 diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S new file mode 100644 index 0000000000..0545460952 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized sincosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16vvv_sincosf) + .type _ZGVeN16vvv_sincosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16vvv_sincosf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16vvv_sincosf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16vvv_sincosf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16vvv_sincosf) + +#define _ZGVeN16vvv_sincosf _ZGVeN16vvv_sincosf_avx2_wrapper +#include "../svml_s_sincosf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S new file mode 100644 index 0000000000..f73ab7de7c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S @@ -0,0 +1,806 @@ +/* Function sincosf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" +#include "svml_s_wrapper_impl.h" + +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/4; +Pi/4] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer S for destination sign setting. + SS = ((S-S&1)&2)<<30; For sin part + SC = ((S+S&1)&2)<<30; For cos part + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" (0x4B000000) value + h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))); + c) Swap RS & RC if if first bit of obtained value after + Right Shifting is set to 1. Using And, Andnot & Or operations. + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R1 = XOR( RS, SS ); + R2 = XOR( RC, SC ). */ + + .text +ENTRY (_ZGVeN16vl4l4_sincosf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_fFF _ZGVdN8vl4l4_sincosf +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm2 + movl $-1, %edx + vmovups __sAbsMask(%rax), %zmm0 + vmovups __sInvPI(%rax), %zmm3 + +/* Absolute argument computation */ + vpandd %zmm0, %zmm2, %zmm1 + vmovups __sPI1_FMA(%rax), %zmm5 + vmovups __sSignMask(%rax), %zmm9 + vpandnd %zmm2, %zmm0, %zmm0 + +/* h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 3 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 */ + vmovaps %zmm1, %zmm6 + vmovaps %zmm1, %zmm8 + +/* c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value */ + vfmadd213ps __sRShifter(%rax), %zmm1, %zmm3 + vmovups __sPI3_FMA(%rax), %zmm7 + +/* g) Subtract "Right Shifter" (0x4B000000) value */ + vsubps __sRShifter(%rax), %zmm3, %zmm12 + +/* e) Treat obtained value as integer S for destination sign setting */ + vpslld $31, %zmm3, %zmm13 + vmovups __sA7_FMA(%rax), %zmm14 + vfnmadd231ps %zmm12, %zmm5, %zmm6 + +/* 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))) */ + vmovaps %zmm14, %zmm15 + vmovups __sA9_FMA(%rax), %zmm3 + vcmpps $22, __sRangeReductionVal(%rax), %zmm1, %k1 + vpbroadcastd %edx, %zmm1{%k1}{z} + vfnmadd231ps __sPI2_FMA(%rax), %zmm12, %zmm6 + vptestmd %zmm1, %zmm1, %k0 + vpandd %zmm6, %zmm9, %zmm11 + kmovw %k0, %ecx + vpxord __sOneHalf(%rax), %zmm11, %zmm4 + +/* Result sign calculations */ + vpternlogd $150, %zmm13, %zmm9, %zmm11 + +/* Add correction term 0.5 for cos() part */ + vaddps %zmm4, %zmm12, %zmm10 + vfnmadd213ps %zmm6, %zmm7, %zmm12 + vfnmadd231ps %zmm10, %zmm5, %zmm8 + vpxord %zmm13, %zmm12, %zmm13 + vmulps %zmm13, %zmm13, %zmm12 + vfnmadd231ps __sPI2_FMA(%rax), %zmm10, %zmm8 + vfmadd231ps __sA9_FMA(%rax), %zmm12, %zmm15 + vfnmadd213ps %zmm8, %zmm7, %zmm10 + vfmadd213ps __sA5_FMA(%rax), %zmm12, %zmm15 + vpxord %zmm11, %zmm10, %zmm5 + vmulps %zmm5, %zmm5, %zmm4 + vfmadd213ps __sA3(%rax), %zmm12, %zmm15 + vfmadd213ps %zmm14, %zmm4, %zmm3 + vmulps %zmm12, %zmm15, %zmm14 + vfmadd213ps __sA5_FMA(%rax), %zmm4, %zmm3 + vfmadd213ps %zmm13, %zmm13, %zmm14 + vfmadd213ps __sA3(%rax), %zmm4, %zmm3 + vpxord %zmm0, %zmm14, %zmm0 + vmulps %zmm4, %zmm3, %zmm3 + vfmadd213ps %zmm5, %zmm5, %zmm3 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups %zmm0, (%rdi) + vmovups %zmm3, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm2, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + vmovups %zmm3, 1280(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %eax, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %ecx, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + movq %rbx, 1064(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + movq %rbx, %rdi + kmovw 1048(%rsp), %k4 + movq 1056(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + kmovw 1032(%rsp), %k6 + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + movq 1064(%rsp), %rbx + vmovups 1216(%rsp), %zmm0 + vmovups 1280(%rsp), %zmm3 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1220(%rsp,%r15,8) + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 1284(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1216(%rsp,%r15,8) + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 1280(%rsp,%r15,8) + jmp .LBL_1_7 +#endif +END (_ZGVeN16vl4l4_sincosf_knl) +libmvec_hidden_def(_ZGVeN16vl4l4_sincosf_knl) + +ENTRY (_ZGVeN16vl4l4_sincosf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512_fFF _ZGVdN8vvv_sincosf +#else + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1344, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + vmovaps %zmm0, %zmm4 + vmovups __sAbsMask(%rax), %zmm3 + vmovups __sInvPI(%rax), %zmm5 + vmovups __sRShifter(%rax), %zmm6 + vmovups __sPI1_FMA(%rax), %zmm9 + vmovups __sPI2_FMA(%rax), %zmm10 + vmovups __sSignMask(%rax), %zmm14 + vmovups __sOneHalf(%rax), %zmm7 + vmovups __sPI3_FMA(%rax), %zmm12 + +/* Absolute argument computation */ + vandps %zmm3, %zmm4, %zmm2 + +/* c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value */ + vfmadd213ps %zmm6, %zmm2, %zmm5 + vcmpps $18, __sRangeReductionVal(%rax), %zmm2, %k1 + +/* e) Treat obtained value as integer S for destination sign setting */ + vpslld $31, %zmm5, %zmm0 + +/* g) Subtract "Right Shifter" (0x4B000000) value */ + vsubps %zmm6, %zmm5, %zmm5 + vmovups __sA3(%rax), %zmm6 + +/* h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 3 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 */ + vmovaps %zmm2, %zmm11 + vfnmadd231ps %zmm5, %zmm9, %zmm11 + vfnmadd231ps %zmm5, %zmm10, %zmm11 + vandps %zmm11, %zmm14, %zmm1 + vxorps %zmm1, %zmm7, %zmm8 + +/* Result sign calculations */ + vpternlogd $150, %zmm0, %zmm14, %zmm1 + vmovups .L_2il0floatpacket.13(%rip), %zmm14 + +/* Add correction term 0.5 for cos() part */ + vaddps %zmm8, %zmm5, %zmm15 + vfnmadd213ps %zmm11, %zmm12, %zmm5 + vandnps %zmm4, %zmm3, %zmm11 + vmovups __sA7_FMA(%rax), %zmm3 + vmovaps %zmm2, %zmm13 + vfnmadd231ps %zmm15, %zmm9, %zmm13 + vxorps %zmm0, %zmm5, %zmm9 + vmovups __sA5_FMA(%rax), %zmm0 + vfnmadd231ps %zmm15, %zmm10, %zmm13 + vmulps %zmm9, %zmm9, %zmm8 + vfnmadd213ps %zmm13, %zmm12, %zmm15 + vmovups __sA9_FMA(%rax), %zmm12 + vxorps %zmm1, %zmm15, %zmm1 + vmulps %zmm1, %zmm1, %zmm13 + +/* 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))) */ + vmovaps %zmm12, %zmm7 + vfmadd213ps %zmm3, %zmm8, %zmm7 + vfmadd213ps %zmm3, %zmm13, %zmm12 + vfmadd213ps %zmm0, %zmm8, %zmm7 + vfmadd213ps %zmm0, %zmm13, %zmm12 + vfmadd213ps %zmm6, %zmm8, %zmm7 + vfmadd213ps %zmm6, %zmm13, %zmm12 + vmulps %zmm8, %zmm7, %zmm10 + vmulps %zmm13, %zmm12, %zmm3 + vfmadd213ps %zmm9, %zmm9, %zmm10 + vfmadd213ps %zmm1, %zmm1, %zmm3 + vxorps %zmm11, %zmm10, %zmm0 + vpandnd %zmm2, %zmm2, %zmm14{%k1} + vptestmd %zmm14, %zmm14, %k0 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovups %zmm0, (%rdi) + vmovups %zmm3, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm4, 1152(%rsp) + vmovups %zmm0, 1216(%rsp) + vmovups %zmm3, 1280(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %eax, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %ecx, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + movq %rbx, 1064(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_2_6: + btl %r13d, %r14d + jc .LBL_2_13 + +.LBL_2_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + movq %rbx, %rdi + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm0 + vmovups 1280(%rsp), %zmm3 + movq 1056(%rsp), %rsi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + movq 1064(%rsp), %rbx + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1220(%rsp,%r15,8) + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 1284(%rsp,%r15,8) + jmp .LBL_2_8 + +.LBL_2_13: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1216(%rsp,%r15,8) + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 1280(%rsp,%r15,8) + jmp .LBL_2_7 +#endif +END (_ZGVeN16vl4l4_sincosf_skx) +libmvec_hidden_def(_ZGVeN16vl4l4_sincosf_skx) + +/* Wrapper between vvv and vl4l4 vector variants. */ +.macro WRAPPER_AVX512_vvv_vl4l4 callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $384, %rsp + /* Encoding for vmovups %zmm1, 128(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4c + .byte 0x24 + .byte 0x02 + lea (%rsp), %rdi + /* Encoding for vmovups %zmm2, 192(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x57 + .byte 0x03 + /* Encoding for vmovups %zmm3, 256(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x5f + .byte 0x04 + /* Encoding for vmovups %zmm4, 320(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x67 + .byte 0x05 + lea 64(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 128(%rsp), %rdx + movq 136(%rsp), %rsi + movq 144(%rsp), %r8 + movq 152(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 160(%rsp), %rax + movq 168(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 176(%rsp), %rdi + movq 184(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 192(%rsp), %r11 + movq 200(%rsp), %rdx + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 208(%rsp), %rsi + movq 216(%rsp), %r8 + movl 32(%rsp), %r10d + movl 36(%rsp), %eax + movl 40(%rsp), %ecx + movl 44(%rsp), %edi + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 224(%rsp), %r10 + movq 232(%rsp), %rax + movl %ecx, (%rsi) + movl %edi, (%r8) + movq 240(%rsp), %rcx + movq 248(%rsp), %rdi + movl 48(%rsp), %r9d + movl 52(%rsp), %r11d + movl 56(%rsp), %edx + movl 60(%rsp), %esi + movl %r9d, (%r10) + movl %r11d, (%rax) + movq 256(%rsp), %r9 + movq 264(%rsp), %r11 + movl %edx, (%rcx) + movl %esi, (%rdi) + movq 272(%rsp), %rdx + movq 280(%rsp), %rsi + movl 64(%rsp), %r8d + movl 68(%rsp), %r10d + movl 72(%rsp), %eax + movl 76(%rsp), %ecx + movl %r8d, (%r9) + movl %r10d, (%r11) + movq 288(%rsp), %r8 + movq 296(%rsp), %r10 + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 304(%rsp), %rax + movq 312(%rsp), %rcx + movl 80(%rsp), %edi + movl 84(%rsp), %r9d + movl 88(%rsp), %r11d + movl 92(%rsp), %edx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 320(%rsp), %rdi + movq 328(%rsp), %r9 + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 336(%rsp), %r11 + movq 344(%rsp), %rdx + movl 96(%rsp), %esi + movl 100(%rsp), %r8d + movl 104(%rsp), %r10d + movl 108(%rsp), %eax + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 352(%rsp), %rsi + movq 360(%rsp), %r8 + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 368(%rsp), %r10 + movq 376(%rsp), %rax + movl 112(%rsp), %ecx + movl 116(%rsp), %edi + movl 120(%rsp), %r9d + movl 124(%rsp), %r11d + movl %ecx, (%rsi) + movl %edi, (%r8) + movl %r9d, (%r10) + movl %r11d, (%rax) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-64, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x78,0x6 + leal -112(%rbp), %esi + leal -176(%rbp), %edi + subl $296, %esp + /* Encoding for vmovdqa64 %zmm1, -240(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0xfd + .byte 0x48 + .byte 0x7f + .byte 0x8d + .byte 0x10 + .byte 0xff + .byte 0xff + .byte 0xff + /* Encoding for vmovdqa64 %zmm2, -304(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0xfd + .byte 0x48 + .byte 0x7f + .byte 0x95 + .byte 0xd0 + .byte 0xfe + .byte 0xff + .byte 0xff + call HIDDEN_JUMPTARGET(\callee) + movl -240(%ebp), %eax + vmovss -176(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -236(%ebp), %eax + vmovss -172(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -232(%ebp), %eax + vmovss -168(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -228(%ebp), %eax + vmovss -164(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -224(%ebp), %eax + vmovss -160(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -220(%ebp), %eax + vmovss -156(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -216(%ebp), %eax + vmovss -152(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -212(%ebp), %eax + vmovss -148(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -208(%ebp), %eax + vmovss -144(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -204(%ebp), %eax + vmovss -140(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -200(%ebp), %eax + vmovss -136(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -196(%ebp), %eax + vmovss -132(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -192(%ebp), %eax + vmovss -128(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -188(%ebp), %eax + vmovss -124(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -184(%ebp), %eax + vmovss -120(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -180(%ebp), %eax + vmovss -116(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -304(%ebp), %eax + vmovss -112(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -300(%ebp), %eax + vmovss -108(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -296(%ebp), %eax + vmovss -104(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -292(%ebp), %eax + vmovss -100(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -288(%ebp), %eax + vmovss -96(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -284(%ebp), %eax + vmovss -92(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -280(%ebp), %eax + vmovss -88(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -276(%ebp), %eax + vmovss -84(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -272(%ebp), %eax + vmovss -80(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -268(%ebp), %eax + vmovss -76(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -264(%ebp), %eax + vmovss -72(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -260(%ebp), %eax + vmovss -68(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -256(%ebp), %eax + vmovss -64(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -252(%ebp), %eax + vmovss -60(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -248(%ebp), %eax + vmovss -56(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -244(%ebp), %eax + vmovss -52(%ebp), %xmm0 + vmovss %xmm0, (%eax) + addl $296, %esp + popq %r10 + .cfi_def_cfa 10, 0 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVeN16vvv_sincosf_knl) +WRAPPER_AVX512_vvv_vl4l4 _ZGVeN16vl4l4_sincosf_knl +END (_ZGVeN16vvv_sincosf_knl) + +ENTRY (_ZGVeN16vvv_sincosf_skx) +WRAPPER_AVX512_vvv_vl4l4 _ZGVeN16vl4l4_sincosf_skx +END (_ZGVeN16vvv_sincosf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.13: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.13,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S new file mode 100644 index 0000000000..a249be33d1 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sincosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4vvv_sincosf) + .type _ZGVbN4vvv_sincosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4vvv_sincosf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4vvv_sincosf_sse2(%rip), %rax + ret +END (_ZGVbN4vvv_sincosf) +libmvec_hidden_def (_ZGVbN4vvv_sincosf) + +#define _ZGVbN4vvv_sincosf _ZGVbN4vvv_sincosf_sse2 +#include "../svml_s_sincosf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core_sse4.S new file mode 100644 index 0000000000..74a6ac1157 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core_sse4.S @@ -0,0 +1,346 @@ +/* Function sincosf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY (_ZGVbN4vl4l4_sincosf_sse4) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/4; +Pi/4] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer S for destination sign setting. + SS = ((S-S&1)&2)<<30; For sin part + SC = ((S+S&1)&2)<<30; For cos part + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" (0x4B000000) value + h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))); + c) Swap RS & RC if if first bit of obtained value after + Right Shifting is set to 1. Using And, Andnot & Or operations. + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R1 = XOR( RS, SS ); + R2 = XOR( RC, SC ). */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + movups %xmm12, 176(%rsp) + movups %xmm9, 160(%rsp) + movups __sAbsMask(%rax), %xmm12 + +/* Absolute argument computation */ + movaps %xmm12, %xmm5 + andnps %xmm0, %xmm12 + movups __sInvPI(%rax), %xmm7 + andps %xmm0, %xmm5 + +/* c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value. */ + mulps %xmm5, %xmm7 + movups %xmm10, 144(%rsp) + movups __sPI1(%rax), %xmm10 + +/* h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 3 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3. */ + movaps %xmm10, %xmm1 + addps __sRShifter(%rax), %xmm7 + +/* e) Treat obtained value as integer S for destination sign setting */ + movaps %xmm7, %xmm9 + +/* g) Subtract "Right Shifter" (0x4B000000) value */ + subps __sRShifter(%rax), %xmm7 + mulps %xmm7, %xmm1 + pslld $31, %xmm9 + movups __sPI2(%rax), %xmm6 + movups %xmm13, 112(%rsp) + movaps %xmm5, %xmm13 + movaps %xmm6, %xmm2 + subps %xmm1, %xmm13 + mulps %xmm7, %xmm2 + movups __sSignMask(%rax), %xmm3 + movaps %xmm5, %xmm1 + movups __sOneHalf(%rax), %xmm4 + subps %xmm2, %xmm13 + cmpnleps __sRangeReductionVal(%rax), %xmm5 + movaps %xmm3, %xmm2 + andps %xmm13, %xmm2 + xorps %xmm2, %xmm4 + +/* Result sign calculations */ + xorps %xmm2, %xmm3 + xorps %xmm9, %xmm3 + +/* Add correction term 0.5 for cos() part */ + addps %xmm7, %xmm4 + movmskps %xmm5, %ecx + mulps %xmm4, %xmm10 + mulps %xmm4, %xmm6 + subps %xmm10, %xmm1 + movups __sPI3(%rax), %xmm10 + subps %xmm6, %xmm1 + movaps %xmm10, %xmm6 + mulps %xmm7, %xmm6 + mulps %xmm4, %xmm10 + subps %xmm6, %xmm13 + subps %xmm10, %xmm1 + movups __sPI4(%rax), %xmm6 + mulps %xmm6, %xmm7 + mulps %xmm6, %xmm4 + subps %xmm7, %xmm13 + subps %xmm4, %xmm1 + xorps %xmm9, %xmm13 + xorps %xmm3, %xmm1 + movaps %xmm13, %xmm4 + movaps %xmm1, %xmm2 + mulps %xmm13, %xmm4 + mulps %xmm1, %xmm2 + movups __sA9(%rax), %xmm7 + +/* 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))) */ + movaps %xmm7, %xmm3 + mulps %xmm4, %xmm3 + mulps %xmm2, %xmm7 + addps __sA7(%rax), %xmm3 + addps __sA7(%rax), %xmm7 + mulps %xmm4, %xmm3 + mulps %xmm2, %xmm7 + addps __sA5(%rax), %xmm3 + addps __sA5(%rax), %xmm7 + mulps %xmm4, %xmm3 + mulps %xmm2, %xmm7 + addps __sA3(%rax), %xmm3 + addps __sA3(%rax), %xmm7 + mulps %xmm3, %xmm4 + mulps %xmm7, %xmm2 + mulps %xmm13, %xmm4 + mulps %xmm1, %xmm2 + addps %xmm4, %xmm13 + addps %xmm2, %xmm1 + xorps %xmm12, %xmm13 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movups 160(%rsp), %xmm9 + movaps %xmm13, (%rdi) + movups 144(%rsp), %xmm10 + movups 176(%rsp), %xmm12 + movups 112(%rsp), %xmm13 + movups %xmm1, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm0, 128(%rsp) + movups %xmm13, 192(%rsp) + movups %xmm1, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 48(%rsp) + movups %xmm11, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 64(%rsp) + movq %r12, 104(%rsp) + cfi_offset_rel_rsp (12, 104) + movb %dl, %r12b + movq %r13, 96(%rsp) + cfi_offset_rel_rsp (13, 96) + movl %eax, %r13d + movq %r14, 88(%rsp) + cfi_offset_rel_rsp (14, 88) + movl %ecx, %r14d + movq %r15, 80(%rsp) + cfi_offset_rel_rsp (15, 80) + movq %rbx, 72(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 48(%rsp), %xmm8 + movq %rbx, %rdi + movups 32(%rsp), %xmm11 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 64(%rsp), %rsi + movq 104(%rsp), %r12 + cfi_restore (%r12) + movq 96(%rsp), %r13 + cfi_restore (%r13) + movq 88(%rsp), %r14 + cfi_restore (%r14) + movq 80(%rsp), %r15 + cfi_restore (%r15) + movq 72(%rsp), %rbx + movups 192(%rsp), %xmm13 + movups 256(%rsp), %xmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 132(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + movss %xmm0, 196(%rsp,%r15,8) + movss 132(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + movss %xmm0, 260(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + movss 128(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + movss %xmm0, 192(%rsp,%r15,8) + movss 128(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + movss %xmm0, 256(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVbN4vl4l4_sincosf_sse4) +libmvec_hidden_def(_ZGVbN4vl4l4_sincosf_sse4) + +/* vvv version implemented with wrapper to vl4l4 variant. */ +ENTRY (_ZGVbN4vvv_sincosf_sse4) +#ifndef __ILP32__ + subq $104, %rsp + .cfi_def_cfa_offset 112 + movdqu %xmm1, 32(%rsp) + lea (%rsp), %rdi + movdqu %xmm2, 48(%rdi) + lea 16(%rsp), %rsi + movdqu %xmm3, 48(%rsi) + movdqu %xmm4, 64(%rsi) + call HIDDEN_JUMPTARGET(_ZGVbN4vl4l4_sincosf_sse4) + movq 32(%rsp), %rdx + movq 40(%rsp), %rsi + movq 48(%rsp), %r8 + movq 56(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 64(%rsp), %rax + movq 72(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 80(%rsp), %rdi + movq 88(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movl %esi, (%rdi) + movl %r8d, (%r9) + addq $104, %rsp + .cfi_def_cfa_offset 8 + ret +#else + subl $72, %esp + .cfi_def_cfa_offset 80 + leal 48(%rsp), %esi + movaps %xmm1, 16(%esp) + leal 32(%rsp), %edi + movaps %xmm2, (%esp) + call HIDDEN_JUMPTARGET(_ZGVbN4vl4l4_sincosf_sse4) + movl 16(%esp), %eax + movss 32(%esp), %xmm0 + movss %xmm0, (%eax) + movl 20(%esp), %eax + movss 36(%esp), %xmm0 + movss %xmm0, (%eax) + movl 24(%esp), %eax + movss 40(%esp), %xmm0 + movss %xmm0, (%eax) + movl 28(%esp), %eax + movss 44(%esp), %xmm0 + movss %xmm0, (%eax) + movl (%esp), %eax + movss 48(%esp), %xmm0 + movss %xmm0, (%eax) + movl 4(%esp), %eax + movss 52(%esp), %xmm0 + movss %xmm0, (%eax) + movl 8(%esp), %eax + movss 56(%esp), %xmm0 + movss %xmm0, (%eax) + movl 12(%esp), %eax + movss 60(%esp), %xmm0 + movss %xmm0, (%eax) + addl $72, %esp + .cfi_def_cfa_offset 8 + ret +#endif +END (_ZGVbN4vvv_sincosf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S new file mode 100644 index 0000000000..320fd861a5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sincosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8vvv_sincosf) + .type _ZGVdN8vvv_sincosf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8vvv_sincosf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8vvv_sincosf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8vvv_sincosf) +libmvec_hidden_def (_ZGVdN8vvv_sincosf) + +#define _ZGVdN8vvv_sincosf _ZGVdN8vvv_sincosf_sse_wrapper +#include "../svml_s_sincosf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core_avx2.S new file mode 100644 index 0000000000..9e4e2c71c5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core_avx2.S @@ -0,0 +1,389 @@ +/* Function sincosf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY (_ZGVdN8vl4l4_sincosf_avx2) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/4; +Pi/4] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer S for destination sign setting. + SS = ((S-S&1)&2)<<30; For sin part + SC = ((S+S&1)&2)<<30; For cos part + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" (0x4B000000) value + h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))); + c) Swap RS & RC if if first bit of obtained value after + Right Shifting is set to 1. Using And, Andnot & Or operations. + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R1 = XOR( RS, SS ); + R2 = XOR( RC, SC ). */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm5 + vmovups %ymm13, 352(%rsp) + vmovups __sAbsMask(%rax), %ymm2 + vmovups __sInvPI(%rax), %ymm1 + vmovups __sPI1_FMA(%rax), %ymm13 + vmovups %ymm15, 288(%rsp) + +/* Absolute argument computation */ + vandps %ymm2, %ymm5, %ymm4 + +/* c) Getting octant Y by 2/Pi multiplication + d) Add "Right Shifter" value */ + vfmadd213ps __sRShifter(%rax), %ymm4, %ymm1 + +/* e) Treat obtained value as integer S for destination sign setting */ + vpslld $31, %ymm1, %ymm0 + +/* g) Subtract "Right Shifter" (0x4B000000) value */ + vsubps __sRShifter(%rax), %ymm1, %ymm1 + +/* h) Subtract Y*(PI/2) from X argument, where PI/2 divided to 3 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 */ + vmovdqa %ymm4, %ymm7 + vfnmadd231ps %ymm1, %ymm13, %ymm7 + vfnmadd231ps __sPI2_FMA(%rax), %ymm1, %ymm7 + vandps __sSignMask(%rax), %ymm7, %ymm15 + vxorps __sOneHalf(%rax), %ymm15, %ymm6 + +/* Add correction term 0.5 for cos() part */ + vaddps %ymm6, %ymm1, %ymm6 + vmovdqa %ymm4, %ymm3 + vfnmadd231ps %ymm6, %ymm13, %ymm3 + vmovups __sPI3_FMA(%rax), %ymm13 + vcmpnle_uqps __sRangeReductionVal(%rax), %ymm4, %ymm4 + vfnmadd231ps __sPI2_FMA(%rax), %ymm6, %ymm3 + vfnmadd213ps %ymm7, %ymm13, %ymm1 + vfnmadd213ps %ymm3, %ymm13, %ymm6 + +/* Result sign calculations */ + vxorps __sSignMask(%rax), %ymm15, %ymm3 + vxorps %ymm0, %ymm3, %ymm7 + vxorps %ymm7, %ymm6, %ymm3 + vxorps %ymm0, %ymm1, %ymm15 + vandnps %ymm5, %ymm2, %ymm6 + vmovups __sA7_FMA(%rax), %ymm2 + vmulps %ymm15, %ymm15, %ymm13 + vmovups __sA9_FMA(%rax), %ymm7 + vmulps %ymm3, %ymm3, %ymm1 + +/* 2) Polynomial (minimax for sin within [-Pi/4; +Pi/4] interval) + a) Calculate X^2 = X * X + b) Calculate 2 polynomials for sin and cos: + RS = X * ( A0 + X^2 * (A1 + x^2 * (A2 + x^2 * (A3)))); + RC = B0 + X^2 * (B1 + x^2 * (B2 + x^2 * (B3 + x^2 * (B4)))) */ + vmovdqa %ymm2, %ymm0 + vfmadd231ps __sA9_FMA(%rax), %ymm13, %ymm0 + vfmadd213ps %ymm2, %ymm1, %ymm7 + vfmadd213ps __sA5_FMA(%rax), %ymm13, %ymm0 + vfmadd213ps __sA5_FMA(%rax), %ymm1, %ymm7 + vfmadd213ps __sA3(%rax), %ymm13, %ymm0 + vfmadd213ps __sA3(%rax), %ymm1, %ymm7 + vmulps %ymm13, %ymm0, %ymm13 + vmulps %ymm1, %ymm7, %ymm1 + vfmadd213ps %ymm15, %ymm15, %ymm13 + vfmadd213ps %ymm3, %ymm3, %ymm1 + vmovmskps %ymm4, %ecx + vxorps %ymm6, %ymm13, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovups 352(%rsp), %ymm13 + vmovups 288(%rsp), %ymm15 + vmovups %ymm0, (%rdi) + vmovups %ymm1, (%rsi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm5, 256(%rsp) + vmovups %ymm0, 320(%rsp) + vmovups %ymm1, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 160(%rsp) + vmovups %ymm9, 128(%rsp) + vmovups %ymm10, 96(%rsp) + vmovups %ymm11, 64(%rsp) + vmovups %ymm12, 32(%rsp) + vmovups %ymm14, (%rsp) + movq %rsi, 192(%rsp) + movq %r12, 232(%rsp) + cfi_offset_rel_rsp (12, 232) + movb %dl, %r12b + movq %r13, 224(%rsp) + cfi_offset_rel_rsp (13, 224) + movl %eax, %r13d + movq %r14, 216(%rsp) + cfi_offset_rel_rsp (14, 216) + movl %ecx, %r14d + movq %r15, 208(%rsp) + cfi_offset_rel_rsp (14, 208) + movq %rbx, 200(%rsp) + movq %rdi, %rbx + cfi_remember_state + +.LBL_1_6: + btl %r13d, %r14d + jc .LBL_1_13 + +.LBL_1_7: + lea 1(%r13), %esi + btl %esi, %r14d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r13d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 160(%rsp), %ymm8 + movq %rbx, %rdi + vmovups 128(%rsp), %ymm9 + vmovups 96(%rsp), %ymm10 + vmovups 64(%rsp), %ymm11 + vmovups 32(%rsp), %ymm12 + vmovups (%rsp), %ymm14 + vmovups 320(%rsp), %ymm0 + vmovups 384(%rsp), %ymm1 + movq 192(%rsp), %rsi + movq 232(%rsp), %r12 + cfi_restore (%r12) + movq 224(%rsp), %r13 + cfi_restore (%r13) + movq 216(%rsp), %r14 + cfi_restore (%r14) + movq 208(%rsp), %r15 + cfi_restore (%r15) + movq 200(%rsp), %rbx + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 260(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(sinf) + + vmovss %xmm0, 324(%rsp,%r15,8) + vmovss 260(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 388(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_13: + movzbl %r12b, %r15d + vmovss 256(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(sinf) + + vmovss %xmm0, 320(%rsp,%r15,8) + vmovss 256(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(cosf) + + vmovss %xmm0, 384(%rsp,%r15,8) + jmp .LBL_1_7 + +END (_ZGVdN8vl4l4_sincosf_avx2) +libmvec_hidden_def(_ZGVdN8vl4l4_sincosf_avx2) + +/* vvv version implemented with wrapper to vl4l4 variant. */ +ENTRY (_ZGVdN8vvv_sincosf_avx2) +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $192, %rsp + vmovdqu %ymm1, 64(%rsp) + lea (%rsp), %rdi + vmovdqu %ymm2, 96(%rdi) + vmovdqu %ymm3, 128(%rdi) + vmovdqu %ymm4, 160(%rdi) + lea 32(%rsp), %rsi + call HIDDEN_JUMPTARGET(_ZGVdN8vl4l4_sincosf_avx2) + movq 64(%rsp), %rdx + movq 72(%rsp), %rsi + movq 80(%rsp), %r8 + movq 88(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 96(%rsp), %rax + movq 104(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 112(%rsp), %rdi + movq 120(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 128(%rsp), %r11 + movq 136(%rsp), %rdx + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 144(%rsp), %rsi + movq 152(%rsp), %r8 + movl 32(%rsp), %r10d + movl 36(%rsp), %eax + movl 40(%rsp), %ecx + movl 44(%rsp), %edi + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 160(%rsp), %r10 + movq 168(%rsp), %rax + movl %ecx, (%rsi) + movl %edi, (%r8) + movq 176(%rsp), %rcx + movq 184(%rsp), %rdi + movl 48(%rsp), %r9d + movl 52(%rsp), %r11d + movl 56(%rsp), %edx + movl 60(%rsp), %esi + movl %r9d, (%r10) + movl %r11d, (%rax) + movl %edx, (%rcx) + movl %esi, (%rdi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x78,0x6 + leal -48(%rbp), %esi + leal -80(%rbp), %edi + subl $136, %esp + vmovdqa %ymm1, -112(%ebp) + vmovdqa %ymm2, -144(%ebp) + call HIDDEN_JUMPTARGET(_ZGVdN8vl4l4_sincosf_avx2) + vmovdqa -112(%ebp), %xmm0 + vmovq %xmm0, %rax + vmovss -80(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -76(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -104(%ebp), %rax + vmovss -72(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -68(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -96(%ebp), %rax + vmovss -64(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -60(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -88(%ebp), %rax + vmovss -56(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -52(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + vmovdqa -144(%ebp), %xmm0 + vmovq %xmm0, %rax + vmovss -48(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -44(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -136(%ebp), %rax + vmovss -40(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -36(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -128(%ebp), %rax + vmovss -32(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -28(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + movq -120(%ebp), %rax + vmovss -24(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -20(%ebp), %xmm0 + shrq $32, %rax + vmovss %xmm0, (%eax) + addl $136, %esp + popq %r10 + .cfi_def_cfa 10, 0 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +END (_ZGVdN8vvv_sincosf_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S new file mode 100644 index 0000000000..2c18dbce53 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S @@ -0,0 +1,37 @@ +/* Multiple versions of vectorized sinf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVeN16v_sinf) + .type _ZGVeN16v_sinf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_sinf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) + jnz 2f + leaq _ZGVeN16v_sinf_knl(%rip), %rax + HAS_ARCH_FEATURE (AVX512F_Usable) + jnz 2f + leaq _ZGVeN16v_sinf_avx2_wrapper(%rip), %rax +2: ret +END (_ZGVeN16v_sinf) + +#define _ZGVeN16v_sinf _ZGVeN16v_sinf_avx2_wrapper +#include "../svml_s_sinf16_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S new file mode 100644 index 0000000000..8670673a29 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S @@ -0,0 +1,479 @@ +/* Function sinf vectorized with AVX-512. KNL and SKX versions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" +#include "svml_s_wrapper_impl.h" + + .text +ENTRY(_ZGVeN16v_sinf_knl) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_sinf +#else +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" value + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + +/* Check for large and special values */ + movl $-1, %edx + vmovups __sAbsMask(%rax), %zmm4 + vmovups __sInvPI(%rax), %zmm1 + +/* b) Remove sign using AND operation */ + vpandd %zmm4, %zmm0, %zmm12 + vmovups __sPI1_FMA(%rax), %zmm2 + vmovups __sA9(%rax), %zmm7 + +/* + f) Change destination sign if source sign is negative + using XOR operation. + */ + vpandnd %zmm0, %zmm4, %zmm11 + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3; + */ + vmovaps %zmm12, %zmm3 + +/* + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + */ + vfmadd213ps __sRShifter(%rax), %zmm12, %zmm1 + vcmpps $22, __sRangeReductionVal(%rax), %zmm12, %k1 + vpbroadcastd %edx, %zmm13{%k1}{z} + +/* g) Subtract "Right Shifter" value */ + vsubps __sRShifter(%rax), %zmm1, %zmm5 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + */ + vpslld $31, %zmm1, %zmm6 + vptestmd %zmm13, %zmm13, %k0 + vfnmadd231ps %zmm5, %zmm2, %zmm3 + kmovw %k0, %ecx + vfnmadd231ps __sPI2_FMA(%rax), %zmm5, %zmm3 + vfnmadd132ps __sPI3_FMA(%rax), %zmm3, %zmm5 + +/* + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + */ + vmulps %zmm5, %zmm5, %zmm8 + vpxord %zmm6, %zmm5, %zmm9 + vfmadd213ps __sA7(%rax), %zmm8, %zmm7 + vfmadd213ps __sA5(%rax), %zmm8, %zmm7 + vfmadd213ps __sA3(%rax), %zmm8, %zmm7 + vmulps %zmm8, %zmm7, %zmm10 + vfmadd213ps %zmm9, %zmm9, %zmm10 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vpxord %zmm11, %zmm10, %zmm1 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + kmovw %k4, 1048(%rsp) + xorl %eax, %eax + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + addb $1, %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + kmovw 1048(%rsp), %k4 + movq 1064(%rsp), %rsi + kmovw 1040(%rsp), %k5 + movq 1056(%rsp), %rdi + kmovw 1032(%rsp), %k6 + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + vmovups 1216(%rsp), %zmm1 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + call JUMPTARGET(sinf) + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + call JUMPTARGET(sinf) + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_1_7 +#endif +END(_ZGVeN16v_sinf_knl) + +ENTRY (_ZGVeN16v_sinf_skx) +#ifndef HAVE_AVX512DQ_ASM_SUPPORT +WRAPPER_IMPL_AVX512 _ZGVdN8v_sinf +#else +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" value + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $1280, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + +/* Check for large and special values */ + vmovups .L_2il0floatpacket.11(%rip), %zmm14 + vmovups __sAbsMask(%rax), %zmm5 + vmovups __sInvPI(%rax), %zmm1 + vmovups __sRShifter(%rax), %zmm2 + vmovups __sPI1_FMA(%rax), %zmm3 + vmovups __sA9(%rax), %zmm8 + +/* b) Remove sign using AND operation */ + vandps %zmm5, %zmm0, %zmm13 + +/* + f) Change destination sign if source sign is negative + using XOR operation. + */ + vandnps %zmm0, %zmm5, %zmm12 + +/* + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + */ + vfmadd213ps %zmm2, %zmm13, %zmm1 + vcmpps $18, __sRangeReductionVal(%rax), %zmm13, %k1 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + */ + vpslld $31, %zmm1, %zmm7 + +/* g) Subtract "Right Shifter" value */ + vsubps %zmm2, %zmm1, %zmm6 + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3; + */ + vmovaps %zmm13, %zmm4 + vfnmadd231ps %zmm6, %zmm3, %zmm4 + vfnmadd231ps __sPI2_FMA(%rax), %zmm6, %zmm4 + vfnmadd132ps __sPI3_FMA(%rax), %zmm4, %zmm6 + +/* + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + */ + vmulps %zmm6, %zmm6, %zmm9 + vxorps %zmm7, %zmm6, %zmm10 + vfmadd213ps __sA7(%rax), %zmm9, %zmm8 + vfmadd213ps __sA5(%rax), %zmm9, %zmm8 + vfmadd213ps __sA3(%rax), %zmm9, %zmm8 + vmulps %zmm9, %zmm8, %zmm11 + vfmadd213ps %zmm10, %zmm10, %zmm11 + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vxorps %zmm12, %zmm11, %zmm1 + vpandnd %zmm13, %zmm13, %zmm14{%k1} + vptestmd %zmm14, %zmm14, %k0 + kmovw %k0, %ecx + testl %ecx, %ecx + jne .LBL_2_3 + +.LBL_2_2: + cfi_remember_state + vmovaps %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_2_3: + cfi_restore_state + vmovups %zmm0, 1152(%rsp) + vmovups %zmm1, 1216(%rsp) + je .LBL_2_2 + + xorb %dl, %dl + xorl %eax, %eax + kmovw %k4, 1048(%rsp) + kmovw %k5, 1040(%rsp) + kmovw %k6, 1032(%rsp) + kmovw %k7, 1024(%rsp) + vmovups %zmm16, 960(%rsp) + vmovups %zmm17, 896(%rsp) + vmovups %zmm18, 832(%rsp) + vmovups %zmm19, 768(%rsp) + vmovups %zmm20, 704(%rsp) + vmovups %zmm21, 640(%rsp) + vmovups %zmm22, 576(%rsp) + vmovups %zmm23, 512(%rsp) + vmovups %zmm24, 448(%rsp) + vmovups %zmm25, 384(%rsp) + vmovups %zmm26, 320(%rsp) + vmovups %zmm27, 256(%rsp) + vmovups %zmm28, 192(%rsp) + vmovups %zmm29, 128(%rsp) + vmovups %zmm30, 64(%rsp) + vmovups %zmm31, (%rsp) + movq %rsi, 1064(%rsp) + movq %rdi, 1056(%rsp) + movq %r12, 1096(%rsp) + cfi_offset_rel_rsp (12, 1096) + movb %dl, %r12b + movq %r13, 1088(%rsp) + cfi_offset_rel_rsp (13, 1088) + movl %ecx, %r13d + movq %r14, 1080(%rsp) + cfi_offset_rel_rsp (14, 1080) + movl %eax, %r14d + movq %r15, 1072(%rsp) + cfi_offset_rel_rsp (15, 1072) + cfi_remember_state + +.LBL_2_6: + btl %r14d, %r13d + jc .LBL_2_12 + +.LBL_2_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_2_10 + +.LBL_2_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_2_6 + + kmovw 1048(%rsp), %k4 + kmovw 1040(%rsp), %k5 + kmovw 1032(%rsp), %k6 + kmovw 1024(%rsp), %k7 + vmovups 960(%rsp), %zmm16 + vmovups 896(%rsp), %zmm17 + vmovups 832(%rsp), %zmm18 + vmovups 768(%rsp), %zmm19 + vmovups 704(%rsp), %zmm20 + vmovups 640(%rsp), %zmm21 + vmovups 576(%rsp), %zmm22 + vmovups 512(%rsp), %zmm23 + vmovups 448(%rsp), %zmm24 + vmovups 384(%rsp), %zmm25 + vmovups 320(%rsp), %zmm26 + vmovups 256(%rsp), %zmm27 + vmovups 192(%rsp), %zmm28 + vmovups 128(%rsp), %zmm29 + vmovups 64(%rsp), %zmm30 + vmovups (%rsp), %zmm31 + vmovups 1216(%rsp), %zmm1 + movq 1064(%rsp), %rsi + movq 1056(%rsp), %rdi + movq 1096(%rsp), %r12 + cfi_restore (%r12) + movq 1088(%rsp), %r13 + cfi_restore (%r13) + movq 1080(%rsp), %r14 + cfi_restore (%r14) + movq 1072(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_2_2 + +.LBL_2_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 1156(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1156(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1220(%rsp,%r15,8) + jmp .LBL_2_8 + +.LBL_2_12: + movzbl %r12b, %r15d + vmovss 1152(%rsp,%r15,8), %xmm0 + vzeroupper + vmovss 1152(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + vmovss %xmm0, 1216(%rsp,%r15,8) + jmp .LBL_2_7 +#endif +END (_ZGVeN16v_sinf_skx) + + .section .rodata, "a" +.L_2il0floatpacket.11: + .long 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff + .type .L_2il0floatpacket.11,@object diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S new file mode 100644 index 0000000000..3556473899 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sinf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVbN4v_sinf) + .type _ZGVbN4v_sinf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_sinf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) + jz 2f + ret +2: leaq _ZGVbN4v_sinf_sse2(%rip), %rax + ret +END (_ZGVbN4v_sinf) +libmvec_hidden_def (_ZGVbN4v_sinf) + +#define _ZGVbN4v_sinf _ZGVbN4v_sinf_sse2 +#include "../svml_s_sinf4_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core_sse4.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core_sse4.S new file mode 100644 index 0000000000..c690150964 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core_sse4.S @@ -0,0 +1,224 @@ +/* Function sinf vectorized with SSE4. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY(_ZGVbN4v_sinf_sse4) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" value + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + movaps %xmm0, %xmm5 + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + movups __sAbsMask(%rax), %xmm2 + +/* b) Remove sign using AND operation */ + movaps %xmm2, %xmm4 + +/* + f) Change destination sign if source sign is negative + using XOR operation. + */ + andnps %xmm5, %xmm2 + movups __sInvPI(%rax), %xmm1 + andps %xmm5, %xmm4 + +/* c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value */ + mulps %xmm4, %xmm1 + +/* h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4 */ + movaps %xmm4, %xmm0 + +/* Check for large and special values */ + cmpnleps __sRangeReductionVal(%rax), %xmm4 + movups __sRShifter(%rax), %xmm6 + movups __sPI1(%rax), %xmm7 + addps %xmm6, %xmm1 + movmskps %xmm4, %ecx + +/* e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position */ + movaps %xmm1, %xmm3 + +/* g) Subtract "Right Shifter" value */ + subps %xmm6, %xmm1 + mulps %xmm1, %xmm7 + pslld $31, %xmm3 + movups __sPI2(%rax), %xmm6 + subps %xmm7, %xmm0 + mulps %xmm1, %xmm6 + movups __sPI3(%rax), %xmm7 + subps %xmm6, %xmm0 + mulps %xmm1, %xmm7 + movups __sPI4(%rax), %xmm6 + subps %xmm7, %xmm0 + mulps %xmm6, %xmm1 + subps %xmm1, %xmm0 + +/* 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... */ + movaps %xmm0, %xmm1 + mulps %xmm0, %xmm1 + xorps %xmm3, %xmm0 + movups __sA9(%rax), %xmm3 + mulps %xmm1, %xmm3 + addps __sA7(%rax), %xmm3 + mulps %xmm1, %xmm3 + addps __sA5(%rax), %xmm3 + mulps %xmm1, %xmm3 + addps __sA3(%rax), %xmm3 + mulps %xmm3, %xmm1 + mulps %xmm0, %xmm1 + addps %xmm1, %xmm0 + +/* 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); */ + xorps %xmm2, %xmm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + movups %xmm5, 192(%rsp) + movups %xmm0, 256(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + movups %xmm8, 112(%rsp) + movups %xmm9, 96(%rsp) + movups %xmm10, 80(%rsp) + movups %xmm11, 64(%rsp) + movups %xmm12, 48(%rsp) + movups %xmm13, 32(%rsp) + movups %xmm14, 16(%rsp) + movups %xmm15, (%rsp) + movq %rsi, 136(%rsp) + movq %rdi, 128(%rsp) + movq %r12, 168(%rsp) + cfi_offset_rel_rsp (12, 168) + movb %dl, %r12b + movq %r13, 160(%rsp) + cfi_offset_rel_rsp (13, 160) + movl %ecx, %r13d + movq %r14, 152(%rsp) + cfi_offset_rel_rsp (14, 152) + movl %eax, %r14d + movq %r15, 144(%rsp) + cfi_offset_rel_rsp (15, 144) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + movups 112(%rsp), %xmm8 + movups 96(%rsp), %xmm9 + movups 80(%rsp), %xmm10 + movups 64(%rsp), %xmm11 + movups 48(%rsp), %xmm12 + movups 32(%rsp), %xmm13 + movups 16(%rsp), %xmm14 + movups (%rsp), %xmm15 + movq 136(%rsp), %rsi + movq 128(%rsp), %rdi + movq 168(%rsp), %r12 + cfi_restore (%r12) + movq 160(%rsp), %r13 + cfi_restore (%r13) + movq 152(%rsp), %r14 + cfi_restore (%r14) + movq 144(%rsp), %r15 + cfi_restore (%r15) + movups 256(%rsp), %xmm0 + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + movss 196(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + movss %xmm0, 260(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + movss 192(%rsp,%r15,8), %xmm0 + + call JUMPTARGET(sinf) + + movss %xmm0, 256(%rsp,%r15,8) + jmp .LBL_1_7 + +END(_ZGVbN4v_sinf_sse4) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S new file mode 100644 index 0000000000..674e88bd55 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S @@ -0,0 +1,36 @@ +/* Multiple versions of vectorized sinf, vector length is 8. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <init-arch.h> + + .text +ENTRY (_ZGVdN8v_sinf) + .type _ZGVdN8v_sinf, @gnu_indirect_function + LOAD_RTLD_GLOBAL_RO_RDX +1: leaq _ZGVdN8v_sinf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) + jz 2f + ret +2: leaq _ZGVdN8v_sinf_sse_wrapper(%rip), %rax + ret +END (_ZGVdN8v_sinf) +libmvec_hidden_def (_ZGVdN8v_sinf) + +#define _ZGVdN8v_sinf _ZGVdN8v_sinf_sse_wrapper +#include "../svml_s_sinf8_core.S" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core_avx2.S b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core_avx2.S new file mode 100644 index 0000000000..d34870fa3a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core_avx2.S @@ -0,0 +1,219 @@ +/* Function sinf vectorized with AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_trig_data.h" + + .text +ENTRY(_ZGVdN8v_sinf_avx2) +/* + ALGORITHM DESCRIPTION: + + 1) Range reduction to [-Pi/2; +Pi/2] interval + a) Grab sign from source argument and save it. + b) Remove sign using AND operation + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + f) Change destination sign if source sign is negative + using XOR operation. + g) Subtract "Right Shifter" value + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4; + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + movq __svml_s_trig_data@GOTPCREL(%rip), %rax + vmovdqa %ymm0, %ymm5 + vmovups __sAbsMask(%rax), %ymm3 + vmovups __sInvPI(%rax), %ymm7 + vmovups __sRShifter(%rax), %ymm0 + vmovups __sPI1_FMA(%rax), %ymm1 + +/* b) Remove sign using AND operation */ + vandps %ymm3, %ymm5, %ymm4 + +/* + c) Getting octant Y by 1/Pi multiplication + d) Add "Right Shifter" value + */ + vfmadd213ps %ymm0, %ymm4, %ymm7 + +/* g) Subtract "Right Shifter" value */ + vsubps %ymm0, %ymm7, %ymm2 + +/* + e) Treat obtained value as integer for destination sign setting. + Shift first bit of this value to the last (sign) position + */ + vpslld $31, %ymm7, %ymm6 + +/* + h) Subtract Y*PI from X argument, where PI divided to 4 parts: + X = X - Y*PI1 - Y*PI2 - Y*PI3; + */ + vmovdqa %ymm4, %ymm0 + vfnmadd231ps %ymm2, %ymm1, %ymm0 + +/* Check for large and special values */ + vcmpnle_uqps __sRangeReductionVal(%rax), %ymm4, %ymm4 + vfnmadd231ps __sPI2_FMA(%rax), %ymm2, %ymm0 + vfnmadd132ps __sPI3_FMA(%rax), %ymm0, %ymm2 + +/* + 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval) + a) Calculate X^2 = X * X + b) Calculate polynomial: + R = X + X * X^2 * (A3 + x^2 * (A5 + ...... + */ + vmulps %ymm2, %ymm2, %ymm1 + +/* + f) Change destination sign if source sign is negative + using XOR operation. + */ + vandnps %ymm5, %ymm3, %ymm0 + vxorps %ymm6, %ymm2, %ymm3 + vmovups __sA9(%rax), %ymm2 + vfmadd213ps __sA7(%rax), %ymm1, %ymm2 + vfmadd213ps __sA5(%rax), %ymm1, %ymm2 + vfmadd213ps __sA3(%rax), %ymm1, %ymm2 + vmulps %ymm1, %ymm2, %ymm6 + vfmadd213ps %ymm3, %ymm3, %ymm6 + vmovmskps %ymm4, %ecx + +/* + 3) Destination sign setting + a) Set shifted destination sign using XOR operation: + R = XOR( R, S ); + */ + vxorps %ymm0, %ymm6, %ymm0 + testl %ecx, %ecx + jne .LBL_1_3 + +.LBL_1_2: + cfi_remember_state + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret + +.LBL_1_3: + cfi_restore_state + vmovups %ymm5, 320(%rsp) + vmovups %ymm0, 384(%rsp) + je .LBL_1_2 + + xorb %dl, %dl + xorl %eax, %eax + vmovups %ymm8, 224(%rsp) + vmovups %ymm9, 192(%rsp) + vmovups %ymm10, 160(%rsp) + vmovups %ymm11, 128(%rsp) + vmovups %ymm12, 96(%rsp) + vmovups %ymm13, 64(%rsp) + vmovups %ymm14, 32(%rsp) + vmovups %ymm15, (%rsp) + movq %rsi, 264(%rsp) + movq %rdi, 256(%rsp) + movq %r12, 296(%rsp) + cfi_offset_rel_rsp (12, 296) + movb %dl, %r12b + movq %r13, 288(%rsp) + cfi_offset_rel_rsp (13, 288) + movl %ecx, %r13d + movq %r14, 280(%rsp) + cfi_offset_rel_rsp (14, 280) + movl %eax, %r14d + movq %r15, 272(%rsp) + cfi_offset_rel_rsp (15, 272) + cfi_remember_state + +.LBL_1_6: + btl %r14d, %r13d + jc .LBL_1_12 + +.LBL_1_7: + lea 1(%r14), %esi + btl %esi, %r13d + jc .LBL_1_10 + +.LBL_1_8: + incb %r12b + addl $2, %r14d + cmpb $16, %r12b + jb .LBL_1_6 + + vmovups 224(%rsp), %ymm8 + vmovups 192(%rsp), %ymm9 + vmovups 160(%rsp), %ymm10 + vmovups 128(%rsp), %ymm11 + vmovups 96(%rsp), %ymm12 + vmovups 64(%rsp), %ymm13 + vmovups 32(%rsp), %ymm14 + vmovups (%rsp), %ymm15 + vmovups 384(%rsp), %ymm0 + movq 264(%rsp), %rsi + movq 256(%rsp), %rdi + movq 296(%rsp), %r12 + cfi_restore (%r12) + movq 288(%rsp), %r13 + cfi_restore (%r13) + movq 280(%rsp), %r14 + cfi_restore (%r14) + movq 272(%rsp), %r15 + cfi_restore (%r15) + jmp .LBL_1_2 + +.LBL_1_10: + cfi_restore_state + movzbl %r12b, %r15d + vmovss 324(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(sinf) + + vmovss %xmm0, 388(%rsp,%r15,8) + jmp .LBL_1_8 + +.LBL_1_12: + movzbl %r12b, %r15d + vmovss 320(%rsp,%r15,8), %xmm0 + vzeroupper + + call JUMPTARGET(sinf) + + vmovss %xmm0, 384(%rsp,%r15,8) + jmp .LBL_1_7 + +END(_ZGVdN8v_sinf_avx2) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/printf_fphex.c b/REORG.TODO/sysdeps/x86_64/fpu/printf_fphex.c new file mode 100644 index 0000000000..fd68eaeebf --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/printf_fphex.c @@ -0,0 +1,93 @@ +/* Print floating point number in hexadecimal notation according to ISO C99. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef LONG_DOUBLE_DENORM_BIAS +# define LONG_DOUBLE_DENORM_BIAS (IEEE854_LONG_DOUBLE_BIAS - 1) +#endif + +#define PRINT_FPHEX_LONG_DOUBLE \ +do { \ + /* The "strange" 80 bit format on ix86 and m68k has an explicit \ + leading digit in the 64 bit mantissa. */ \ + unsigned long long int num; \ + union ieee854_long_double u; \ + u.d = fpnum.ldbl; \ + \ + num = (((unsigned long long int) u.ieee.mantissa0) << 32 \ + | u.ieee.mantissa1); \ + \ + zero_mantissa = num == 0; \ + \ + if (sizeof (unsigned long int) > 6) \ + { \ + numstr = _itoa_word (num, numbuf + sizeof numbuf, 16, \ + info->spec == 'A'); \ + wnumstr = _itowa_word (num, \ + wnumbuf + sizeof (wnumbuf) / sizeof (wchar_t),\ + 16, info->spec == 'A'); \ + } \ + else \ + { \ + numstr = _itoa (num, numbuf + sizeof numbuf, 16, info->spec == 'A');\ + wnumstr = _itowa (num, \ + wnumbuf + sizeof (wnumbuf) / sizeof (wchar_t), \ + 16, info->spec == 'A'); \ + } \ + \ + /* Fill with zeroes. */ \ + while (numstr > numbuf + (sizeof numbuf - 64 / 4)) \ + { \ + *--numstr = '0'; \ + *--wnumstr = L'0'; \ + } \ + \ + /* We use a full nibble for the leading digit. */ \ + leading = *numstr++; \ + wnumstr++; \ + \ + /* We have 3 bits from the mantissa in the leading nibble. \ + Therefore we are here using `IEEE854_LONG_DOUBLE_BIAS + 3'. */ \ + exponent = u.ieee.exponent; \ + \ + if (exponent == 0) \ + { \ + if (zero_mantissa) \ + expnegative = 0; \ + else \ + { \ + /* This is a denormalized number. */ \ + expnegative = 1; \ + /* This is a hook for the m68k long double format, where the \ + exponent bias is the same for normalized and denormalized \ + numbers. */ \ + exponent = LONG_DOUBLE_DENORM_BIAS + 3; \ + } \ + } \ + else if (exponent >= IEEE854_LONG_DOUBLE_BIAS + 3) \ + { \ + expnegative = 0; \ + exponent -= IEEE854_LONG_DOUBLE_BIAS + 3; \ + } \ + else \ + { \ + expnegative = 1; \ + exponent = -(exponent - (IEEE854_LONG_DOUBLE_BIAS + 3)); \ + } \ +} while (0) + +#include <stdio-common/printf_fphex.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_atanl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_atanl.c new file mode 100644 index 0000000000..fd4a455b55 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_atanl.c @@ -0,0 +1 @@ +#include "sysdeps/i386/fpu/s_atanl.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_ceill.S b/REORG.TODO/sysdeps/x86_64/fpu/s_ceill.S new file mode 100644 index 0000000000..9d8b79dbee --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_ceill.S @@ -0,0 +1,36 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com> + * Changes for x86-64 by Andreas Jaeger <aj@suse.de> + * Public domain. + */ + +#include <machine/asm.h> + + +ENTRY(__ceill) + fldt 8(%rsp) + + fnstenv -28(%rsp) /* store fpu environment */ + + /* We use here %edx although only the low 1 bits are defined. + But none of the operations should care and they are faster + than the 16 bit operations. */ + movl $0x0800,%edx /* round towards +oo */ + orl -28(%rsp),%edx + andl $0xfbff,%edx + movl %edx,-32(%rsp) + fldcw -32(%rsp) /* load modified control word */ + + frndint /* round */ + + /* Preserve "invalid" exceptions from sNaN input. */ + fnstsw + andl $0x1, %eax + orl %eax, -24(%rsp) + + fldenv -28(%rsp) /* restore original environment */ + + ret +END (__ceill) +weak_alias (__ceill, ceill) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_copysign.S b/REORG.TODO/sysdeps/x86_64/fpu/s_copysign.S new file mode 100644 index 0000000000..8939dffd99 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_copysign.S @@ -0,0 +1,50 @@ +/* copy sign, double version. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> + + .section .rodata.cst16,"aM",@progbits,16 + + .align ALIGNARG(4) + .type signmask,@object +signmask: + .byte 0, 0, 0, 0, 0, 0, 0, 0x80 + .byte 0, 0, 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(signmask) + .type othermask,@object +othermask: + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f + .byte 0, 0, 0, 0, 0, 0, 0, 0 + ASM_SIZE_DIRECTIVE(othermask) + +#ifdef PIC +#define MO(op) op##(%rip) +#else +#define MO(op) op +#endif + + .text +ENTRY(__copysign) + andpd MO(othermask),%xmm0 + andpd MO(signmask),%xmm1 + orpd %xmm1,%xmm0 + ret +END (__copysign) + +weak_alias (__copysign, copysign) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_copysignf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_copysignf.S new file mode 100644 index 0000000000..213c2d3c2c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_copysignf.S @@ -0,0 +1,45 @@ +/* copy sign, double version. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> + + .section .rodata + + .align ALIGNARG(4) + .type mask,@object +mask: + .byte 0xff, 0xff, 0xff, 0x7f + ASM_SIZE_DIRECTIVE(mask) + +#ifdef PIC +#define MO(op) op##(%rip) +#else +#define MO(op) op +#endif + + .text +ENTRY(__copysignf) + movss MO(mask),%xmm3 + andps %xmm3,%xmm0 + andnps %xmm1,%xmm3 + orps %xmm3,%xmm0 + retq +END (__copysignf) + +weak_alias (__copysignf, copysignf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_copysignl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_copysignl.S new file mode 100644 index 0000000000..2ffd612d65 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_copysignl.S @@ -0,0 +1,22 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com>. + * Adopted for x86-64 by Andreas Jaeger <aj@suse.de>. + * Public domain. + */ + +#include <machine/asm.h> + +RCSID("$NetBSD: $") + +ENTRY(__copysignl) + movl 32(%rsp),%edx + movl 16(%rsp),%eax + andl $0x8000,%edx + andl $0x7fff,%eax + orl %edx,%eax + movl %eax,16(%rsp) + fldt 8(%rsp) + ret +END (__copysignl) +weak_alias (__copysignl, copysignl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_cosf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_cosf.S new file mode 100644 index 0000000000..e9fdc7e56e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_cosf.S @@ -0,0 +1,533 @@ +/* Optimized cosf function. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#define __need_Emath +#include <bits/errno.h> + +/* Short algorithm description: + * + * 1) if |x| == 0: return 1.0-|x|. + * 2) if |x| < 2^-27: return 1.0-|x|. + * 3) if |x| < 2^-5 : return 1.0+x^2*DP_COS2_0+x^5*DP_COS2_1. + * 4) if |x| < Pi/4: return 1.0+x^2*(C0+x^2*(C1+x^2*(C2+x^2*(C3+x^2*C4)))). + * 5) if |x| < 9*Pi/4: + * 5.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0x0e, n=k+3, + * t=|x|-j*Pi/4. + * 5.2) Reconstruction: + * s = (-1.0)^((n>>2)&1) + * if(n&2 != 0) { + * using cos(t) polynomial for |t|<Pi/4, result is + * s * (1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4))))). + * } else { + * using sin(t) polynomial for |t|<Pi/4, result is + * s * t * (1.0+t^2*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4))))). + * } + * 6) if |x| < 2^23, large args: + * 6.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+3, + * t=|x|-j*Pi/4. + * 6.2) Reconstruction same as (5.2). + * 7) if |x| >= 2^23, very large args: + * 7.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+3, + * t=|x|-j*Pi/4. + * 7.2) Reconstruction same as (5.2). + * 8) if x is Inf, return x-x, and set errno=EDOM. + * 9) if x is NaN, return x-x. + * + * Special cases: + * cos(+-0) = 1 not raising inexact, + * cos(subnormal) raises inexact, + * cos(min_normalized) raises inexact, + * cos(normalized) raises inexact, + * cos(Inf) = NaN, raises invalid, sets errno to EDOM, + * cos(NaN) = NaN. + */ + + .text +ENTRY(__cosf) + /* Input: single precision x in %xmm0 */ + + movd %xmm0, %eax /* Bits of x */ + movaps %xmm0, %xmm7 /* Copy of x */ + cvtss2sd %xmm0, %xmm0 /* DP x */ + movss L(SP_ABS_MASK)(%rip), %xmm3 + andl $0x7fffffff, %eax /* |x| */ + + cmpl $0x3f490fdb, %eax /* |x|<Pi/4? */ + jb L(arg_less_pio4) + + /* Here if |x|>=Pi/4 */ + andps %xmm7, %xmm3 /* SP |x| */ + andpd L(DP_ABS_MASK)(%rip), %xmm0 /* DP |x| */ + movss L(SP_INVPIO4)(%rip), %xmm2 /* SP 1/(Pi/4) */ + + cmpl $0x40e231d6, %eax /* |x|<9*Pi/4? */ + jae L(large_args) + + /* Here if Pi/4<=|x|<9*Pi/4 */ + mulss %xmm3, %xmm2 /* SP |x|/(Pi/4) */ + cvttss2si %xmm2, %eax /* k, number of Pi/4 in x */ + lea L(PIO4J)(%rip), %rsi + addl $1, %eax /* k+1 */ + movl $0x0e, %edx + andl %eax, %edx /* j = (k+1)&0x0e */ + addl $2, %eax /* n */ + subsd (%rsi,%rdx,8), %xmm0 /* t = |x| - j * Pi/4 */ + +L(reconstruction): + /* Input: %eax=n, %xmm0=t */ + testl $2, %eax /* n&2 != 0? */ + jz L(sin_poly) + +/*L(cos_poly):*/ + /* Here if cos(x) calculated using cos(t) polynomial for |t|<Pi/4: + * y = t*t; z = y*y; + * s = sign(x) * (-1.0)^((n>>2)&1) + * result = s * (1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4))))) + */ + shrl $2, %eax /* n>>2 */ + mulsd %xmm0, %xmm0 /* y=t^2 */ + andl $1, %eax /* (n>>2)&1 */ + movaps %xmm0, %xmm1 /* y */ + mulsd %xmm0, %xmm0 /* z=t^4 */ + + movsd L(DP_C4)(%rip), %xmm4 /* C4 */ + mulsd %xmm0, %xmm4 /* z*C4 */ + movsd L(DP_C3)(%rip), %xmm3 /* C3 */ + mulsd %xmm0, %xmm3 /* z*C3 */ + lea L(DP_ONES)(%rip), %rsi + addsd L(DP_C2)(%rip), %xmm4 /* C2+z*C4 */ + mulsd %xmm0, %xmm4 /* z*(C2+z*C4) */ + addsd L(DP_C1)(%rip), %xmm3 /* C1+z*C3 */ + mulsd %xmm0, %xmm3 /* z*(C1+z*C3) */ + addsd L(DP_C0)(%rip), %xmm4 /* C0+z*(C2+z*C4) */ + mulsd %xmm1, %xmm4 /* y*(C0+z*(C2+z*C4)) */ + + addsd %xmm4, %xmm3 /* y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + /* 1.0+y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + addsd L(DP_ONES)(%rip), %xmm3 + + mulsd (%rsi,%rax,8), %xmm3 /* DP result */ + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(sin_poly): + /* Here if cos(x) calculated using sin(t) polynomial for |t|<Pi/4: + * y = t*t; z = y*y; + * s = sign(x) * (-1.0)^((n>>2)&1) + * result = s * t * (1.0+t^2*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4))))) + */ + + movaps %xmm0, %xmm4 /* t */ + shrl $2, %eax /* n>>2 */ + mulsd %xmm0, %xmm0 /* y=t^2 */ + andl $1, %eax /* (n>>2)&1 */ + movaps %xmm0, %xmm1 /* y */ + mulsd %xmm0, %xmm0 /* z=t^4 */ + + movsd L(DP_S4)(%rip), %xmm2 /* S4 */ + mulsd %xmm0, %xmm2 /* z*S4 */ + movsd L(DP_S3)(%rip), %xmm3 /* S3 */ + mulsd %xmm0, %xmm3 /* z*S3 */ + lea L(DP_ONES)(%rip), %rsi + addsd L(DP_S2)(%rip), %xmm2 /* S2+z*S4 */ + mulsd %xmm0, %xmm2 /* z*(S2+z*S4) */ + addsd L(DP_S1)(%rip), %xmm3 /* S1+z*S3 */ + mulsd %xmm0, %xmm3 /* z*(S1+z*S3) */ + addsd L(DP_S0)(%rip), %xmm2 /* S0+z*(S2+z*S4) */ + mulsd %xmm1, %xmm2 /* y*(S0+z*(S2+z*S4)) */ + /* t*s, where s = sign(x) * (-1.0)^((n>>2)&1) */ + mulsd (%rsi,%rax,8), %xmm4 + /* y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm2, %xmm3 + /* t*s*y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + mulsd %xmm4, %xmm3 + /* t*s*(1.0+y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm4, %xmm3 + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(large_args): + /* Here if |x|>=9*Pi/4 */ + cmpl $0x7f800000, %eax /* x is Inf or NaN? */ + jae L(arg_inf_or_nan) + + /* Here if finite |x|>=9*Pi/4 */ + cmpl $0x4b000000, %eax /* |x|<2^23? */ + jae L(very_large_args) + + /* Here if 9*Pi/4<=|x|<2^23 */ + movsd L(DP_INVPIO4)(%rip), %xmm1 /* 1/(Pi/4) */ + mulsd %xmm0, %xmm1 /* |x|/(Pi/4) */ + cvttsd2si %xmm1, %eax /* k=trunc(|x|/(Pi/4)) */ + addl $1, %eax /* k+1 */ + movl %eax, %edx + andl $0xfffffffe, %edx /* j=(k+1)&0xfffffffe */ + cvtsi2sdl %edx, %xmm4 /* DP j */ + movsd L(DP_PIO4HI)(%rip), %xmm2 /* -PIO4HI = high part of -Pi/4 */ + mulsd %xmm4, %xmm2 /* -j*PIO4HI */ + movsd L(DP_PIO4LO)(%rip), %xmm3 /* -PIO4LO = low part of -Pi/4 */ + addsd %xmm2, %xmm0 /* |x| - j*PIO4HI */ + addl $2, %eax /* n */ + mulsd %xmm3, %xmm4 /* j*PIO4LO */ + addsd %xmm4, %xmm0 /* t = |x| - j*PIO4HI - j*PIO4LO */ + jmp L(reconstruction) + + .p2align 4 +L(very_large_args): + /* Here if finite |x|>=2^23 */ + + /* bitpos = (ix>>23) - BIAS_32 + 59; */ + shrl $23, %eax /* eb = biased exponent of x */ + /* bitpos = eb - 0x7f + 59, where 0x7f is exponent bias */ + subl $68, %eax + movl $28, %ecx /* %cl=28 */ + movl %eax, %edx /* bitpos copy */ + + /* j = bitpos/28; */ + div %cl /* j in register %al=%ax/%cl */ + movapd %xmm0, %xmm3 /* |x| */ + /* clear unneeded remainder from %ah */ + andl $0xff, %eax + + imull $28, %eax, %ecx /* j*28 */ + lea L(_FPI)(%rip), %rsi + movsd L(DP_HI_MASK)(%rip), %xmm4 /* DP_HI_MASK */ + movapd %xmm0, %xmm5 /* |x| */ + mulsd -16(%rsi,%rax,8), %xmm3 /* tmp3 = FPI[j-2]*|x| */ + movapd %xmm0, %xmm1 /* |x| */ + mulsd -8(%rsi,%rax,8), %xmm5 /* tmp2 = FPI[j-1]*|x| */ + mulsd (%rsi,%rax,8), %xmm0 /* tmp0 = FPI[j]*|x| */ + addl $19, %ecx /* j*28+19 */ + mulsd 8(%rsi,%rax,8), %xmm1 /* tmp1 = FPI[j+1]*|x| */ + cmpl %ecx, %edx /* bitpos>=j*28+19? */ + jl L(very_large_skip1) + + /* Here if bitpos>=j*28+19 */ + andpd %xmm3, %xmm4 /* HI(tmp3) */ + subsd %xmm4, %xmm3 /* tmp3 = tmp3 - HI(tmp3) */ +L(very_large_skip1): + + movsd L(DP_2POW52)(%rip), %xmm6 + movapd %xmm5, %xmm2 /* tmp2 copy */ + addsd %xmm3, %xmm5 /* tmp5 = tmp3 + tmp2 */ + movl $1, %edx + addsd %xmm5, %xmm6 /* tmp6 = tmp5 + 2^52 */ + movsd 8+L(DP_2POW52)(%rip), %xmm4 + movd %xmm6, %eax /* k = I64_LO(tmp6); */ + addsd %xmm6, %xmm4 /* tmp4 = tmp6 - 2^52 */ + comisd %xmm5, %xmm4 /* tmp4 > tmp5? */ + jbe L(very_large_skip2) + + /* Here if tmp4 > tmp5 */ + subl $1, %eax /* k-- */ + addsd 8+L(DP_ONES)(%rip), %xmm4 /* tmp4 -= 1.0 */ +L(very_large_skip2): + + andl %eax, %edx /* k&1 */ + lea L(DP_ZERONE)(%rip), %rsi + subsd %xmm4, %xmm3 /* tmp3 -= tmp4 */ + addsd (%rsi,%rdx,8), %xmm3 /* t = DP_ZERONE[k&1] + tmp3 */ + addsd %xmm2, %xmm3 /* t += tmp2 */ + addsd %xmm3, %xmm0 /* t += tmp0 */ + addl $3, %eax /* n=k+3 */ + addsd %xmm1, %xmm0 /* t += tmp1 */ + mulsd L(DP_PIO4)(%rip), %xmm0 /* t *= PI04 */ + + jmp L(reconstruction) /* end of very_large_args peth */ + + .p2align 4 +L(arg_less_pio4): + /* Here if |x|<Pi/4 */ + cmpl $0x3d000000, %eax /* |x|<2^-5? */ + jl L(arg_less_2pn5) + + /* Here if 2^-5<=|x|<Pi/4 */ + mulsd %xmm0, %xmm0 /* y=x^2 */ + movaps %xmm0, %xmm1 /* y */ + mulsd %xmm0, %xmm0 /* z=x^4 */ + movsd L(DP_C4)(%rip), %xmm3 /* C4 */ + mulsd %xmm0, %xmm3 /* z*C4 */ + movsd L(DP_C3)(%rip), %xmm5 /* C3 */ + mulsd %xmm0, %xmm5 /* z*C3 */ + addsd L(DP_C2)(%rip), %xmm3 /* C2+z*C4 */ + mulsd %xmm0, %xmm3 /* z*(C2+z*C4) */ + addsd L(DP_C1)(%rip), %xmm5 /* C1+z*C3 */ + mulsd %xmm0, %xmm5 /* z*(C1+z*C3) */ + addsd L(DP_C0)(%rip), %xmm3 /* C0+z*(C2+z*C4) */ + mulsd %xmm1, %xmm3 /* y*(C0+z*(C2+z*C4)) */ + /* y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + addsd %xmm5, %xmm3 + /* 1.0 + y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + addsd L(DP_ONES)(%rip), %xmm3 + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(arg_less_2pn5): + /* Here if |x|<2^-5 */ + cmpl $0x32000000, %eax /* |x|<2^-27? */ + jl L(arg_less_2pn27) + + /* Here if 2^-27<=|x|<2^-5 */ + mulsd %xmm0, %xmm0 /* DP x^2 */ + movsd L(DP_COS2_1)(%rip), %xmm3 /* DP DP_COS2_1 */ + mulsd %xmm0, %xmm3 /* DP x^2*DP_COS2_1 */ + addsd L(DP_COS2_0)(%rip), %xmm3 /* DP DP_COS2_0+x^2*DP_COS2_1 */ + mulsd %xmm0, %xmm3 /* DP x^2*DP_COS2_0+x^4*DP_COS2_1 */ + /* DP 1.0+x^2*DP_COS2_0+x^4*DP_COS2_1 */ + addsd L(DP_ONES)(%rip), %xmm3 + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(arg_less_2pn27): + /* Here if |x|<2^-27 */ + andps L(SP_ABS_MASK)(%rip),%xmm7 /* |x| */ + movss L(SP_ONE)(%rip), %xmm0 /* 1.0 */ + subss %xmm7, %xmm0 /* result is 1.0-|x| */ + ret + + .p2align 4 +L(arg_inf_or_nan): + /* Here if |x| is Inf or NAN */ + jne L(skip_errno_setting) /* in case of x is NaN */ + + /* Align stack to 16 bytes. */ + subq $8, %rsp + cfi_adjust_cfa_offset (8) + /* Here if x is Inf. Set errno to EDOM. */ + call JUMPTARGET(__errno_location) + addq $8, %rsp + cfi_adjust_cfa_offset (-8) + + movl $EDOM, (%rax) + + .p2align 4 +L(skip_errno_setting): + /* Here if |x| is Inf or NAN. Continued. */ + movaps %xmm7, %xmm0 /* load x */ + subss %xmm0, %xmm0 /* Result is NaN */ + ret +END(__cosf) + + .section .rodata, "a" + .p2align 3 +L(PIO4J): /* Table of j*Pi/4, for j=0,1,..,10 */ + .long 0x00000000,0x00000000 + .long 0x54442d18,0x3fe921fb + .long 0x54442d18,0x3ff921fb + .long 0x7f3321d2,0x4002d97c + .long 0x54442d18,0x400921fb + .long 0x2955385e,0x400f6a7a + .long 0x7f3321d2,0x4012d97c + .long 0xe9bba775,0x4015fdbb + .long 0x54442d18,0x401921fb + .long 0xbeccb2bb,0x401c463a + .long 0x2955385e,0x401f6a7a + .type L(PIO4J), @object + ASM_SIZE_DIRECTIVE(L(PIO4J)) + + .p2align 3 +L(_FPI): /* 4/Pi broken into sum of positive DP values */ + .long 0x00000000,0x00000000 + .long 0x6c000000,0x3ff45f30 + .long 0x2a000000,0x3e3c9c88 + .long 0xa8000000,0x3c54fe13 + .long 0xd0000000,0x3aaf47d4 + .long 0x6c000000,0x38fbb81b + .long 0xe0000000,0x3714acc9 + .long 0x7c000000,0x3560e410 + .long 0x56000000,0x33bca2c7 + .long 0xac000000,0x31fbd778 + .long 0xe0000000,0x300b7246 + .long 0xe8000000,0x2e5d2126 + .long 0x48000000,0x2c970032 + .long 0xe8000000,0x2ad77504 + .long 0xe0000000,0x290921cf + .long 0xb0000000,0x274deb1c + .long 0xe0000000,0x25829a73 + .long 0xbe000000,0x23fd1046 + .long 0x10000000,0x2224baed + .long 0x8e000000,0x20709d33 + .long 0x80000000,0x1e535a2f + .long 0x64000000,0x1cef904e + .long 0x30000000,0x1b0d6398 + .long 0x24000000,0x1964ce7d + .long 0x16000000,0x17b908bf + .type L(_FPI), @object + ASM_SIZE_DIRECTIVE(L(_FPI)) + +/* Coefficients of polynomial + for cos(x)~=1.0+x^2*DP_COS2_0+x^4*DP_COS2_1, |x|<2^-5. */ + .p2align 3 +L(DP_COS2_0): + .long 0xff5cc6fd,0xbfdfffff + .type L(DP_COS2_0), @object + ASM_SIZE_DIRECTIVE(L(DP_COS2_0)) + + .p2align 3 +L(DP_COS2_1): + .long 0xb178dac5,0x3fa55514 + .type L(DP_COS2_1), @object + ASM_SIZE_DIRECTIVE(L(DP_COS2_1)) + + .p2align 3 +L(DP_ZERONE): + .long 0x00000000,0x00000000 /* 0.0 */ + .long 0x00000000,0xbff00000 /* 1.0 */ + .type L(DP_ZERONE), @object + ASM_SIZE_DIRECTIVE(L(DP_ZERONE)) + + .p2align 3 +L(DP_ONES): + .long 0x00000000,0x3ff00000 /* +1.0 */ + .long 0x00000000,0xbff00000 /* -1.0 */ + .type L(DP_ONES), @object + ASM_SIZE_DIRECTIVE(L(DP_ONES)) + +/* Coefficients of polynomial + for sin(t)~=t+t^3*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4)))), |t|<Pi/4. */ + .p2align 3 +L(DP_S3): + .long 0x64e6b5b4,0x3ec71d72 + .type L(DP_S3), @object + ASM_SIZE_DIRECTIVE(L(DP_S3)) + + .p2align 3 +L(DP_S1): + .long 0x10c2688b,0x3f811111 + .type L(DP_S1), @object + ASM_SIZE_DIRECTIVE(L(DP_S1)) + + .p2align 3 +L(DP_S4): + .long 0x1674b58a,0xbe5a947e + .type L(DP_S4), @object + ASM_SIZE_DIRECTIVE(L(DP_S4)) + + .p2align 3 +L(DP_S2): + .long 0x8b4bd1f9,0xbf2a019f + .type L(DP_S2),@object + ASM_SIZE_DIRECTIVE(L(DP_S2)) + + .p2align 3 +L(DP_S0): + .long 0x55551cd9,0xbfc55555 + .type L(DP_S0), @object + ASM_SIZE_DIRECTIVE(L(DP_S0)) + +/* Coefficients of polynomial + for cos(t)~=1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4)))), |t|<Pi/4. */ + .p2align 3 +L(DP_C3): + .long 0x9ac43cc0,0x3efa00eb + .type L(DP_C3), @object + ASM_SIZE_DIRECTIVE(L(DP_C3)) + + .p2align 3 +L(DP_C1): + .long 0x545c50c7,0x3fa55555 + .type L(DP_C1), @object + ASM_SIZE_DIRECTIVE(L(DP_C1)) + + .p2align 3 +L(DP_C4): + .long 0xdd8844d7,0xbe923c97 + .type L(DP_C4), @object + ASM_SIZE_DIRECTIVE(L(DP_C4)) + + .p2align 3 +L(DP_C2): + .long 0x348b6874,0xbf56c16b + .type L(DP_C2), @object + ASM_SIZE_DIRECTIVE(L(DP_C2)) + + .p2align 3 +L(DP_C0): + .long 0xfffe98ae,0xbfdfffff + .type L(DP_C0), @object + ASM_SIZE_DIRECTIVE(L(DP_C0)) + + .p2align 3 +L(DP_PIO4): + .long 0x54442d18,0x3fe921fb /* Pi/4 */ + .type L(DP_PIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4)) + + .p2align 3 +L(DP_2POW52): + .long 0x00000000,0x43300000 /* +2^52 */ + .long 0x00000000,0xc3300000 /* -2^52 */ + .type L(DP_2POW52), @object + ASM_SIZE_DIRECTIVE(L(DP_2POW52)) + + .p2align 3 +L(DP_INVPIO4): + .long 0x6dc9c883,0x3ff45f30 /* 4/Pi */ + .type L(DP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_INVPIO4)) + + .p2align 3 +L(DP_PIO4HI): + .long 0x54000000,0xbfe921fb /* High part of Pi/4 */ + .type L(DP_PIO4HI), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4HI)) + + .p2align 3 +L(DP_PIO4LO): + .long 0x11A62633,0xbe010b46 /* Low part of Pi/4 */ + .type L(DP_PIO4LO), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4LO)) + + .p2align 2 +L(SP_INVPIO4): + .long 0x3fa2f983 /* 4/Pi */ + .type L(SP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(SP_INVPIO4)) + + .p2align 4 +L(DP_ABS_MASK): /* Mask for getting DP absolute value */ + .long 0xffffffff,0x7fffffff + .long 0xffffffff,0x7fffffff + .type L(DP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(DP_ABS_MASK)) + + .p2align 3 +L(DP_HI_MASK): /* Mask for getting high 21 bits of DP value */ + .long 0x00000000,0xffffffff + .type L(DP_HI_MASK), @object + ASM_SIZE_DIRECTIVE(L(DP_HI_MASK)) + + .p2align 4 +L(SP_ABS_MASK): /* Mask for getting SP absolute value */ + .long 0x7fffffff,0x7fffffff + .long 0x7fffffff,0x7fffffff + .type L(SP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(SP_ABS_MASK)) + + .p2align 2 +L(SP_ONE): + .long 0x3f800000 /* 1.0 */ + .type L(SP_ONE), @object + ASM_SIZE_DIRECTIVE(L(SP_ONE)) + +weak_alias(__cosf, cosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_expm1l.S b/REORG.TODO/sysdeps/x86_64/fpu/s_expm1l.S new file mode 100644 index 0000000000..7fbd99b0db --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_expm1l.S @@ -0,0 +1,2 @@ +#define USE_AS_EXPM1L +#include <e_expl.S> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fabs.c b/REORG.TODO/sysdeps/x86_64/fpu/s_fabs.c new file mode 100644 index 0000000000..f5d3ee87e9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fabs.c @@ -0,0 +1,26 @@ +/* Absolute value of floating point number. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +double +__fabs (double x) +{ + return __builtin_fabs (x); +} +weak_alias (__fabs, fabs) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fabsf.c b/REORG.TODO/sysdeps/x86_64/fpu/s_fabsf.c new file mode 100644 index 0000000000..9956cce757 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fabsf.c @@ -0,0 +1,26 @@ +/* Absolute value of floating point number. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +float +__fabsf (float x) +{ + return __builtin_fabsf (x); +} +weak_alias (__fabsf, fabsf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fabsl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fabsl.S new file mode 100644 index 0000000000..1aef8318d9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fabsl.S @@ -0,0 +1,27 @@ +/* Absolute value of floating point number. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fabsl) + fldt 8(%rsp) + fabs + ret +END(__fabsl) +weak_alias (__fabsl, fabsl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_finitel.S b/REORG.TODO/sysdeps/x86_64/fpu/s_finitel.S new file mode 100644 index 0000000000..9e49796901 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_finitel.S @@ -0,0 +1,16 @@ +/* + * Written by Joe Keane <jgk@jgk.org>. + * Adopted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + +ENTRY(__finitel) + movl 16(%rsp),%eax + orl $0xffff8000, %eax + incl %eax + shrl $31, %eax + ret +END (__finitel) +weak_alias (__finitel, finitel) +hidden_def (__finitel) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_floorl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_floorl.S new file mode 100644 index 0000000000..535fdd8571 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_floorl.S @@ -0,0 +1,35 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com> + * Changes for x86-64 by Andreas Jaeger <aj@suse.de>=09 + * Public domain. + */ + +#include <machine/asm.h> + +ENTRY(__floorl) + fldt 8(%rsp) + + fnstenv -28(%rsp) /* store fpu environment */ + + /* We use here %edx although only the low 1 bits are defined. + But none of the operations should care and they are faster + than the 16 bit operations. */ + movl $0x400,%edx /* round towards -oo */ + orl -28(%rsp),%edx + andl $0xf7ff,%edx + movl %edx,-32(%rsp) + fldcw -32(%rsp) /* load modified control word */ + + frndint /* round */ + + /* Preserve "invalid" exceptions from sNaN input. */ + fnstsw + andl $0x1, %eax + orl %eax, -24(%rsp) + + fldenv -28(%rsp) /* restore original environment */ + + ret +END (__floorl) +weak_alias (__floorl, floorl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fmax.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fmax.S new file mode 100644 index 0000000000..f93c9f9371 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fmax.S @@ -0,0 +1,52 @@ +/* Compute maximum of two numbers, regarding NaN as missing argument. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fmax) + ucomisd %xmm0, %xmm1 + jp 1f // jump if unordered + maxsd %xmm1, %xmm0 + jmp 2f + +1: ucomisd %xmm1, %xmm1 // Is xmm1 a NaN? + jp 3f + // xmm0 is a NaN; xmm1 is not. Test if xmm0 is signaling. + movsd %xmm0, -8(%rsp) + testb $0x8, -2(%rsp) + jz 4f + movsd %xmm1, %xmm0 // otherwise return xmm1 + ret + +3: // xmm1 is a NaN; xmm0 may or may not be. + ucomisd %xmm0, %xmm0 + jp 4f + // xmm1 is a NaN; xmm0 is not. Test if xmm1 is signaling. + movsd %xmm1, -8(%rsp) + testb $0x8, -2(%rsp) + jz 4f + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + addsd %xmm1, %xmm0 + +2: ret +END(__fmax) +weak_alias (__fmax, fmax) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxf.S new file mode 100644 index 0000000000..82989feb4b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxf.S @@ -0,0 +1,52 @@ +/* Compute maximum of two numbers, regarding NaN as missing argument. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fmaxf) + ucomiss %xmm0, %xmm1 + jp 1f // jump if unordered + maxss %xmm1, %xmm0 + jmp 2f + +1: ucomiss %xmm1, %xmm1 // Is xmm1 a NaN? + jp 3f + // xmm0 is a NaN; xmm1 is not. Test if xmm0 is signaling. + movss %xmm0, -4(%rsp) + testb $0x40, -2(%rsp) + jz 4f + movss %xmm1, %xmm0 // otherwise return xmm1 + ret + +3: // xmm1 is a NaN; xmm0 may or may not be. + ucomiss %xmm0, %xmm0 + jp 4f + // xmm1 is a NaN; xmm0 is not. Test if xmm1 is signaling. + movss %xmm1, -4(%rsp) + testb $0x40, -2(%rsp) + jz 4f + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + addss %xmm1, %xmm0 + +2: ret +END(__fmaxf) +weak_alias (__fmaxf, fmaxf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxl.S new file mode 100644 index 0000000000..2d3321fce4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fmaxl.S @@ -0,0 +1,58 @@ +/* Compute maximum of two numbers, regarding NaN as missing argument. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fmaxl) + fldt 8(%rsp) // x + fldt 24(%rsp) // x : y + + fucomi %st(1), %st + jp 2f + fcmovb %st(1), %st + + fstp %st(1) + + ret + +2: // Unordered. + fucomi %st(0), %st + jp 3f + // st(1) is a NaN; st(0) is not. Test if st(1) is signaling. + testb $0x40, 15(%rsp) + jz 4f + fstp %st(1) + ret + +3: // st(0) is a NaN; st(1) may or may not be. + fxch + fucomi %st(0), %st + jp 4f + // st(1) is a NaN; st(0) is not. Test if st(1) is signaling. + testb $0x40, 31(%rsp) + jz 4f + fstp %st(1) + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + faddp + ret +END(__fmaxl) +weak_alias (__fmaxl, fmaxl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fmin.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fmin.S new file mode 100644 index 0000000000..718bf489df --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fmin.S @@ -0,0 +1,52 @@ +/* Compute minimum of two numbers, regarding NaN as missing argument. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fmin) + ucomisd %xmm0, %xmm1 + jp 1f // jump if unordered + minsd %xmm1, %xmm0 + jmp 2f + +1: ucomisd %xmm1, %xmm1 // Is xmm1 a NaN? + jp 3f + // xmm0 is a NaN; xmm1 is not. Test if xmm0 is signaling. + movsd %xmm0, -8(%rsp) + testb $0x8, -2(%rsp) + jz 4f + movsd %xmm1, %xmm0 // otherwise return xmm1 + ret + +3: // xmm1 is a NaN; xmm0 may or may not be. + ucomisd %xmm0, %xmm0 + jp 4f + // xmm1 is a NaN; xmm0 is not. Test if xmm1 is signaling. + movsd %xmm1, -8(%rsp) + testb $0x8, -2(%rsp) + jz 4f + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + addsd %xmm1, %xmm0 + +2: ret +END(__fmin) +weak_alias (__fmin, fmin) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fminf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fminf.S new file mode 100644 index 0000000000..8e8c9360ac --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fminf.S @@ -0,0 +1,52 @@ +/* Compute minimum of two numbers, regarding NaN as missing argument. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.de>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fminf) + ucomiss %xmm0, %xmm1 + jp 1f // jump if unordered + minss %xmm1, %xmm0 + jmp 2f + +1: ucomiss %xmm1, %xmm1 // Is xmm1 a NaN? + jp 3f + // xmm0 is a NaN; xmm1 is not. Test if xmm0 is signaling. + movss %xmm0, -4(%rsp) + testb $0x40, -2(%rsp) + jz 4f + movss %xmm1, %xmm0 // otherwise return xmm1 + ret + +3: // xmm1 is a NaN; xmm0 may or may not be. + ucomiss %xmm0, %xmm0 + jp 4f + // xmm1 is a NaN; xmm0 is not. Test if xmm1 is signaling. + movss %xmm1, -4(%rsp) + testb $0x40, -2(%rsp) + jz 4f + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + addss %xmm1, %xmm0 + +2: ret +END(__fminf) +weak_alias (__fminf, fminf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fminl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_fminl.S new file mode 100644 index 0000000000..33eed7b30b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fminl.S @@ -0,0 +1,58 @@ +/* Compute minimum of two numbers, regarding NaN as missing argument. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__fminl) + fldt 8(%rsp) // x + fldt 24(%rsp) // x : y + + fucomi %st(1), %st + jp 2f + fcmovnb %st(1), %st + + fstp %st(1) + + ret + +2: // Unordered. + fucomi %st(0), %st + jp 3f + // st(1) is a NaN; st(0) is not. Test if st(1) is signaling. + testb $0x40, 15(%rsp) + jz 4f + fstp %st(1) + ret + +3: // st(0) is a NaN; st(1) may or may not be. + fxch + fucomi %st(0), %st + jp 4f + // st(1) is a NaN; st(0) is not. Test if st(1) is signaling. + testb $0x40, 31(%rsp) + jz 4f + fstp %st(1) + ret + +4: // Both arguments are NaNs, or one is a signaling NaN. + faddp + ret +END(__fminl) +weak_alias (__fminl, fminl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_fpclassifyl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_fpclassifyl.c new file mode 100644 index 0000000000..856854b0f5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_fpclassifyl.c @@ -0,0 +1,2 @@ +#include <sysdeps/i386/fpu/s_fpclassifyl.c> + diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_isinfl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_isinfl.c new file mode 100644 index 0000000000..ca818b5e90 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_isinfl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_isinfl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_isnanl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_isnanl.c new file mode 100644 index 0000000000..06e69c3aeb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_isnanl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_isnanl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_llrint.S b/REORG.TODO/sysdeps/x86_64/fpu/s_llrint.S new file mode 100644 index 0000000000..af7bbce585 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_llrint.S @@ -0,0 +1,32 @@ +/* Round argument to nearest integral value according to current rounding + direction. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.d>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__llrint) + cvtsd2si %xmm0,%rax + ret +END(__llrint) +weak_alias (__llrint, llrint) +#ifndef __ILP32__ +strong_alias (__llrint, __lrint) +weak_alias (__llrint, lrint) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_llrintf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_llrintf.S new file mode 100644 index 0000000000..9edb78bf1d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_llrintf.S @@ -0,0 +1,32 @@ +/* Round argument to nearest integral value according to current rounding + direction. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Andreas Jaeger <aj@suse.d>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__llrintf) + cvtss2si %xmm0,%rax + ret +END(__llrintf) +weak_alias (__llrintf, llrintf) +#ifndef __ILP32__ +strong_alias (__llrintf, __lrintf) +weak_alias (__llrintf, lrintf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_llrintl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_llrintl.S new file mode 100644 index 0000000000..e5bbf0106e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_llrintl.S @@ -0,0 +1,34 @@ +/* Round argument to nearest integral value according to current rounding + direction. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(__llrintl) + fldt 8(%rsp) + fistpll -8(%rsp) + fwait + movq -8(%rsp),%rax + ret +END(__llrintl) +weak_alias (__llrintl, llrintl) +#ifndef __ILP32__ +strong_alias (__llrintl, __lrintl) +weak_alias (__llrintl, lrintl) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_log1pl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_log1pl.S new file mode 100644 index 0000000000..947e5e4552 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_log1pl.S @@ -0,0 +1,74 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + * + * Adapted for `long double' by Ulrich Drepper <drepper@cygnus.com>. + * Adapted for x86-64 by Andreas Jaeger <aj@suse.de>. + */ + +#include <machine/asm.h> + +RCSID("$NetBSD: s_log1p.S,v 1.7 1995/05/09 00:10:58 jtc Exp $") + + .section .rodata + + .align ALIGNARG(4) + /* The fyl2xp1 can only be used for values in + -1 + sqrt(2) / 2 <= x <= 1 - sqrt(2) / 2 + 0.29 is a safe value. + */ +limit: .tfloat 0.29 + /* Please note: we use a double value here. Since 1.0 has + an exact representation this does not effect the accuracy + but it helps to optimize the code. */ +one: .double 1.0 + +/* + * Use the fyl2xp1 function when the argument is in the range -0.29 to 0.29, + * otherwise fyl2x with the needed extra computation. + */ +#ifdef PIC +#define MO(op) op##(%rip) +#else +#define MO(op) op +#endif + + .text +ENTRY(__log1pl) + fldln2 + + fldt 8(%rsp) + + fxam + fnstsw + fld %st + testb $1, %ah + jnz 3f // in case x is NaN or ±Inf +4: + fabs + fldt MO(limit) + fcompp + fnstsw + andb $1,%ah + jz 2f + + movzwl 8+8(%rsp), %eax + xorb $0x80, %ah + cmpl $0xc040, %eax + jae 5f + + faddl MO(one) +5: fyl2x + ret + +2: fyl2xp1 + ret + +3: testb $4, %ah + jnz 4b // in case x is ±Inf + fstp %st(1) + fstp %st(1) + fadd %st(0) + ret + +END (__log1pl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_logbl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_logbl.c new file mode 100644 index 0000000000..4791ba64e8 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_logbl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_logbl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_lrint.S b/REORG.TODO/sysdeps/x86_64/fpu/s_lrint.S new file mode 100644 index 0000000000..dfc31359a0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_lrint.S @@ -0,0 +1 @@ +/* Not needed, see s_llrint.S. */ diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_lrintf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_lrintf.S new file mode 100644 index 0000000000..fcdc4dca9a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_lrintf.S @@ -0,0 +1 @@ +/* Not needed, see s_llrintf.S. */ diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_lrintl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_lrintl.S new file mode 100644 index 0000000000..ef9c45d00d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_lrintl.S @@ -0,0 +1 @@ +/* Not needed, see s_llrintl.S. */ diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_nearbyintl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_nearbyintl.S new file mode 100644 index 0000000000..31b21a5037 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_nearbyintl.S @@ -0,0 +1,19 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + */ +/* Adapted for use as nearbyint by Ulrich Drepper <drepper@cygnus.com>. */ + +#include <machine/asm.h> + +ENTRY(__nearbyintl) + fldt 8(%rsp) + fnstenv -28(%rsp) + frndint + fnstsw + andl $0x1, %eax + orl %eax, -24(%rsp) + fldenv -28(%rsp) + ret +END (__nearbyintl) +weak_alias (__nearbyintl, nearbyintl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_nextafterl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_nextafterl.c new file mode 100644 index 0000000000..f59f16848f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_nextafterl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_nextafterl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_nexttoward.c b/REORG.TODO/sysdeps/x86_64/fpu/s_nexttoward.c new file mode 100644 index 0000000000..aee2bb5895 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_nexttoward.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_nexttoward.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_nexttowardf.c b/REORG.TODO/sysdeps/x86_64/fpu/s_nexttowardf.c new file mode 100644 index 0000000000..55e95f6916 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_nexttowardf.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_nexttowardf.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_rintl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_rintl.c new file mode 100644 index 0000000000..1cad42e921 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_rintl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_rintl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_scalbnl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_scalbnl.S new file mode 100644 index 0000000000..6c7683c32b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_scalbnl.S @@ -0,0 +1,17 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com> + * Changes for x86-64 by Andreas Jaeger <aj@suse.de>=09 + * Public domain. + */ + +#include <machine/asm.h> + +ENTRY(__scalbnl) + movl %edi,-4(%rsp) + fildl -4(%rsp) + fldt 8(%rsp) + fscale + fstp %st(1) + ret +END (__scalbnl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_signbit.S b/REORG.TODO/sysdeps/x86_64/fpu/s_signbit.S new file mode 100644 index 0000000000..a24757cd48 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_signbit.S @@ -0,0 +1,26 @@ +/* Return nonzero value if number is negative. + Copyright (C) 2009-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@redha.com>, 2009. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__signbit) + pmovmskb %xmm0, %eax + andl $0x80, %eax + ret +END(__signbit) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_signbitf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_signbitf.S new file mode 100644 index 0000000000..7739424bf6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_signbitf.S @@ -0,0 +1,26 @@ +/* Return nonzero value if number is negative. + Copyright (C) 2009-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@redha.com>, 2009. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__signbitf) + pmovmskb %xmm0, %eax + andl $0x8, %eax + ret +END(__signbitf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_significandl.c b/REORG.TODO/sysdeps/x86_64/fpu/s_significandl.c new file mode 100644 index 0000000000..a4ad986164 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_significandl.c @@ -0,0 +1 @@ +#include <sysdeps/i386/fpu/s_significandl.c> diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_sincosf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_sincosf.S new file mode 100644 index 0000000000..e6ed81ed91 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_sincosf.S @@ -0,0 +1,564 @@ +/* Optimized sincosf function. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#define __need_Emath +#include <bits/errno.h> + +/* Short algorithm description: + * + * 1) if |x|==0: sin(x)=x, + * cos(x)=1. + * 2) if |x|<2^-27: sin(x)=x-x*DP_SMALL, raising underflow only when needed, + * cos(x)=1-|x|. + * 3) if |x|<2^-5 : sin(x)=x+x*x^2*DP_SIN2_0+x^5*DP_SIN2_1, + * cos(x)=1+1*x^2*DP_COS2_0+x^5*DP_COS2_1 + * 4) if |x|< Pi/4: sin(x)=x+x*x^2*(S0+x^2*(S1+x^2*(S2+x^2*(S3+x^2*S4)))), + * cos(x)=1+1*x^2*(C0+x^2*(C1+x^2*(C2+x^2*(C3+x^2*C4)))). + * 5) if |x| < 9*Pi/4: + * 5.1) Range reduction: + * k=trunc(|x|/(Pi/4)), j=(k+1)&0x0e, n=k+1, t=|x|-j*Pi/4. + * 5.2) Reconstruction: + * sign_sin = sign(x) * (-1.0)^(( n >>2)&1) + * sign_cos = (-1.0)^(((n+2)>>2)&1) + * poly_sin = ((((S4*t^2 + S3)*t^2 + S2)*t^2 + S1)*t^2 + S0)*t^2*t+t + * poly_cos = ((((C4*t^2 + C3)*t^2 + C2)*t^2 + C1)*t^2 + C0)*t^2*s+s + * if(n&2 != 0) { + * using cos(t) and sin(t) polynomials for |t|<Pi/4, results are + * cos(x) = poly_sin * sign_cos + * sin(x) = poly_cos * sign_sin + * } else { + * sin(x) = poly_sin * sign_sin + * cos(x) = poly_cos * sign_cos + * } + * 6) if |x| < 2^23, large args: + * 6.1) Range reduction: + * k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+1, t=|x|-j*Pi/4 + * 6.2) Reconstruction same as (5.2). + * 7) if |x| >= 2^23, very large args: + * 7.1) Range reduction: + * k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+1, t=|x|-j*Pi/4. + * 7.2) Reconstruction same as (5.2). + * 8) if x is Inf, return x-x, and set errno=EDOM. + * 9) if x is NaN, return x-x. + * + * Special cases: + * sin/cos(+-0) = +-0/1 not raising inexact/underflow, + * sin/cos(subnormal) raises inexact/underflow, + * sin/cos(min_normalized) raises inexact/underflow, + * sin/cos(normalized) raises inexact, + * sin/cos(Inf) = NaN, raises invalid, sets errno to EDOM, + * sin/cos(NaN) = NaN. + */ + +# define ARG_SIN_PTR %rdi +# define ARG_COS_PTR %rsi + + .text +ENTRY(__sincosf) + /* Input: %xmm0 contains single precision argument x */ + /* %rdi points to sin result */ + /* %rsi points to cos result */ + + movd %xmm0, %eax /* Bits of x */ + movaps %xmm0, %xmm7 /* Copy of x */ + cvtss2sd %xmm0, %xmm0 /* DP x */ + movss L(SP_ABS_MASK)(%rip), %xmm3 + movl %eax, %r8d /* Copy of x bits */ + andl $0x7fffffff, %eax /* |x| */ + + cmpl $0x3f490fdb, %eax /* |x|<Pi/4 ? */ + jb L(arg_less_pio4) + + /* Here if |x|>=Pi/4 */ + andps %xmm7, %xmm3 /* SP |x| */ + andpd L(DP_ABS_MASK)(%rip),%xmm0 /* DP |x| */ + movss L(SP_INVPIO4)(%rip), %xmm2 /* SP 1/(Pi/4) */ + + cmpl $0x40e231d6, %eax /* |x|<9*Pi/4 ? */ + jae L(large_args) + + /* Here if Pi/4<=|x|<9*Pi/4 */ + mulss %xmm3, %xmm2 /* SP |x|/(Pi/4) */ + movl %r8d, %ecx /* Load x */ + cvttss2si %xmm2, %eax /* k, number of Pi/4 in x */ + lea L(PIO4J)(%rip), %r9 + shrl $29, %ecx /* (sign of x) << 2 */ + addl $1, %eax /* k+1 */ + movl $0x0e, %edx + andl %eax, %edx /* j = (k+1)&0x0e */ + subsd (%r9,%rdx,8), %xmm0 /* t = |x| - j * Pi/4 */ + +L(reconstruction): + /* Input: %eax=n, %xmm0=t, %ecx=sign(x) */ + + movaps %xmm0, %xmm4 /* t */ + movhpd L(DP_ONES)(%rip), %xmm4 /* 1|t */ + mulsd %xmm0, %xmm0 /* y=t^2 */ + movl $2, %edx + unpcklpd %xmm0, %xmm0 /* y|y */ + addl %eax, %edx /* k+2 */ + movaps %xmm0, %xmm1 /* y|y */ + mulpd %xmm0, %xmm0 /* z=t^4|z=t^4 */ + + movaps L(DP_SC4)(%rip), %xmm2 /* S4 */ + mulpd %xmm0, %xmm2 /* z*S4 */ + movaps L(DP_SC3)(%rip), %xmm3 /* S3 */ + mulpd %xmm0, %xmm3 /* z*S3 */ + xorl %eax, %ecx /* (sign_x ^ (k>>2))<<2 */ + addpd L(DP_SC2)(%rip), %xmm2 /* S2+z*S4 */ + mulpd %xmm0, %xmm2 /* z*(S2+z*S4) */ + shrl $2, %edx /* (k+2)>>2 */ + addpd L(DP_SC1)(%rip), %xmm3 /* S1+z*S3 */ + mulpd %xmm0, %xmm3 /* z*(S1+z*S3) */ + shrl $2, %ecx /* sign_x ^ k>>2 */ + addpd L(DP_SC0)(%rip), %xmm2 /* S0+z*(S2+z*S4) */ + andl $1, %edx /* sign_cos = ((k+2)>>2)&1 */ + mulpd %xmm1, %xmm2 /* y*(S0+z*(S2+z*S4)) */ + andl $1, %ecx /* sign_sin = sign_x ^ ((k>>2)&1) */ + addpd %xmm2, %xmm3 /* y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + lea L(DP_ONES)(%rip), %r9 + mulpd %xmm4, %xmm3 /*t*y*(S0+y*(S1+y*(S2+y*(S3+y*S4))))*/ + testl $2, %eax /* n&2 != 0 ? */ + addpd %xmm4, %xmm3 /*t+t*y*(S0+y*(S1+y*(S2+y*(S3+y*S4))*/ + jnz L(sin_result_sin_poly) + +/*L(sin_result_cos_poly):*/ + /* + * Here if + * cos(x) = poly_sin * sign_cos + * sin(x) = poly_cos * sign_sin + */ + movsd (%r9,%rcx,8), %xmm4 /* 0|sign_sin */ + movhpd (%r9,%rdx,8), %xmm4 /* sign_cos|sign_sin */ + mulpd %xmm4, %xmm3 /* result_cos|result_sin */ + cvtpd2ps %xmm3, %xmm0 /* SP results */ + movss %xmm0, (ARG_SIN_PTR) /* store sin(x) from xmm0[0] */ + shufps $1, %xmm0, %xmm0 /* move cos(x) to xmm0[0] */ + movss %xmm0, (ARG_COS_PTR) /* store cos(x) */ + ret + + .p2align 4 +L(sin_result_sin_poly): + /* + * Here if + * sin(x) = poly_sin * sign_sin + * cos(x) = poly_cos * sign_cos + */ + movsd (%r9,%rdx,8), %xmm4 /* 0|sign_cos */ + movhpd (%r9,%rcx,8), %xmm4 /* sign_sin|sign_cos */ + mulpd %xmm4, %xmm3 /* result_sin|result_cos */ + cvtpd2ps %xmm3, %xmm0 /* SP results */ + movss %xmm0, (ARG_COS_PTR) /* store cos(x) from xmm0[0] */ + shufps $1, %xmm0, %xmm0 /* move sin(x) to xmm0[0] */ + movss %xmm0, (ARG_SIN_PTR) /* store sin(x) */ + ret + + .p2align 4 +L(large_args): + /* Here if |x|>=9*Pi/4 */ + cmpl $0x7f800000, %eax /* x is Inf or NaN ? */ + jae L(arg_inf_or_nan) + + /* Here if finite |x|>=9*Pi/4 */ + cmpl $0x4b000000, %eax /* |x|<2^23 ? */ + jae L(very_large_args) + + /* Here if 9*Pi/4<=|x|<2^23 */ + movsd L(DP_INVPIO4)(%rip), %xmm1 /* 1/(Pi/4) */ + mulsd %xmm0, %xmm1 /* |x|/(Pi/4) */ + cvttsd2si %xmm1, %eax /* k=trunc(|x|/(Pi/4)) */ + addl $1, %eax /* k+1 */ + movl %eax, %edx + andl $0xfffffffe, %edx /* j=(k+1)&0xfffffffe */ + cvtsi2sdl %edx, %xmm4 /* DP j */ + movl %r8d, %ecx /* Load x */ + movsd L(DP_PIO4HI)(%rip), %xmm2 /* -PIO4HI = high part of -Pi/4 */ + shrl $29, %ecx /* (sign of x) << 2 */ + mulsd %xmm4, %xmm2 /* -j*PIO4HI */ + movsd L(DP_PIO4LO)(%rip), %xmm3 /* -PIO4LO = low part of -Pi/4 */ + addsd %xmm2, %xmm0 /* |x| - j*PIO4HI */ + mulsd %xmm3, %xmm4 /* j*PIO4LO */ + addsd %xmm4, %xmm0 /* t = |x| - j*PIO4HI - j*PIO4LO */ + jmp L(reconstruction) + + .p2align 4 +L(very_large_args): + /* Here if finite |x|>=2^23 */ + + /* bitpos = (ix>>23) - BIAS_32 + 59; */ + shrl $23, %eax /* eb = biased exponent of x */ + subl $68, %eax /* bitpos=eb-0x7f+59, where 0x7f */ + /*is exponent bias */ + movl $28, %ecx /* %cl=28 */ + movl %eax, %edx /* bitpos copy */ + + /* j = bitpos/28; */ + div %cl /* j in register %al=%ax/%cl */ + movapd %xmm0, %xmm3 /* |x| */ + andl $0xff, %eax /* clear unneeded remainder from %ah*/ + + imull $28, %eax, %ecx /* j*28 */ + lea L(_FPI)(%rip), %r9 + movsd L(DP_HI_MASK)(%rip), %xmm4 /* DP_HI_MASK */ + movapd %xmm0, %xmm5 /* |x| */ + mulsd -16(%r9,%rax,8), %xmm3 /* tmp3 = FPI[j-2]*|x| */ + movapd %xmm0, %xmm1 /* |x| */ + mulsd -8(%r9,%rax,8), %xmm5 /* tmp2 = FPI[j-1]*|x| */ + mulsd (%r9,%rax,8), %xmm0 /* tmp0 = FPI[j]*|x| */ + addl $19, %ecx /* j*28+19 */ + mulsd 8(%r9,%rax,8), %xmm1 /* tmp1 = FPI[j+1]*|x| */ + cmpl %ecx, %edx /* bitpos>=j*28+19 ? */ + jl L(very_large_skip1) + + /* Here if bitpos>=j*28+19 */ + andpd %xmm3, %xmm4 /* HI(tmp3) */ + subsd %xmm4, %xmm3 /* tmp3 = tmp3 - HI(tmp3) */ +L(very_large_skip1): + + movsd L(DP_2POW52)(%rip), %xmm6 + movapd %xmm5, %xmm2 /* tmp2 copy */ + addsd %xmm3, %xmm5 /* tmp5 = tmp3 + tmp2 */ + movl $1, %edx + addsd %xmm5, %xmm6 /* tmp6 = tmp5 + 2^52 */ + movsd 8+L(DP_2POW52)(%rip), %xmm4 + movd %xmm6, %eax /* k = I64_LO(tmp6); */ + addsd %xmm6, %xmm4 /* tmp4 = tmp6 - 2^52 */ + movl %r8d, %ecx /* Load x */ + comisd %xmm5, %xmm4 /* tmp4 > tmp5 ? */ + jbe L(very_large_skip2) + + /* Here if tmp4 > tmp5 */ + subl $1, %eax /* k-- */ + addsd 8+L(DP_ONES)(%rip), %xmm4 /* tmp4 -= 1.0 */ +L(very_large_skip2): + + andl %eax, %edx /* k&1 */ + lea L(DP_ZERONE)(%rip), %r9 + subsd %xmm4, %xmm3 /* tmp3 -= tmp4 */ + addsd (%r9,%rdx,8), %xmm3 /* t = DP_ZERONE[k&1] + tmp3 */ + addsd %xmm2, %xmm3 /* t += tmp2 */ + shrl $29, %ecx /* (sign of x) << 2 */ + addsd %xmm3, %xmm0 /* t += tmp0 */ + addl $1, %eax /* n=k+1 */ + addsd %xmm1, %xmm0 /* t += tmp1 */ + mulsd L(DP_PIO4)(%rip), %xmm0 /* t *= PI04 */ + + jmp L(reconstruction) /* end of very_large_args peth */ + + .p2align 4 +L(arg_less_pio4): + /* Here if |x|<Pi/4 */ + cmpl $0x3d000000, %eax /* |x|<2^-5 ? */ + jl L(arg_less_2pn5) + + /* Here if 2^-5<=|x|<Pi/4 */ + movaps %xmm0, %xmm3 /* DP x */ + movhpd L(DP_ONES)(%rip), %xmm3 /* DP 1|x */ + mulsd %xmm0, %xmm0 /* DP y=x^2 */ + unpcklpd %xmm0, %xmm0 /* DP y|y */ + movaps %xmm0, %xmm1 /* y|y */ + mulpd %xmm0, %xmm0 /* z=x^4|z=x^4 */ + + movapd L(DP_SC4)(%rip), %xmm4 /* S4 */ + mulpd %xmm0, %xmm4 /* z*S4 */ + movapd L(DP_SC3)(%rip), %xmm5 /* S3 */ + mulpd %xmm0, %xmm5 /* z*S3 */ + addpd L(DP_SC2)(%rip), %xmm4 /* S2+z*S4 */ + mulpd %xmm0, %xmm4 /* z*(S2+z*S4) */ + addpd L(DP_SC1)(%rip), %xmm5 /* S1+z*S3 */ + mulpd %xmm0, %xmm5 /* z*(S1+z*S3) */ + addpd L(DP_SC0)(%rip), %xmm4 /* S0+z*(S2+z*S4) */ + mulpd %xmm1, %xmm4 /* y*(S0+z*(S2+z*S4)) */ + mulpd %xmm3, %xmm5 /* x*z*(S1+z*S3) */ + mulpd %xmm3, %xmm4 /* x*y*(S0+z*(S2+z*S4)) */ + addpd %xmm5, %xmm4 /*x*y*(S0+y*(S1+y*(S2+y*(S3+y*S4))))*/ + addpd %xmm4, %xmm3 /*x+x*y*(S0+y*(S1+y*(S2+y*(S3+y*S4))*/ + cvtpd2ps %xmm3, %xmm0 /* SP results */ + movss %xmm0, (ARG_SIN_PTR) /* store sin(x) from xmm0[0] */ + shufps $1, %xmm0, %xmm0 /* move cos(x) to xmm0[0] */ + movss %xmm0, (ARG_COS_PTR) /* store cos(x) */ + ret + + .p2align 4 +L(arg_less_2pn5): + /* Here if |x|<2^-5 */ + cmpl $0x32000000, %eax /* |x|<2^-27 ? */ + jl L(arg_less_2pn27) + + /* Here if 2^-27<=|x|<2^-5 */ + movaps %xmm0, %xmm1 /* DP x */ + movhpd L(DP_ONES)(%rip), %xmm1 /* DP 1|x */ + mulsd %xmm0, %xmm0 /* DP x^2 */ + unpcklpd %xmm0, %xmm0 /* DP x^2|x^2 */ + + movaps L(DP_SINCOS2_1)(%rip), %xmm3 /* DP DP_SIN2_1 */ + mulpd %xmm0, %xmm3 /* DP x^2*DP_SIN2_1 */ + addpd L(DP_SINCOS2_0)(%rip), %xmm3 /* DP DP_SIN2_0+x^2*DP_SIN2_1 */ + mulpd %xmm0, %xmm3 /* DP x^2*DP_SIN2_0+x^4*DP_SIN2_1 */ + mulpd %xmm1, %xmm3 /* DP x^3*DP_SIN2_0+x^5*DP_SIN2_1 */ + addpd %xmm1, %xmm3 /* DP x+x^3*DP_SIN2_0+x^5*DP_SIN2_1 */ + cvtpd2ps %xmm3, %xmm0 /* SP results */ + movss %xmm0, (ARG_SIN_PTR) /* store sin(x) from xmm0[0] */ + shufps $1, %xmm0, %xmm0 /* move cos(x) to xmm0[0] */ + movss %xmm0, (ARG_COS_PTR) /* store cos(x) */ + ret + + .p2align 4 +L(arg_less_2pn27): + cmpl $0, %eax /* x=0 ? */ + je L(arg_zero) /* in case x=0 return sin(+-0)==+-0 */ + /* Here if |x|<2^-27 */ + /* + * Special cases here: + * sin(subnormal) raises inexact/underflow + * sin(min_normalized) raises inexact/underflow + * sin(normalized) raises inexact + * cos(here)=1-|x| (raising inexact) + */ + movaps %xmm0, %xmm3 /* DP x */ + mulsd L(DP_SMALL)(%rip), %xmm0/* DP x*DP_SMALL */ + subsd %xmm0, %xmm3 /* DP sin result is x-x*DP_SMALL */ + andps L(SP_ABS_MASK)(%rip), %xmm7/* SP |x| */ + cvtsd2ss %xmm3, %xmm0 /* sin(x) */ + movss L(SP_ONE)(%rip), %xmm1 /* SP 1.0 */ + movss %xmm0, (ARG_SIN_PTR) /* sin(x) store */ + subss %xmm7, %xmm1 /* cos(x) */ + movss %xmm1, (ARG_COS_PTR) /* cos(x) store */ + ret + + .p2align 4 +L(arg_zero): + movss L(SP_ONE)(%rip), %xmm0 /* 1.0 */ + movss %xmm7, (ARG_SIN_PTR) /* sin(+-0)==x */ + movss %xmm0, (ARG_COS_PTR) /* cos(+-0)==1 */ + ret + + .p2align 4 +L(arg_inf_or_nan): + /* Here if |x| is Inf or NAN */ + jne L(skip_errno_setting) /* in case of x is NaN */ + + /* Align stack to 16 bytes. */ + subq $8, %rsp + cfi_adjust_cfa_offset (8) + /* Here if x is Inf. Set errno to EDOM. */ + call JUMPTARGET(__errno_location) + addq $8, %rsp + cfi_adjust_cfa_offset (-8) + + movl $EDOM, (%rax) + + .p2align 4 +L(skip_errno_setting): + /* Here if |x| is Inf or NAN. Continued. */ + subss %xmm7, %xmm7 /* x-x, result is NaN */ + movss %xmm7, (ARG_SIN_PTR) + movss %xmm7, (ARG_COS_PTR) + ret +END(__sincosf) + + .section .rodata, "a" + .p2align 3 +L(PIO4J): /* Table of j*Pi/4, for j=0,1,..,10 */ + .long 0x00000000,0x00000000 + .long 0x54442d18,0x3fe921fb + .long 0x54442d18,0x3ff921fb + .long 0x7f3321d2,0x4002d97c + .long 0x54442d18,0x400921fb + .long 0x2955385e,0x400f6a7a + .long 0x7f3321d2,0x4012d97c + .long 0xe9bba775,0x4015fdbb + .long 0x54442d18,0x401921fb + .long 0xbeccb2bb,0x401c463a + .long 0x2955385e,0x401f6a7a + .type L(PIO4J), @object + ASM_SIZE_DIRECTIVE(L(PIO4J)) + + .p2align 3 +L(_FPI): /* 4/Pi broken into sum of positive DP values */ + .long 0x00000000,0x00000000 + .long 0x6c000000,0x3ff45f30 + .long 0x2a000000,0x3e3c9c88 + .long 0xa8000000,0x3c54fe13 + .long 0xd0000000,0x3aaf47d4 + .long 0x6c000000,0x38fbb81b + .long 0xe0000000,0x3714acc9 + .long 0x7c000000,0x3560e410 + .long 0x56000000,0x33bca2c7 + .long 0xac000000,0x31fbd778 + .long 0xe0000000,0x300b7246 + .long 0xe8000000,0x2e5d2126 + .long 0x48000000,0x2c970032 + .long 0xe8000000,0x2ad77504 + .long 0xe0000000,0x290921cf + .long 0xb0000000,0x274deb1c + .long 0xe0000000,0x25829a73 + .long 0xbe000000,0x23fd1046 + .long 0x10000000,0x2224baed + .long 0x8e000000,0x20709d33 + .long 0x80000000,0x1e535a2f + .long 0x64000000,0x1cef904e + .long 0x30000000,0x1b0d6398 + .long 0x24000000,0x1964ce7d + .long 0x16000000,0x17b908bf + .type L(_FPI), @object + ASM_SIZE_DIRECTIVE(L(_FPI)) + +/* Coefficients of polynomials for */ +/* sin(x)~=x+x*x^2*(DP_SIN2_0+x^2*DP_SIN2_1) in low DP part, */ +/* cos(x)~=1+1*x^2*(DP_COS2_0+x^2*DP_COS2_1) in high DP part, */ +/* for |x|<2^-5. */ + .p2align 4 +L(DP_SINCOS2_0): + .long 0x5543d49d,0xbfc55555 + .long 0xff5cc6fd,0xbfdfffff + .type L(DP_SINCOS2_0), @object + ASM_SIZE_DIRECTIVE(L(DP_SINCOS2_0)) + + .p2align 4 +L(DP_SINCOS2_1): + .long 0x75cec8c5,0x3f8110f4 + .long 0xb178dac5,0x3fa55514 + .type L(DP_SINCOS2_1), @object + ASM_SIZE_DIRECTIVE(L(DP_SINCOS2_1)) + + + .p2align 3 +L(DP_ZERONE): + .long 0x00000000,0x00000000 /* 0.0 */ + .long 0x00000000,0xbff00000 /* 1.0 */ + .type L(DP_ZERONE), @object + ASM_SIZE_DIRECTIVE(L(DP_ZERONE)) + + .p2align 3 +L(DP_ONES): + .long 0x00000000,0x3ff00000 /* +1.0 */ + .long 0x00000000,0xbff00000 /* -1.0 */ + .type L(DP_ONES), @object + ASM_SIZE_DIRECTIVE(L(DP_ONES)) + +/* Coefficients of polynomials for */ +/* sin(t)~=t+t*t^2*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4)))) in low DP part, */ +/* cos(t)~=1+1*t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4)))) in high DP part, */ +/* for |t|<Pi/4. */ + .p2align 4 +L(DP_SC4): + .long 0x1674b58a,0xbe5a947e + .long 0xdd8844d7,0xbe923c97 + .type L(DP_SC4), @object + ASM_SIZE_DIRECTIVE(L(DP_SC4)) + + .p2align 4 +L(DP_SC3): + .long 0x64e6b5b4,0x3ec71d72 + .long 0x9ac43cc0,0x3efa00eb + .type L(DP_SC3), @object + ASM_SIZE_DIRECTIVE(L(DP_SC3)) + + .p2align 4 +L(DP_SC2): + .long 0x8b4bd1f9,0xbf2a019f + .long 0x348b6874,0xbf56c16b + .type L(DP_SC2), @object + ASM_SIZE_DIRECTIVE(L(DP_SC2)) + + .p2align 4 +L(DP_SC1): + .long 0x10c2688b,0x3f811111 + .long 0x545c50c7,0x3fa55555 + .type L(DP_SC1), @object + ASM_SIZE_DIRECTIVE(L(DP_SC1)) + + .p2align 4 +L(DP_SC0): + .long 0x55551cd9,0xbfc55555 + .long 0xfffe98ae,0xbfdfffff + .type L(DP_SC0), @object + ASM_SIZE_DIRECTIVE(L(DP_SC0)) + + .p2align 3 +L(DP_SMALL): + .long 0x00000000,0x3cd00000 /* 2^(-50) */ + .type L(DP_SMALL), @object + ASM_SIZE_DIRECTIVE(L(DP_SMALL)) + + .p2align 3 +L(DP_PIO4): + .long 0x54442d18,0x3fe921fb /* Pi/4 */ + .type L(DP_PIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4)) + + .p2align 3 +L(DP_2POW52): + .long 0x00000000,0x43300000 /* +2^52 */ + .long 0x00000000,0xc3300000 /* -2^52 */ + .type L(DP_2POW52), @object + ASM_SIZE_DIRECTIVE(L(DP_2POW52)) + + .p2align 3 +L(DP_INVPIO4): + .long 0x6dc9c883,0x3ff45f30 /* 4/Pi */ + .type L(DP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_INVPIO4)) + + .p2align 3 +L(DP_PIO4HI): + .long 0x54000000,0xbfe921fb /* High part of Pi/4 */ + .type L(DP_PIO4HI), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4HI)) + + .p2align 3 +L(DP_PIO4LO): + .long 0x11A62633,0xbe010b46 /* Low part of Pi/4 */ + .type L(DP_PIO4LO), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4LO)) + + .p2align 2 +L(SP_INVPIO4): + .long 0x3fa2f983 /* 4/Pi */ + .type L(SP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(SP_INVPIO4)) + + .p2align 4 +L(DP_ABS_MASK): /* Mask for getting DP absolute value */ + .long 0xffffffff,0x7fffffff + .long 0xffffffff,0x7fffffff + .type L(DP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(DP_ABS_MASK)) + + .p2align 3 +L(DP_HI_MASK): /* Mask for getting high 21 bits of DP value */ + .long 0x00000000,0xffffffff + .type L(DP_HI_MASK), @object + ASM_SIZE_DIRECTIVE(L(DP_HI_MASK)) + + .p2align 4 +L(SP_ABS_MASK): /* Mask for getting SP absolute value */ + .long 0x7fffffff,0x7fffffff + .long 0x7fffffff,0x7fffffff + .type L(SP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(SP_ABS_MASK)) + + .p2align 2 +L(SP_ONE): + .long 0x3f800000 /* 1.0 */ + .type L(SP_ONE), @object + ASM_SIZE_DIRECTIVE(L(SP_ONE)) + +weak_alias(__sincosf, sincosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_sinf.S b/REORG.TODO/sysdeps/x86_64/fpu/s_sinf.S new file mode 100644 index 0000000000..0aa5d43d8c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_sinf.S @@ -0,0 +1,559 @@ +/* Optimized sinf function. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#define __need_Emath +#include <bits/errno.h> + +/* Short algorithm description: + * + * 1) if |x| == 0: return x. + * 2) if |x| < 2^-27: return x-x*DP_SMALL, raise underflow only when needed. + * 3) if |x| < 2^-5 : return x+x^3*DP_SIN2_0+x^5*DP_SIN2_1. + * 4) if |x| < Pi/4: return x+x^3*(S0+x^2*(S1+x^2*(S2+x^2*(S3+x^2*S4)))). + * 5) if |x| < 9*Pi/4: + * 5.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0x0e, n=k+1, + * t=|x|-j*Pi/4. + * 5.2) Reconstruction: + * s = sign(x) * (-1.0)^((n>>2)&1) + * if(n&2 != 0) { + * using cos(t) polynomial for |t|<Pi/4, result is + * s * (1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4))))). + * } else { + * using sin(t) polynomial for |t|<Pi/4, result is + * s * t * (1.0+t^2*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4))))). + * } + * 6) if |x| < 2^23, large args: + * 6.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+1, + * t=|x|-j*Pi/4. + * 6.2) Reconstruction same as (5.2). + * 7) if |x| >= 2^23, very large args: + * 7.1) Range reduction: k=trunc(|x|/(Pi/4)), j=(k+1)&0xfffffffe, n=k+1, + * t=|x|-j*Pi/4. + * 7.2) Reconstruction same as (5.2). + * 8) if x is Inf, return x-x, and set errno=EDOM. + * 9) if x is NaN, return x-x. + * + * Special cases: + * sin(+-0) = +-0 not raising inexact/underflow, + * sin(subnormal) raises inexact/underflow, + * sin(min_normalized) raises inexact/underflow, + * sin(normalized) raises inexact, + * sin(Inf) = NaN, raises invalid, sets errno to EDOM, + * sin(NaN) = NaN. + */ + + .text +ENTRY(__sinf) + /* Input: single precision x in %xmm0 */ + + movd %xmm0, %eax /* Bits of x */ + movaps %xmm0, %xmm7 /* Copy of x */ + cvtss2sd %xmm0, %xmm0 /* DP x */ + movss L(SP_ABS_MASK)(%rip), %xmm3 + movl %eax, %edi /* Copy of x bits */ + andl $0x7fffffff, %eax /* |x| */ + + cmpl $0x3f490fdb, %eax /* |x|<Pi/4? */ + jb L(arg_less_pio4) + + /* Here if |x|>=Pi/4 */ + andps %xmm7, %xmm3 /* SP |x| */ + andpd L(DP_ABS_MASK)(%rip),%xmm0 /* DP |x| */ + movss L(SP_INVPIO4)(%rip), %xmm2 /* SP 1/(Pi/4) */ + + cmpl $0x40e231d6, %eax /* |x|<9*Pi/4? */ + jae L(large_args) + + /* Here if Pi/4<=|x|<9*Pi/4 */ + mulss %xmm3, %xmm2 /* SP |x|/(Pi/4) */ + movl %edi, %ecx /* Load x */ + cvttss2si %xmm2, %eax /* k, number of Pi/4 in x */ + lea L(PIO4J)(%rip), %rsi + shrl $31, %ecx /* sign of x */ + addl $1, %eax /* k+1 */ + movl $0x0e, %edx + andl %eax, %edx /* j = (k+1)&0x0e */ + subsd (%rsi,%rdx,8), %xmm0 /* t = |x| - j * Pi/4 */ + +L(reconstruction): + /* Input: %eax=n, %xmm0=t, %ecx=sign(x) */ + testl $2, %eax /* n&2 != 0? */ + jz L(sin_poly) + +/*L(cos_poly):*/ + /* Here if sin(x) calculated using cos(t) polynomial for |t|<Pi/4: + * y = t*t; z = y*y; + * s = sign(x) * (-1.0)^((n>>2)&1) + * result = s * (1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4))))) + */ + shrl $2, %eax /* n>>2 */ + mulsd %xmm0, %xmm0 /* y=t^2 */ + andl $1, %eax /* (n>>2)&1 */ + movaps %xmm0, %xmm1 /* y */ + mulsd %xmm0, %xmm0 /* z=t^4 */ + + movsd L(DP_C4)(%rip), %xmm4 /* C4 */ + mulsd %xmm0, %xmm4 /* z*C4 */ + xorl %eax, %ecx /* (-1.0)^((n>>2)&1) XOR sign(x) */ + movsd L(DP_C3)(%rip), %xmm3 /* C3 */ + mulsd %xmm0, %xmm3 /* z*C3 */ + lea L(DP_ONES)(%rip), %rsi + addsd L(DP_C2)(%rip), %xmm4 /* C2+z*C4 */ + mulsd %xmm0, %xmm4 /* z*(C2+z*C4) */ + addsd L(DP_C1)(%rip), %xmm3 /* C1+z*C3 */ + mulsd %xmm0, %xmm3 /* z*(C1+z*C3) */ + addsd L(DP_C0)(%rip), %xmm4 /* C0+z*(C2+z*C4) */ + mulsd %xmm1, %xmm4 /* y*(C0+z*(C2+z*C4)) */ + + /* y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + addsd %xmm4, %xmm3 + /* 1.0+y*(C0+y*(C1+y*(C2+y*(C3+y*C4)))) */ + addsd L(DP_ONES)(%rip), %xmm3 + + mulsd (%rsi,%rcx,8), %xmm3 /* DP result */ + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(sin_poly): + /* Here if sin(x) calculated using sin(t) polynomial for |t|<Pi/4: + * y = t*t; z = y*y; + * s = sign(x) * (-1.0)^((n>>2)&1) + * result = s * t * (1.0+t^2*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4))))) + */ + + movaps %xmm0, %xmm4 /* t */ + shrl $2, %eax /* n>>2 */ + mulsd %xmm0, %xmm0 /* y=t^2 */ + andl $1, %eax /* (n>>2)&1 */ + movaps %xmm0, %xmm1 /* y */ + xorl %eax, %ecx /* (-1.0)^((n>>2)&1) XOR sign(x) */ + mulsd %xmm0, %xmm0 /* z=t^4 */ + + movsd L(DP_S4)(%rip), %xmm2 /* S4 */ + mulsd %xmm0, %xmm2 /* z*S4 */ + movsd L(DP_S3)(%rip), %xmm3 /* S3 */ + mulsd %xmm0, %xmm3 /* z*S3 */ + lea L(DP_ONES)(%rip), %rsi + addsd L(DP_S2)(%rip), %xmm2 /* S2+z*S4 */ + mulsd %xmm0, %xmm2 /* z*(S2+z*S4) */ + addsd L(DP_S1)(%rip), %xmm3 /* S1+z*S3 */ + mulsd %xmm0, %xmm3 /* z*(S1+z*S3) */ + addsd L(DP_S0)(%rip), %xmm2 /* S0+z*(S2+z*S4) */ + mulsd %xmm1, %xmm2 /* y*(S0+z*(S2+z*S4)) */ + /* t*s, where s = sign(x) * (-1.0)^((n>>2)&1) */ + mulsd (%rsi,%rcx,8), %xmm4 + /* y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm2, %xmm3 + /* t*s*y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + mulsd %xmm4, %xmm3 + /* t*s*(1.0+y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm4, %xmm3 + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(large_args): + /* Here if |x|>=9*Pi/4 */ + cmpl $0x7f800000, %eax /* x is Inf or NaN? */ + jae L(arg_inf_or_nan) + + /* Here if finite |x|>=9*Pi/4 */ + cmpl $0x4b000000, %eax /* |x|<2^23? */ + jae L(very_large_args) + + /* Here if 9*Pi/4<=|x|<2^23 */ + movsd L(DP_INVPIO4)(%rip), %xmm1 /* 1/(Pi/4) */ + mulsd %xmm0, %xmm1 /* |x|/(Pi/4) */ + cvttsd2si %xmm1, %eax /* k=trunc(|x|/(Pi/4)) */ + addl $1, %eax /* k+1 */ + movl %eax, %edx + andl $0xfffffffe, %edx /* j=(k+1)&0xfffffffe */ + cvtsi2sdl %edx, %xmm4 /* DP j */ + movl %edi, %ecx /* Load x */ + movsd L(DP_PIO4HI)(%rip), %xmm2 /* -PIO4HI = high part of -Pi/4 */ + shrl $31, %ecx /* sign bit of x */ + mulsd %xmm4, %xmm2 /* -j*PIO4HI */ + movsd L(DP_PIO4LO)(%rip), %xmm3 /* -PIO4LO = low part of -Pi/4 */ + addsd %xmm2, %xmm0 /* |x| - j*PIO4HI */ + mulsd %xmm3, %xmm4 /* j*PIO4LO */ + addsd %xmm4, %xmm0 /* t = |x| - j*PIO4HI - j*PIO4LO */ + jmp L(reconstruction) + + .p2align 4 +L(very_large_args): + /* Here if finite |x|>=2^23 */ + + /* bitpos = (ix>>23) - BIAS_32 + 59; */ + shrl $23, %eax /* eb = biased exponent of x */ + /* bitpos = eb - 0x7f + 59, where 0x7f is exponent bias */ + subl $68, %eax + movl $28, %ecx /* %cl=28 */ + movl %eax, %edx /* bitpos copy */ + + /* j = bitpos/28; */ + div %cl /* j in register %al=%ax/%cl */ + movapd %xmm0, %xmm3 /* |x| */ + /* clear unneeded remainder from %ah */ + andl $0xff, %eax + + imull $28, %eax, %ecx /* j*28 */ + lea L(_FPI)(%rip), %rsi + movsd L(DP_HI_MASK)(%rip), %xmm4 /* DP_HI_MASK */ + movapd %xmm0, %xmm5 /* |x| */ + mulsd -16(%rsi,%rax,8), %xmm3 /* tmp3 = FPI[j-2]*|x| */ + movapd %xmm0, %xmm1 /* |x| */ + mulsd -8(%rsi,%rax,8), %xmm5 /* tmp2 = FPI[j-1]*|x| */ + mulsd (%rsi,%rax,8), %xmm0 /* tmp0 = FPI[j]*|x| */ + addl $19, %ecx /* j*28+19 */ + mulsd 8(%rsi,%rax,8), %xmm1 /* tmp1 = FPI[j+1]*|x| */ + cmpl %ecx, %edx /* bitpos>=j*28+19? */ + jl L(very_large_skip1) + + /* Here if bitpos>=j*28+19 */ + andpd %xmm3, %xmm4 /* HI(tmp3) */ + subsd %xmm4, %xmm3 /* tmp3 = tmp3 - HI(tmp3) */ +L(very_large_skip1): + + movsd L(DP_2POW52)(%rip), %xmm6 + movapd %xmm5, %xmm2 /* tmp2 copy */ + addsd %xmm3, %xmm5 /* tmp5 = tmp3 + tmp2 */ + movl $1, %edx + addsd %xmm5, %xmm6 /* tmp6 = tmp5 + 2^52 */ + movsd 8+L(DP_2POW52)(%rip), %xmm4 + movd %xmm6, %eax /* k = I64_LO(tmp6); */ + addsd %xmm6, %xmm4 /* tmp4 = tmp6 - 2^52 */ + movl %edi, %ecx /* Load x */ + comisd %xmm5, %xmm4 /* tmp4 > tmp5? */ + jbe L(very_large_skip2) + + /* Here if tmp4 > tmp5 */ + subl $1, %eax /* k-- */ + addsd 8+L(DP_ONES)(%rip), %xmm4 /* tmp4 -= 1.0 */ +L(very_large_skip2): + + andl %eax, %edx /* k&1 */ + lea L(DP_ZERONE)(%rip), %rsi + subsd %xmm4, %xmm3 /* tmp3 -= tmp4 */ + addsd (%rsi,%rdx,8), %xmm3 /* t = DP_ZERONE[k&1] + tmp3 */ + addsd %xmm2, %xmm3 /* t += tmp2 */ + shrl $31, %ecx /* sign of x */ + addsd %xmm3, %xmm0 /* t += tmp0 */ + addl $1, %eax /* n=k+1 */ + addsd %xmm1, %xmm0 /* t += tmp1 */ + mulsd L(DP_PIO4)(%rip), %xmm0 /* t *= PI04 */ + + jmp L(reconstruction) /* end of very_large_args peth */ + + .p2align 4 +L(arg_less_pio4): + /* Here if |x|<Pi/4 */ + cmpl $0x3d000000, %eax /* |x|<2^-5? */ + jl L(arg_less_2pn5) + + /* Here if 2^-5<=|x|<Pi/4 */ + movaps %xmm0, %xmm3 /* x */ + mulsd %xmm0, %xmm0 /* y=x^2 */ + movaps %xmm0, %xmm1 /* y */ + mulsd %xmm0, %xmm0 /* z=x^4 */ + movsd L(DP_S4)(%rip), %xmm4 /* S4 */ + mulsd %xmm0, %xmm4 /* z*S4 */ + movsd L(DP_S3)(%rip), %xmm5 /* S3 */ + mulsd %xmm0, %xmm5 /* z*S3 */ + addsd L(DP_S2)(%rip), %xmm4 /* S2+z*S4 */ + mulsd %xmm0, %xmm4 /* z*(S2+z*S4) */ + addsd L(DP_S1)(%rip), %xmm5 /* S1+z*S3 */ + mulsd %xmm0, %xmm5 /* z*(S1+z*S3) */ + addsd L(DP_S0)(%rip), %xmm4 /* S0+z*(S2+z*S4) */ + mulsd %xmm1, %xmm4 /* y*(S0+z*(S2+z*S4)) */ + mulsd %xmm3, %xmm5 /* x*z*(S1+z*S3) */ + mulsd %xmm3, %xmm4 /* x*y*(S0+z*(S2+z*S4)) */ + /* x*y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm5, %xmm4 + /* x + x*y*(S0+y*(S1+y*(S2+y*(S3+y*S4)))) */ + addsd %xmm4, %xmm3 + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(arg_less_2pn5): + /* Here if |x|<2^-5 */ + cmpl $0x32000000, %eax /* |x|<2^-27? */ + jl L(arg_less_2pn27) + + /* Here if 2^-27<=|x|<2^-5 */ + movaps %xmm0, %xmm1 /* DP x */ + mulsd %xmm0, %xmm0 /* DP x^2 */ + movsd L(DP_SIN2_1)(%rip), %xmm3 /* DP DP_SIN2_1 */ + mulsd %xmm0, %xmm3 /* DP x^2*DP_SIN2_1 */ + addsd L(DP_SIN2_0)(%rip), %xmm3 /* DP DP_SIN2_0+x^2*DP_SIN2_1 */ + mulsd %xmm0, %xmm3 /* DP x^2*DP_SIN2_0+x^4*DP_SIN2_1 */ + mulsd %xmm1, %xmm3 /* DP x^3*DP_SIN2_0+x^5*DP_SIN2_1 */ + addsd %xmm1, %xmm3 /* DP x+x^3*DP_SIN2_0+x^5*DP_SIN2_1 */ + cvtsd2ss %xmm3, %xmm0 /* SP result */ + ret + + .p2align 4 +L(arg_less_2pn27): + cmpl $0, %eax /* x=0? */ + je L(arg_zero) /* in case x=0 return sin(+-0)==+-0 */ + /* Here if |x|<2^-27 */ + /* + * Special cases here: + * sin(subnormal) raises inexact/underflow + * sin(min_normalized) raises inexact/underflow + * sin(normalized) raises inexact + */ + movaps %xmm0, %xmm3 /* Copy of DP x */ + mulsd L(DP_SMALL)(%rip), %xmm0 /* x*DP_SMALL */ + subsd %xmm0, %xmm3 /* Result is x-x*DP_SMALL */ + cvtsd2ss %xmm3, %xmm0 /* Result converted to SP */ + ret + + .p2align 4 +L(arg_zero): + movaps %xmm7, %xmm0 /* SP x */ + ret + + .p2align 4 +L(arg_inf_or_nan): + /* Here if |x| is Inf or NAN */ + jne L(skip_errno_setting) /* in case of x is NaN */ + + /* Align stack to 16 bytes. */ + subq $8, %rsp + cfi_adjust_cfa_offset (8) + /* Here if x is Inf. Set errno to EDOM. */ + call JUMPTARGET(__errno_location) + addq $8, %rsp + cfi_adjust_cfa_offset (-8) + + movl $EDOM, (%rax) + + .p2align 4 +L(skip_errno_setting): + /* Here if |x| is Inf or NAN. Continued. */ + movaps %xmm7, %xmm0 /* load x */ + subss %xmm0, %xmm0 /* Result is NaN */ + ret +END(__sinf) + + .section .rodata, "a" + .p2align 3 +L(PIO4J): /* Table of j*Pi/4, for j=0,1,..,10 */ + .long 0x00000000,0x00000000 + .long 0x54442d18,0x3fe921fb + .long 0x54442d18,0x3ff921fb + .long 0x7f3321d2,0x4002d97c + .long 0x54442d18,0x400921fb + .long 0x2955385e,0x400f6a7a + .long 0x7f3321d2,0x4012d97c + .long 0xe9bba775,0x4015fdbb + .long 0x54442d18,0x401921fb + .long 0xbeccb2bb,0x401c463a + .long 0x2955385e,0x401f6a7a + .type L(PIO4J), @object + ASM_SIZE_DIRECTIVE(L(PIO4J)) + + .p2align 3 +L(_FPI): /* 4/Pi broken into sum of positive DP values */ + .long 0x00000000,0x00000000 + .long 0x6c000000,0x3ff45f30 + .long 0x2a000000,0x3e3c9c88 + .long 0xa8000000,0x3c54fe13 + .long 0xd0000000,0x3aaf47d4 + .long 0x6c000000,0x38fbb81b + .long 0xe0000000,0x3714acc9 + .long 0x7c000000,0x3560e410 + .long 0x56000000,0x33bca2c7 + .long 0xac000000,0x31fbd778 + .long 0xe0000000,0x300b7246 + .long 0xe8000000,0x2e5d2126 + .long 0x48000000,0x2c970032 + .long 0xe8000000,0x2ad77504 + .long 0xe0000000,0x290921cf + .long 0xb0000000,0x274deb1c + .long 0xe0000000,0x25829a73 + .long 0xbe000000,0x23fd1046 + .long 0x10000000,0x2224baed + .long 0x8e000000,0x20709d33 + .long 0x80000000,0x1e535a2f + .long 0x64000000,0x1cef904e + .long 0x30000000,0x1b0d6398 + .long 0x24000000,0x1964ce7d + .long 0x16000000,0x17b908bf + .type L(_FPI), @object + ASM_SIZE_DIRECTIVE(L(_FPI)) + +/* Coefficients of polynomial + for sin(x)~=x+x^3*DP_SIN2_0+x^5*DP_SIN2_1, |x|<2^-5. */ + .p2align 3 +L(DP_SIN2_0): + .long 0x5543d49d,0xbfc55555 + .type L(DP_SIN2_0), @object + ASM_SIZE_DIRECTIVE(L(DP_SIN2_0)) + + .p2align 3 +L(DP_SIN2_1): + .long 0x75cec8c5,0x3f8110f4 + .type L(DP_SIN2_1), @object + ASM_SIZE_DIRECTIVE(L(DP_SIN2_1)) + + .p2align 3 +L(DP_ZERONE): + .long 0x00000000,0x00000000 /* 0.0 */ + .long 0x00000000,0xbff00000 /* 1.0 */ + .type L(DP_ZERONE), @object + ASM_SIZE_DIRECTIVE(L(DP_ZERONE)) + + .p2align 3 +L(DP_ONES): + .long 0x00000000,0x3ff00000 /* +1.0 */ + .long 0x00000000,0xbff00000 /* -1.0 */ + .type L(DP_ONES), @object + ASM_SIZE_DIRECTIVE(L(DP_ONES)) + +/* Coefficients of polynomial + for sin(t)~=t+t^3*(S0+t^2*(S1+t^2*(S2+t^2*(S3+t^2*S4)))), |t|<Pi/4. */ + .p2align 3 +L(DP_S3): + .long 0x64e6b5b4,0x3ec71d72 + .type L(DP_S3), @object + ASM_SIZE_DIRECTIVE(L(DP_S3)) + + .p2align 3 +L(DP_S1): + .long 0x10c2688b,0x3f811111 + .type L(DP_S1), @object + ASM_SIZE_DIRECTIVE(L(DP_S1)) + + .p2align 3 +L(DP_S4): + .long 0x1674b58a,0xbe5a947e + .type L(DP_S4), @object + ASM_SIZE_DIRECTIVE(L(DP_S4)) + + .p2align 3 +L(DP_S2): + .long 0x8b4bd1f9,0xbf2a019f + .type L(DP_S2), @object + ASM_SIZE_DIRECTIVE(L(DP_S2)) + + .p2align 3 +L(DP_S0): + .long 0x55551cd9,0xbfc55555 + .type L(DP_S0), @object + ASM_SIZE_DIRECTIVE(L(DP_S0)) + + .p2align 3 +L(DP_SMALL): + .long 0x00000000,0x3cd00000 /* 2^(-50) */ + .type L(DP_SMALL), @object + ASM_SIZE_DIRECTIVE(L(DP_SMALL)) + +/* Coefficients of polynomial + for cos(t)~=1.0+t^2*(C0+t^2*(C1+t^2*(C2+t^2*(C3+t^2*C4)))), |t|<Pi/4. */ + .p2align 3 +L(DP_C3): + .long 0x9ac43cc0,0x3efa00eb + .type L(DP_C3), @object + ASM_SIZE_DIRECTIVE(L(DP_C3)) + + .p2align 3 +L(DP_C1): + .long 0x545c50c7,0x3fa55555 + .type L(DP_C1), @object + ASM_SIZE_DIRECTIVE(L(DP_C1)) + + .p2align 3 +L(DP_C4): + .long 0xdd8844d7,0xbe923c97 + .type L(DP_C4), @object + ASM_SIZE_DIRECTIVE(L(DP_C4)) + + .p2align 3 +L(DP_C2): + .long 0x348b6874,0xbf56c16b + .type L(DP_C2), @object + ASM_SIZE_DIRECTIVE(L(DP_C2)) + + .p2align 3 +L(DP_C0): + .long 0xfffe98ae,0xbfdfffff + .type L(DP_C0), @object + ASM_SIZE_DIRECTIVE(L(DP_C0)) + + .p2align 3 +L(DP_PIO4): + .long 0x54442d18,0x3fe921fb /* Pi/4 */ + .type L(DP_PIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4)) + + .p2align 3 +L(DP_2POW52): + .long 0x00000000,0x43300000 /* +2^52 */ + .long 0x00000000,0xc3300000 /* -2^52 */ + .type L(DP_2POW52), @object + ASM_SIZE_DIRECTIVE(L(DP_2POW52)) + + .p2align 3 +L(DP_INVPIO4): + .long 0x6dc9c883,0x3ff45f30 /* 4/Pi */ + .type L(DP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(DP_INVPIO4)) + + .p2align 3 +L(DP_PIO4HI): + .long 0x54000000,0xbfe921fb /* High part of Pi/4 */ + .type L(DP_PIO4HI), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4HI)) + + .p2align 3 +L(DP_PIO4LO): + .long 0x11A62633,0xbe010b46 /* Low part of Pi/4 */ + .type L(DP_PIO4LO), @object + ASM_SIZE_DIRECTIVE(L(DP_PIO4LO)) + + .p2align 2 +L(SP_INVPIO4): + .long 0x3fa2f983 /* 4/Pi */ + .type L(SP_INVPIO4), @object + ASM_SIZE_DIRECTIVE(L(SP_INVPIO4)) + + .p2align 4 +L(DP_ABS_MASK): /* Mask for getting DP absolute value */ + .long 0xffffffff,0x7fffffff + .long 0xffffffff,0x7fffffff + .type L(DP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(DP_ABS_MASK)) + + .p2align 3 +L(DP_HI_MASK): /* Mask for getting high 21 bits of DP value */ + .long 0x00000000,0xffffffff + .type L(DP_HI_MASK),@object + ASM_SIZE_DIRECTIVE(L(DP_HI_MASK)) + + .p2align 4 +L(SP_ABS_MASK): /* Mask for getting SP absolute value */ + .long 0x7fffffff,0x7fffffff + .long 0x7fffffff,0x7fffffff + .type L(SP_ABS_MASK), @object + ASM_SIZE_DIRECTIVE(L(SP_ABS_MASK)) + +weak_alias(__sinf, sinf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/s_truncl.S b/REORG.TODO/sysdeps/x86_64/fpu/s_truncl.S new file mode 100644 index 0000000000..b6ca0bae7b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/s_truncl.S @@ -0,0 +1,36 @@ +/* Truncate long double value. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <machine/asm.h> + +ENTRY(__truncl) + fldt 8(%rsp) + fnstenv -28(%rsp) + movl $0xc00, %edx + orl -28(%rsp), %edx + movl %edx, -32(%rsp) + fldcw -32(%rsp) + frndint + fnstsw + andl $0x1, %eax + orl %eax, -24(%rsp) + fldenv -28(%rsp) + ret +END(__truncl) +weak_alias (__truncl, truncl) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos2_core.S new file mode 100644 index 0000000000..db4fd3f62f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos2_core.S @@ -0,0 +1,29 @@ +/* Function cos vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2v_cos) +WRAPPER_IMPL_SSE2 cos +END (_ZGVbN2v_cos) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2v_cos) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core.S new file mode 100644 index 0000000000..a30f1c43f5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core.S @@ -0,0 +1,29 @@ +/* Function cos vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4v_cos) +WRAPPER_IMPL_AVX _ZGVbN2v_cos +END (_ZGVdN4v_cos) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4v_cos) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S new file mode 100644 index 0000000000..c6ce6fa1a4 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S @@ -0,0 +1,25 @@ +/* Function cos vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4v_cos) +WRAPPER_IMPL_AVX _ZGVbN2v_cos +END (_ZGVcN4v_cos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos8_core.S new file mode 100644 index 0000000000..5432bc701e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_cos8_core.S @@ -0,0 +1,25 @@ +/* Function cos vectorized with AVX-512, wrapper to AVX2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_cos) +WRAPPER_IMPL_AVX512 _ZGVdN4v_cos +END (_ZGVeN8v_cos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp2_core.S new file mode 100644 index 0000000000..92b328331d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp2_core.S @@ -0,0 +1,29 @@ +/* Function exp vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2v_exp) +WRAPPER_IMPL_SSE2 __exp_finite +END (_ZGVbN2v_exp) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2v_exp) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core.S new file mode 100644 index 0000000000..e062263d7a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core.S @@ -0,0 +1,29 @@ +/* Function exp vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4v_exp) +WRAPPER_IMPL_AVX _ZGVbN2v_exp +END (_ZGVdN4v_exp) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4v_exp) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S new file mode 100644 index 0000000000..21ae29d330 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S @@ -0,0 +1,25 @@ +/* Function exp vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4v_exp) +WRAPPER_IMPL_AVX _ZGVbN2v_exp +END (_ZGVcN4v_exp) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp8_core.S new file mode 100644 index 0000000000..28bfa98dde --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp8_core.S @@ -0,0 +1,25 @@ +/* Function exp vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_exp) +WRAPPER_IMPL_AVX512 _ZGVdN4v_exp +END (_ZGVeN8v_exp) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.S new file mode 100644 index 0000000000..521537e3f6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.S @@ -0,0 +1,1088 @@ +/* Data for vector function exp. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_d_exp_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function exp. + * The table may contain polynomial, reduction, lookup + * coefficients and other constants obtained through different + * methods of research and experimental work. */ + .globl __svml_dexp_data +__svml_dexp_data: + +/* Lookup table of 2^(j/2^K): */ +.if .-__svml_dexp_data != __dbT +.err +.endif + .quad 0x3ff0000000000000 + .quad 0x3ff002c605e2e8cf + .quad 0x3ff0058c86da1c0a + .quad 0x3ff0085382faef83 + .quad 0x3ff00b1afa5abcbf + .quad 0x3ff00de2ed0ee0f5 + .quad 0x3ff010ab5b2cbd11 + .quad 0x3ff0137444c9b5b5 + .quad 0x3ff0163da9fb3335 + .quad 0x3ff019078ad6a19f + .quad 0x3ff01bd1e77170b4 + .quad 0x3ff01e9cbfe113ef + .quad 0x3ff02168143b0281 + .quad 0x3ff02433e494b755 + .quad 0x3ff027003103b10e + .quad 0x3ff029ccf99d720a + .quad 0x3ff02c9a3e778061 + .quad 0x3ff02f67ffa765e6 + .quad 0x3ff032363d42b027 + .quad 0x3ff03504f75ef071 + .quad 0x3ff037d42e11bbcc + .quad 0x3ff03aa3e170aafe + .quad 0x3ff03d7411915a8a + .quad 0x3ff04044be896ab6 + .quad 0x3ff04315e86e7f85 + .quad 0x3ff045e78f5640b9 + .quad 0x3ff048b9b35659d8 + .quad 0x3ff04b8c54847a28 + .quad 0x3ff04e5f72f654b1 + .quad 0x3ff051330ec1a03f + .quad 0x3ff0540727fc1762 + .quad 0x3ff056dbbebb786b + .quad 0x3ff059b0d3158574 + .quad 0x3ff05c866520045b + .quad 0x3ff05f5c74f0bec2 + .quad 0x3ff06233029d8216 + .quad 0x3ff0650a0e3c1f89 + .quad 0x3ff067e197e26c14 + .quad 0x3ff06ab99fa6407c + .quad 0x3ff06d92259d794d + .quad 0x3ff0706b29ddf6de + .quad 0x3ff07344ac7d9d51 + .quad 0x3ff0761ead925493 + .quad 0x3ff078f92d32085d + .quad 0x3ff07bd42b72a836 + .quad 0x3ff07eafa86a2771 + .quad 0x3ff0818ba42e7d30 + .quad 0x3ff084681ed5a462 + .quad 0x3ff0874518759bc8 + .quad 0x3ff08a22912465f2 + .quad 0x3ff08d0088f8093f + .quad 0x3ff08fdf00068fe2 + .quad 0x3ff092bdf66607e0 + .quad 0x3ff0959d6c2c830d + .quad 0x3ff0987d61701716 + .quad 0x3ff09b5dd646dd77 + .quad 0x3ff09e3ecac6f383 + .quad 0x3ff0a1203f067a63 + .quad 0x3ff0a402331b9715 + .quad 0x3ff0a6e4a71c726e + .quad 0x3ff0a9c79b1f3919 + .quad 0x3ff0acab0f3a1b9c + .quad 0x3ff0af8f03834e52 + .quad 0x3ff0b27378110974 + .quad 0x3ff0b5586cf9890f + .quad 0x3ff0b83de2530d11 + .quad 0x3ff0bb23d833d93f + .quad 0x3ff0be0a4eb2353b + .quad 0x3ff0c0f145e46c85 + .quad 0x3ff0c3d8bde0ce7a + .quad 0x3ff0c6c0b6bdae53 + .quad 0x3ff0c9a93091632a + .quad 0x3ff0cc922b7247f7 + .quad 0x3ff0cf7ba776bb94 + .quad 0x3ff0d265a4b520ba + .quad 0x3ff0d5502343de02 + .quad 0x3ff0d83b23395dec + .quad 0x3ff0db26a4ac0ed5 + .quad 0x3ff0de12a7b26300 + .quad 0x3ff0e0ff2c62d096 + .quad 0x3ff0e3ec32d3d1a2 + .quad 0x3ff0e6d9bb1be415 + .quad 0x3ff0e9c7c55189c6 + .quad 0x3ff0ecb6518b4874 + .quad 0x3ff0efa55fdfa9c5 + .quad 0x3ff0f294f0653b45 + .quad 0x3ff0f58503328e6d + .quad 0x3ff0f875985e389b + .quad 0x3ff0fb66affed31b + .quad 0x3ff0fe584a2afb21 + .quad 0x3ff1014a66f951ce + .quad 0x3ff1043d06807c2f + .quad 0x3ff1073028d7233e + .quad 0x3ff10a23ce13f3e2 + .quad 0x3ff10d17f64d9ef1 + .quad 0x3ff1100ca19ad92f + .quad 0x3ff11301d0125b51 + .quad 0x3ff115f781cae1fa + .quad 0x3ff118edb6db2dc1 + .quad 0x3ff11be46f5a032c + .quad 0x3ff11edbab5e2ab6 + .quad 0x3ff121d36afe70c9 + .quad 0x3ff124cbae51a5c8 + .quad 0x3ff127c4756e9e05 + .quad 0x3ff12abdc06c31cc + .quad 0x3ff12db78f613d5b + .quad 0x3ff130b1e264a0e9 + .quad 0x3ff133acb98d40a2 + .quad 0x3ff136a814f204ab + .quad 0x3ff139a3f4a9d922 + .quad 0x3ff13ca058cbae1e + .quad 0x3ff13f9d416e77af + .quad 0x3ff1429aaea92de0 + .quad 0x3ff14598a092ccb7 + .quad 0x3ff1489717425438 + .quad 0x3ff14b9612cec861 + .quad 0x3ff14e95934f312e + .quad 0x3ff1519598da9a9a + .quad 0x3ff154962388149e + .quad 0x3ff15797336eb333 + .quad 0x3ff15a98c8a58e51 + .quad 0x3ff15d9ae343c1f2 + .quad 0x3ff1609d83606e12 + .quad 0x3ff163a0a912b6ac + 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.quad 0x3fffbdba3692d514 + .quad 0x3fffc33ac5677ab8 + .quad 0x3fffc8bc4866e8ad + .quad 0x3fffce3ebfbb7237 + .quad 0x3fffd3c22b8f71f1 + .quad 0x3fffd9468c0d49cc + .quad 0x3fffdecbe15f6314 + .quad 0x3fffe4522bb02e6e + .quad 0x3fffe9d96b2a23d9 + .quad 0x3fffef619ff7c2b3 + .quad 0x3ffff4eaca4391b6 + .quad 0x3ffffa74ea381efc + +/* Range reduction coefficients: + * log(2) inverted = 2^k/ln2 */ +double_vector __dbInvLn2 0x40971547652b82fe + +/* right-shifter value = 3*2^52 */ +double_vector __dbShifter 0x4338000000000000 + +/* log(2) high part = ln2/2^k(52-k-9 hibits) */ +double_vector __dbLn2hi 0x3f462e42fec00000 + +/* log(2) low part = ln2/2^k(52-k-9..104-k-9 lobits) */ +double_vector __dbLn2lo 0x3d5d1cf79abc9e3b + +/* Polynomial coefficients (k=10, deg=3): */ +double_vector __dPC0 0x3ff0000000000000 +double_vector __dPC1 0x3fe0000001ebfbe0 +double_vector __dPC2 0x3fc5555555555556 + +/* Other constants: + * index mask = 2^k-1 */ +double_vector __lIndexMask 0x00000000000003ff + +/* absolute value mask (SP) */ +float_vector __iAbsMask 0x7fffffff + +/* domain range (SP) (>=4086232B) */ +float_vector __iDomainRange 0x4086232a + .type __svml_dexp_data,@object + .size __svml_dexp_data,.-__svml_dexp_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.h new file mode 100644 index 0000000000..70e7660739 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_exp_data.h @@ -0,0 +1,52 @@ +/* Offsets for data table for function exp. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_EXP_DATA_H +#define D_EXP_DATA_H + +#define __dbT 0 +#define __dbInvLn2 8192 +#define __dbShifter 8256 +#define __dbLn2hi 8320 +#define __dbLn2lo 8384 +#define __dPC0 8448 +#define __dPC1 8512 +#define __dPC2 8576 +#define __lIndexMask 8640 +#define __iAbsMask 8704 +#define __iDomainRange 8768 + +.macro double_vector offset value +.if .-__svml_dexp_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +.macro float_vector offset value +.if .-__svml_dexp_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log2_core.S new file mode 100644 index 0000000000..4e2d9b9640 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log2_core.S @@ -0,0 +1,29 @@ +/* Function log vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2v_log) +WRAPPER_IMPL_SSE2 __log_finite +END (_ZGVbN2v_log) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2v_log) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core.S new file mode 100644 index 0000000000..2db872682d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core.S @@ -0,0 +1,29 @@ +/* Function log vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4v_log) +WRAPPER_IMPL_AVX _ZGVbN2v_log +END (_ZGVdN4v_log) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4v_log) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S new file mode 100644 index 0000000000..72cb77a1b7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S @@ -0,0 +1,25 @@ +/* Function log vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4v_log) +WRAPPER_IMPL_AVX _ZGVbN2v_log +END (_ZGVcN4v_log) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log8_core.S new file mode 100644 index 0000000000..d4c4850fdc --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log8_core.S @@ -0,0 +1,25 @@ +/* Function log vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_log) +WRAPPER_IMPL_AVX512 _ZGVdN4v_log +END (_ZGVeN8v_log) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.S new file mode 100644 index 0000000000..b17874100c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.S @@ -0,0 +1,1662 @@ +/* Data for function log. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_d_log_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function log. + The table may contain polynomial, reduction, lookup coefficients + and other constants obtained through different methods + of research and experimental work. */ + .globl __svml_dlog_data +__svml_dlog_data: + +/* Lookup table in high+low parts and 9-bit index for + -log(mRcp), where mRcp is mantissa of 1/x 9-bit accurate reciprocal: */ +.if .-__svml_dlog_data != _Log_HA_table +.err +.endif + .quad 0xc086232bdd7a8300 + .quad 0xbe1ce91eef3fb100 + .quad 0xc086232fdc7ad828 + .quad 0xbe1cefcffda73b6a + .quad 0xc0862333d97d2ba0 + .quad 0xbe1cef406748f1ff + .quad 0xc0862337d48378e0 + .quad 0xbe1cef2a9429925a + .quad 0xc086233bcd8fb878 + .quad 0xbe1cf138d17ebecb + .quad 0xc086233fc4a3e018 + .quad 0xbe1ceff2dbbbb29e + .quad 0xc0862343b9c1e270 + .quad 0xbe1cf1a42aae437b + .quad 0xc0862347acebaf68 + .quad 0xbe1cef3b152048af + .quad 0xc086234b9e2333f0 + .quad 0xbe1cef20e127805e + .quad 0xc086234f8d6a5a30 + .quad 0xbe1cf00ad6052cf4 + .quad 0xc08623537ac30980 + .quad 0xbe1cefc4642ee597 + .quad 0xc0862357662f2660 + .quad 0xbe1cf1f277d36e16 + .quad 0xc086235b4fb092a0 + .quad 0xbe1ceed009e8d8e6 + .quad 0xc086235f37492d28 + .quad 0xbe1cf1e4038cb362 + .quad 0xc08623631cfad250 + .quad 0xbe1cf0b0873b8557 + .quad 0xc086236700c75b98 + .quad 0xbe1cf15bb3227c0b + .quad 0xc086236ae2b09fe0 + .quad 0xbe1cf151ef8ca9ed + .quad 0xc086236ec2b87358 + .quad 0xbe1cefe1dc2cd2ed + .quad 0xc0862372a0e0a780 + .quad 0xbe1cf0d1eec5454f + .quad 0xc08623767d2b0b48 + .quad 0xbe1ceeefd570bbce + .quad 0xc086237a57996af0 + .quad 0xbe1cee99ae91b3a7 + .quad 0xc086237e302d9028 + .quad 0xbe1cf0412830fbd1 + .quad 0xc086238206e94218 + .quad 0xbe1ceee898588610 + .quad 0xc0862385dbce4548 + .quad 0xbe1cee9a1fbcaaea + .quad 0xc0862389aede5bc0 + .quad 0xbe1ceed8e7cc1ad6 + .quad 0xc086238d801b4500 + .quad 0xbe1cf10c8d059da6 + .quad 0xc08623914f86be18 + .quad 0xbe1ceee6c63a8165 + .quad 0xc08623951d228180 + .quad 0xbe1cf0c3592d2ff1 + .quad 0xc0862398e8f04758 + .quad 0xbe1cf0026cc4cb1b + .quad 0xc086239cb2f1c538 + .quad 0xbe1cf15d48d8e670 + .quad 0xc08623a07b28ae60 + .quad 0xbe1cef359363787c + .quad 0xc08623a44196b390 + .quad 0xbe1cefdf1ab2e82c + .quad 0xc08623a8063d8338 + .quad 0xbe1cefe43c02aa84 + .quad 0xc08623abc91ec960 + .quad 0xbe1cf044f5ae35b7 + .quad 0xc08623af8a3c2fb8 + .quad 0xbe1cf0b0b4001e1b + .quad 0xc08623b349975d98 + .quad 0xbe1cf1bae76dfbcf + .quad 0xc08623b70731f810 + .quad 0xbe1cef0a72e13a62 + .quad 0xc08623bac30da1c8 + .quad 0xbe1cf184007d2b6b + .quad 0xc08623be7d2bfb40 + .quad 0xbe1cf16f4b239e98 + .quad 0xc08623c2358ea2a0 + .quad 0xbe1cf0976acada87 + .quad 0xc08623c5ec3733d0 + .quad 0xbe1cf066318a16ff + .quad 0xc08623c9a1274880 + .quad 0xbe1ceffaa7148798 + .quad 0xc08623cd54607820 + .quad 0xbe1cf23ab02e9b6e + .quad 0xc08623d105e45800 + .quad 0xbe1cefdfef7d4fde + .quad 0xc08623d4b5b47b20 + .quad 0xbe1cf17fece44f2b + .quad 0xc08623d863d27270 + .quad 0xbe1cf18f907d0d7c + .quad 0xc08623dc103fccb0 + .quad 0xbe1cee61fe072c98 + .quad 0xc08623dfbafe1668 + .quad 0xbe1cf022dd891e2f + .quad 0xc08623e3640eda20 + .quad 0xbe1ceecc1daf4358 + .quad 0xc08623e70b73a028 + .quad 0xbe1cf0173c4fa380 + .quad 0xc08623eab12deec8 + .quad 0xbe1cf16a2150c2f4 + .quad 0xc08623ee553f4a30 + .quad 0xbe1cf1bf980b1f4b + .quad 0xc08623f1f7a93480 + .quad 0xbe1cef8b731663c2 + .quad 0xc08623f5986d2dc0 + .quad 0xbe1cee9a664d7ef4 + .quad 0xc08623f9378cb3f0 + .quad 0xbe1cf1eda2af6400 + .quad 0xc08623fcd5094320 + .quad 0xbe1cf1923f9d68d7 + .quad 0xc086240070e45548 + .quad 0xbe1cf0747cd3e03a + .quad 0xc08624040b1f6260 + .quad 0xbe1cf22ee855bd6d + .quad 0xc0862407a3bbe078 + .quad 0xbe1cf0d57360c00b + .quad 0xc086240b3abb4398 + .quad 0xbe1ceebc815cd575 + .quad 0xc086240ed01efdd0 + .quad 0xbe1cf03bfb970951 + .quad 0xc086241263e87f50 + .quad 0xbe1cf16e74768529 + .quad 0xc0862415f6193658 + .quad 0xbe1cefec64b8becb + .quad 0xc086241986b28f30 + .quad 0xbe1cf0838d210baa + .quad 0xc086241d15b5f448 + .quad 0xbe1cf0ea86e75b11 + .quad 0xc0862420a324ce28 + .quad 0xbe1cf1708d11d805 + .quad 0xc08624242f008380 + .quad 0xbe1ceea988c5a417 + .quad 0xc0862427b94a7910 + .quad 0xbe1cef166a7bbca5 + .quad 0xc086242b420411d0 + .quad 0xbe1cf0c9d9e86a38 + .quad 0xc086242ec92eaee8 + .quad 0xbe1cef0946455411 + .quad 0xc08624324ecbaf98 + .quad 0xbe1cefea60907739 + .quad 0xc0862435d2dc7160 + .quad 0xbe1cf1ed0934ce42 + .quad 0xc086243955624ff8 + .quad 0xbe1cf191ba746c7d + .quad 0xc086243cd65ea548 + .quad 0xbe1ceeec78cf2a7e + .quad 0xc086244055d2c968 + .quad 0xbe1cef345284c119 + .quad 0xc0862443d3c012b8 + .quad 0xbe1cf24f77355219 + .quad 0xc08624475027d5e8 + .quad 0xbe1cf05bf087e114 + .quad 0xc086244acb0b65d0 + .quad 0xbe1cef3504a32189 + .quad 0xc086244e446c1398 + .quad 0xbe1ceff54b2a406f + .quad 0xc0862451bc4b2eb8 + .quad 0xbe1cf0757d54ed4f + .quad 0xc086245532aa04f0 + .quad 0xbe1cf0c8099fdfd5 + .quad 0xc0862458a789e250 + .quad 0xbe1cf0b173796a31 + .quad 0xc086245c1aec1138 + .quad 0xbe1cf11d8734540d + .quad 0xc086245f8cd1da60 + .quad 0xbe1cf1916a723ceb + .quad 0xc0862462fd3c84d8 + .quad 0xbe1cf19a911e1da7 + .quad 0xc08624666c2d5608 + .quad 0xbe1cf23a9ef72e4f + .quad 0xc0862469d9a591c0 + .quad 0xbe1cef503d947663 + .quad 0xc086246d45a67a18 + .quad 0xbe1cf0fceeb1a0b2 + .quad 0xc0862470b0314fa8 + .quad 0xbe1cf107e27e4fbc + .quad 0xc086247419475160 + .quad 0xbe1cf03dd9922331 + .quad 0xc086247780e9bc98 + .quad 0xbe1cefce1a10e129 + .quad 0xc086247ae719cd18 + .quad 0xbe1ceea47f73c4f6 + .quad 0xc086247e4bd8bd10 + .quad 0xbe1ceec0ac56d100 + .quad 0xc0862481af27c528 + .quad 0xbe1cee8a6593278a + .quad 0xc086248511081c70 + .quad 0xbe1cf2231dd9dec7 + .quad 0xc0862488717af888 + .quad 0xbe1cf0b4b8ed7da8 + .quad 0xc086248bd0818d68 + .quad 0xbe1cf1bd8d835002 + .quad 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0xbe1cf143efdd1fd0 + .quad 0xc0862882c24faff8 + .quad 0xbe1cee9896d016da + .quad 0xc0862884cf630e38 + .quad 0xbe1cf2186072f2cc + .quad 0xc0862886dbefeff0 + .quad 0xbe1cef9217633d34 + .quad 0xc0862888e7f699e0 + .quad 0xbe1cf05603549486 + .quad 0xc086288af37750b0 + .quad 0xbe1cef50fff513d3 + .quad 0xc086288cfe7258c0 + .quad 0xbe1cf127713b32d0 + .quad 0xc086288f08e7f650 + .quad 0xbe1cf05015520f3d + .quad 0xc086289112d86d58 + .quad 0xbe1cf12eb458b26f + .quad 0xc08628931c4401a8 + .quad 0xbe1cf22eae2887ed + .quad 0xc0862895252af6e0 + .quad 0xbe1cefdd6656dd2d + .quad 0xc08628972d8d9058 + .quad 0xbe1cf1048ea4e646 + .quad 0xc0862899356c1150 + .quad 0xbe1ceec4501167e9 + .quad 0xc086289b3cc6bcb8 + .quad 0xbe1cf0ad52becc3f + .quad 0xc086289d439dd568 + .quad 0xbe1cf0daa4e00e35 + .quad 0xc086289f49f19df8 + .quad 0xbe1cf00b80de8d6a + .quad 0xc08628a14fc258c8 + .quad 0xbe1cf1bcf2ea8464 + .quad 0xc08628a355104818 + .quad 0xbe1cf0435e2782b0 + .quad 0xc08628a559dbade0 + .quad 0xbe1cf0e3e1a5f56c + .quad 0xc08628a75e24cbf8 + .quad 0xbe1cefed9d5a721d + .quad 0xc08628a961ebe3f8 + .quad 0xbe1cf0d2d74321e2 + .quad 0xc08628ab65313750 + .quad 0xbe1cf24200eb55e9 + .quad 0xc08628ad67f50740 + .quad 0xbe1cf23e9d7cf979 + .quad 0xc08628af6a3794d0 + .quad 0xbe1cf23a088f421c + .quad 0xc08628b16bf920e0 + .quad 0xbe1cef2c1de1ab32 + .quad 0xc08628b36d39ec08 + .quad 0xbe1cf1abc231f7b2 + .quad 0xc08628b56dfa36d0 + .quad 0xbe1cf2074d5ba303 + .quad 0xc08628b76e3a4180 + .quad 0xbe1cf05cd5eed880 + .rept 48 + .byte 0 + .endr + +/* Lookup table with 9-bit index for + -log(mRcp), where mRcp is mantissa of 1/x 9-bit accurate reciprocal: + */ +.if .-__svml_dlog_data != _Log_LA_table +.err +.endif + .quad 0x8000000000000000 + .quad 0xbf5ff802a9ab10e6 + .quad 0xbf6ff00aa2b10bc0 + .quad 0xbf77ee11ebd82e94 + .quad 0xbf7fe02a6b106789 + .quad 0xbf83e7295d25a7d9 + .quad 0xbf87dc475f810a77 + .quad 0xbf8bcf712c74384c + .quad 0xbf8fc0a8b0fc03e4 + .quad 0xbf91d7f7eb9eebe7 + .quad 0xbf93cea44346a575 + .quad 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0xbfc3a8eb2d31a376 + .quad 0xbfc3dfc2b0ecc62a + .quad 0xbfc41682bf727bc0 + .quad 0xbfc44d2b6ccb7d1e + .quad 0xbfc483bccce6e3dd + .quad 0xbfc4ba36f39a55e5 + .quad 0xbfc4f099f4a230b2 + .quad 0xbfc526e5e3a1b438 + .quad 0xbfc55d1ad4232d6f + .quad 0xbfc59338d9982086 + .quad 0xbfc5c940075972b9 + .quad 0xbfc5ff3070a793d4 + .quad 0xbfc6350a28aaa758 + .quad 0xbfc66acd4272ad51 + .quad 0xbfc6a079d0f7aad2 + .quad 0xbfc6d60fe719d21d + .quad 0xbfc70b8f97a1aa75 + .quad 0xbfc740f8f54037a5 + .quad 0xbfc7764c128f2127 + .quad 0xbfc7ab890210d909 + .quad 0xbfc7e0afd630c274 + .quad 0xbfc815c0a14357eb + .quad 0xbfc84abb75865139 + .quad 0xbfc87fa06520c911 + .quad 0xbfc8b46f8223625b + .quad 0xbfc8e928de886d41 + .quad 0xbfc91dcc8c340bde + .quad 0xbfc9525a9cf456b4 + .quad 0xbfc986d3228180ca + .quad 0xbfc9bb362e7dfb83 + .quad 0xbfc9ef83d2769a34 + .quad 0xbfca23bc1fe2b563 + .quad 0xbfca57df28244dcd + .quad 0xbfca8becfc882f19 + .quad 0xbfcabfe5ae46124c + .quad 0xbfcaf3c94e80bff3 + .quad 0xbfcb2797ee46320c + .quad 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0x3f9432a925980cc1 + .quad 0x3f932db0ea132e22 + .quad 0x3f9228fb1fea2e28 + .quad 0x3f912487a5507f70 + .quad 0x3f90205658935847 + .quad 0x3f8e38ce3033310c + .quad 0x3f8c317384c75f06 + .quad 0x3f8a2a9c6c170462 + .quad 0x3f882448a388a2aa + .quad 0x3f861e77e8b53fc6 + .quad 0x3f841929f96832f0 + .quad 0x3f82145e939ef1e9 + .quad 0x3f8010157588de71 + .quad 0x3f7c189cbb0e27fb + .quad 0x3f78121214586b54 + .quad 0x3f740c8a747878e2 + .quad 0x3f70080559588b35 + .quad 0x3f680904828985c0 + .quad 0x3f60040155d5889e + .quad 0x3f50020055655889 + .quad 0x0000000000000000 + .rept 56 + .byte 0 + .endr + +/* Polynomial coefficients: */ +double_vector _poly_coeff_1 0x3fc9999cacdb4d0a +double_vector _poly_coeff_2 0xbfd0000148058ee1 +double_vector _poly_coeff_3 0x3fd55555555543c5 +double_vector _poly_coeff_4 0xbfdffffffffff81f + +/* Exponent mask */ +double_vector _ExpMask 0x000fffffffffffff + +/* 2^10 */ +double_vector _Two10 0x3f50000000000000 + +/* Minimum normal number */ +double_vector _MinNorm 0x0010000000000000 + +/* Maximum normal number */ +double_vector _MaxNorm 0x7fefffffffffffff + +/* Half of mantissa mask */ +double_vector _HalfMask 0xfffffffffc000000 + +/* 1.0 */ +double_vector _One 0x3ff0000000000000 + +/* log(2) high part */ +double_vector _L2H 0x3fe62e42fefa0000 + +/* log(2) low part */ +double_vector _L2L 0x3d7cf79abc9e0000 + +/* Work range threshold = 724 */ +double_vector _Threshold 0x4086a00000000000 + +/* Bias */ +double_vector _Bias 0x408ff80000000000 + +/* Bias (-1 bit) */ +double_vector _Bias1 0x408ff00000000000 + +/* log(2) */ +double_vector _L2 0x3fe62e42fefa39ef + +/* General purpose constants: + DP infinities, +/- */ +.if .-__svml_dlog_data != _dInfs +.err +.endif + .quad 0x7ff0000000000000 + .quad 0xfff0000000000000 + .rept 48 + .byte 0 + .endr + +/* DP 1.0, +/- */ +.if .-__svml_dlog_data != _dOnes +.err +.endif + .quad 0x3ff0000000000000 + .quad 0xbff0000000000000 + .rept 48 + .byte 0 + .endr + +/* DP 0.0, +/- */ +.if .-__svml_dlog_data != _dZeros +.err +.endif + .quad 0x0000000000000000 + .quad 0x8000000000000000 + .rept 48 + .byte 0 + .endr + .type __svml_dlog_data,@object + .size __svml_dlog_data,.-__svml_dlog_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.h new file mode 100644 index 0000000000..84d65db95d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_log_data.h @@ -0,0 +1,54 @@ +/* Offsets for data table for function log. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_LOG_DATA_H +#define D_LOG_DATA_H + +#define _LogRcp_lookup -4218816 +#define _Log_HA_table 0 +#define _Log_LA_table 8256 +#define _poly_coeff_1 12416 +#define _poly_coeff_2 12480 +#define _poly_coeff_3 12544 +#define _poly_coeff_4 12608 +#define _ExpMask 12672 +#define _Two10 12736 +#define _MinNorm 12800 +#define _MaxNorm 12864 +#define _HalfMask 12928 +#define _One 12992 +#define _L2H 13056 +#define _L2L 13120 +#define _Threshold 13184 +#define _Bias 13248 +#define _Bias1 13312 +#define _L2 13376 +#define _dInfs 13440 +#define _dOnes 13504 +#define _dZeros 13568 + +.macro double_vector offset value +.if .-__svml_dlog_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow2_core.S new file mode 100644 index 0000000000..ccdb592135 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow2_core.S @@ -0,0 +1,29 @@ +/* Function pow vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2vv_pow) +WRAPPER_IMPL_SSE2_ff __pow_finite +END (_ZGVbN2vv_pow) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2vv_pow) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core.S new file mode 100644 index 0000000000..30ae0f5a2f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core.S @@ -0,0 +1,29 @@ +/* Function pow vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4vv_pow) +WRAPPER_IMPL_AVX_ff _ZGVbN2vv_pow +END (_ZGVdN4vv_pow) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4vv_pow) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S new file mode 100644 index 0000000000..bcea225c4d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S @@ -0,0 +1,25 @@ +/* Function pow vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4vv_pow) +WRAPPER_IMPL_AVX_ff _ZGVbN2vv_pow +END (_ZGVcN4vv_pow) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow8_core.S new file mode 100644 index 0000000000..06b3a81124 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow8_core.S @@ -0,0 +1,25 @@ +/* Function pow vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8vv_pow) +WRAPPER_IMPL_AVX512_ff _ZGVdN4vv_pow +END (_ZGVeN8vv_pow) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.S new file mode 100644 index 0000000000..2f05f7becb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.S @@ -0,0 +1,4863 @@ +/* Data for function pow. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_d_pow_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function pow. + The table may contain polynomial, reduction, lookup coefficients and + other coefficients obtained through different methods of research and + experimental work. */ + + .globl __svml_dpow_data +__svml_dpow_data: + +/* Lookup log(2) table (for HSW): */ +.if .-__svml_dpow_data != _hsw_log2_table +.err +.endif + .quad 0xc08ff00000000000 + .quad 0x0000000000000000 + .quad 0xc08ff005c3e0ffc2 + .quad 0xbd33ab2631d4676d + .quad 0xc08ff00b84e236bc + .quad 0xbd4563ba56cde925 + .quad 0xc08ff01143068126 + .quad 0x3d11790209e88471 + .quad 0xc08ff016fe50b6ee + .quad 0xbd408517f8e37b00 + .quad 0xc08ff01cb6c3abd0 + .quad 0xbd44558b51cada94 + .quad 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0xc08ff74776066d30 + .quad 0xbd3f86493917b407 + .quad 0xc08ff74a87e1ecfe + .quad 0xbd10be3a57487484 + .quad 0xc08ff74d98ec9fcc + .quad 0xbd2d5297837adb4b + .quad 0xc08ff750a926f472 + .quad 0xbd43ae4d308b33a5 + .quad 0xc08ff753b8915972 + .quad 0x3d2d54d244e2aaee + .quad 0xc08ff756c72c3cee + .quad 0xbd35f097b0fe80a3 + .quad 0xc08ff759d4f80cba + .quad 0xbd3077f1f5f0cc83 + .quad 0xc08ff75ce1f5364e + .quad 0x3d19367107b8e917 + .quad 0xc08ff75fee2426ca + .quad 0xbd33623c81400bcf + .quad 0xc08ff762f9854afc + .quad 0xbd33b55bcb161bac + .quad 0xc08ff76604190f5a + .quad 0x3d2eb3c3bf914b9c + .quad 0xc08ff7690ddfe000 + .quad 0xbd45a6a7f43f6ec0 + .quad 0xc08ff76c16da28be + .quad 0xbd3b253dff5e0495 + .quad 0xc08ff76f1f085508 + .quad 0x3d1b08127eec65d2 + .quad 0xc08ff772266acffc + .quad 0xbd45b1799ceaeb51 + .quad 0xc08ff7752d02046c + .quad 0xbd2e63bd0fcda210 + .quad 0xc08ff77832ce5cce + .quad 0xbd148cd0a7bb24b2 + .quad 0xc08ff77b37d04348 + .quad 0x3d11ef56fa3d37b4 + .quad 0xc08ff77e3c0821ac + .quad 0x3d1a768216f872eb + .quad 0xc08ff7813f766178 + .quad 0xbd44b4a15a96316e + .quad 0xc08ff784421b6bdc + .quad 0xbd4258a7b2336919 + .quad 0xc08ff78743f7a9b2 + .quad 0x3d03f659faac5a20 + .quad 0xc08ff78a450b8380 + .quad 0xbd2401fbaaa67e3c + .quad 0xc08ff78d4557617e + .quad 0xbd476fa81cf6a494 + .quad 0xc08ff79044dbab94 + .quad 0xbd44f46b93eece0a + .quad 0xc08ff7934398c956 + .quad 0xbd3c91f073716495 + .quad 0xc08ff796418f2208 + .quad 0xbd3672b0c88d4dd6 + .quad 0xc08ff7993ebf1c9e + .quad 0xbd3fb554647678d1 + .quad 0xc08ff79c3b291fbe + .quad 0xbd0bb98afdf33295 + .quad 0xc08ff79f36cd91ba + .quad 0xbd3a1c40753a869f + .quad 0xc08ff7a231acd89a + .quad 0xbd3395510d1e3f81 + .quad 0xc08ff7a52bc75a14 + .quad 0xbcf98fd2dca61c14 + .quad 0xc08ff7a8251d7b8e + .quad 0xbd40e7b8e7574248 + .quad 0xc08ff7ab1dafa224 + .quad 0xbd43f88ff2576e98 + .quad 0xc08ff7ae157e32a2 + .quad 0xbd1f61a96b8ce776 + .quad 0xc08ff7b10c899184 + .quad 0x3cde66be73b9da04 + .quad 0xc08ff7b402d222fa + .quad 0xbd408d5c3f1d5c0d + .quad 0xc08ff7b6f8584aea + .quad 0xbd3cbebea25ecd9e + .quad 0xc08ff7b9ed1c6cea + .quad 0xbd2507d6dc1f27ef + .quad 0xc08ff7bce11eec44 + .quad 0x3d2794d4c6c8f327 + .quad 0xc08ff7bfd4602bf4 + .quad 0xbd3f1e32799da52d + .quad 0xc08ff7c2c6e08eb0 + .quad 0xbd35c01818adf4af + .quad 0xc08ff7c5b8a076de + .quad 0x3d2cfc4de6d73dea + .quad 0xc08ff7c8a9a04696 + .quad 0xbd4227264a17d460 + .quad 0xc08ff7cb99e05fae + .quad 0xbd0142b08bb672e8 + .quad 0xc08ff7ce896123a8 + .quad 0xbd2564fcfaea5fb3 + .quad 0xc08ff7d17822f3c2 + .quad 0x3d2aab1b2a41b090 + .quad 0xc08ff7d4662630ea + .quad 0xbd46ac3b83ef359a + .quad 0xc08ff7d7536b3bce + .quad 0x3d241a2f220ccf53 + .quad 0xc08ff7da3ff274c6 + .quad 0xbd38f5d37680fd7c + .quad 0xc08ff7dd2bbc3bec + .quad 0x3d048a179268271d + .quad 0xc08ff7e016c8f108 + .quad 0xbd471e548b69f12a + .quad 0xc08ff7e30118f3a2 + .quad 0xbd41a23946dfa58c + .quad 0xc08ff7e5eaaca2f4 + .quad 0xbd25330d5605f2a6 + .quad 0xc08ff7e8d3845df0 + .quad 0xbd319b14945cf6ba + .quad 0xc08ff7ebbba08342 + .quad 0xbd4702e1863f7c92 + .quad 0xc08ff7eea3017150 + .quad 0xbd437cfeba9ff979 + .quad 0xc08ff7f189a78636 + .quad 0xbd3df6e958e938b0 + .quad 0xc08ff7f46f931fca + .quad 0xbd37ca15910e7069 + .quad 0xc08ff7f754c49b9c + .quad 0xbd15cfd00d77e6ec + .quad 0xc08ff7fa393c56f4 + .quad 0xbd2a025d9e2442e6 + .quad 0xc08ff7fd1cfaaed6 + .quad 0xbd3258e9a821b7cc + .quad 0xc08ff80000000000 + .quad 0x0000000000000000 + .rept 48 + .byte 0 + .endr + +/* Lookup exp(2) table (for HSW): */ +.if .-__svml_dpow_data != _hsw_dTe +.err +.endif + .quad 0x3ff0000000000000 + .quad 0x3ff00b1afa5abcbf + .quad 0x3ff0163da9fb3335 + .quad 0x3ff02168143b0281 + .quad 0x3ff02c9a3e778061 + .quad 0x3ff037d42e11bbcc + .quad 0x3ff04315e86e7f85 + .quad 0x3ff04e5f72f654b1 + .quad 0x3ff059b0d3158574 + .quad 0x3ff0650a0e3c1f89 + .quad 0x3ff0706b29ddf6de + .quad 0x3ff07bd42b72a836 + .quad 0x3ff0874518759bc8 + .quad 0x3ff092bdf66607e0 + .quad 0x3ff09e3ecac6f383 + .quad 0x3ff0a9c79b1f3919 + .quad 0x3ff0b5586cf9890f + .quad 0x3ff0c0f145e46c85 + .quad 0x3ff0cc922b7247f7 + .quad 0x3ff0d83b23395dec + .quad 0x3ff0e3ec32d3d1a2 + .quad 0x3ff0efa55fdfa9c5 + .quad 0x3ff0fb66affed31b + .quad 0x3ff1073028d7233e + .quad 0x3ff11301d0125b51 + .quad 0x3ff11edbab5e2ab6 + .quad 0x3ff12abdc06c31cc + .quad 0x3ff136a814f204ab + .quad 0x3ff1429aaea92de0 + .quad 0x3ff14e95934f312e + .quad 0x3ff15a98c8a58e51 + .quad 0x3ff166a45471c3c2 + .quad 0x3ff172b83c7d517b + .quad 0x3ff17ed48695bbc0 + .quad 0x3ff18af9388c8dea + .quad 0x3ff1972658375d2f + .quad 0x3ff1a35beb6fcb75 + .quad 0x3ff1af99f8138a1c + .quad 0x3ff1bbe084045cd4 + .quad 0x3ff1c82f95281c6b + .quad 0x3ff1d4873168b9aa + .quad 0x3ff1e0e75eb44027 + .quad 0x3ff1ed5022fcd91d + .quad 0x3ff1f9c18438ce4d + .quad 0x3ff2063b88628cd6 + .quad 0x3ff212be3578a819 + .quad 0x3ff21f49917ddc96 + .quad 0x3ff22bdda27912d1 + .quad 0x3ff2387a6e756238 + .quad 0x3ff2451ffb82140a + .quad 0x3ff251ce4fb2a63f + .quad 0x3ff25e85711ece75 + .quad 0x3ff26b4565e27cdd + .quad 0x3ff2780e341ddf29 + .quad 0x3ff284dfe1f56381 + .quad 0x3ff291ba7591bb70 + .quad 0x3ff29e9df51fdee1 + .quad 0x3ff2ab8a66d10f13 + .quad 0x3ff2b87fd0dad990 + .quad 0x3ff2c57e39771b2f + .quad 0x3ff2d285a6e4030b + .quad 0x3ff2df961f641589 + .quad 0x3ff2ecafa93e2f56 + .quad 0x3ff2f9d24abd886b + .quad 0x3ff306fe0a31b715 + .quad 0x3ff31432edeeb2fd + .quad 0x3ff32170fc4cd831 + .quad 0x3ff32eb83ba8ea32 + .quad 0x3ff33c08b26416ff + .quad 0x3ff3496266e3fa2d + .quad 0x3ff356c55f929ff1 + .quad 0x3ff36431a2de883b + .quad 0x3ff371a7373aa9cb + .quad 0x3ff37f26231e754a + .quad 0x3ff38cae6d05d866 + .quad 0x3ff39a401b7140ef + .quad 0x3ff3a7db34e59ff7 + .quad 0x3ff3b57fbfec6cf4 + .quad 0x3ff3c32dc313a8e5 + .quad 0x3ff3d0e544ede173 + .quad 0x3ff3dea64c123422 + .quad 0x3ff3ec70df1c5175 + .quad 0x3ff3fa4504ac801c + .quad 0x3ff40822c367a024 + .quad 0x3ff4160a21f72e2a + .quad 0x3ff423fb2709468a + .quad 0x3ff431f5d950a897 + .quad 0x3ff43ffa3f84b9d4 + .quad 0x3ff44e086061892d + .quad 0x3ff45c2042a7d232 + .quad 0x3ff46a41ed1d0057 + .quad 0x3ff4786d668b3237 + .quad 0x3ff486a2b5c13cd0 + .quad 0x3ff494e1e192aed2 + .quad 0x3ff4a32af0d7d3de + .quad 0x3ff4b17dea6db7d7 + .quad 0x3ff4bfdad5362a27 + .quad 0x3ff4ce41b817c114 + .quad 0x3ff4dcb299fddd0d + .quad 0x3ff4eb2d81d8abff + .quad 0x3ff4f9b2769d2ca7 + .quad 0x3ff508417f4531ee + .quad 0x3ff516daa2cf6642 + .quad 0x3ff5257de83f4eef + .quad 0x3ff5342b569d4f82 + .quad 0x3ff542e2f4f6ad27 + .quad 0x3ff551a4ca5d920f + .quad 0x3ff56070dde910d2 + .quad 0x3ff56f4736b527da + .quad 0x3ff57e27dbe2c4cf + .quad 0x3ff58d12d497c7fd + .quad 0x3ff59c0827ff07cc + .quad 0x3ff5ab07dd485429 + .quad 0x3ff5ba11fba87a03 + .quad 0x3ff5c9268a5946b7 + .quad 0x3ff5d84590998b93 + .quad 0x3ff5e76f15ad2148 + .quad 0x3ff5f6a320dceb71 + .quad 0x3ff605e1b976dc09 + .quad 0x3ff6152ae6cdf6f4 + .quad 0x3ff6247eb03a5585 + .quad 0x3ff633dd1d1929fd + .quad 0x3ff6434634ccc320 + .quad 0x3ff652b9febc8fb7 + .quad 0x3ff6623882552225 + .quad 0x3ff671c1c70833f6 + .quad 0x3ff68155d44ca973 + .quad 0x3ff690f4b19e9538 + .quad 0x3ff6a09e667f3bcd + .quad 0x3ff6b052fa75173e + .quad 0x3ff6c012750bdabf + .quad 0x3ff6cfdcddd47645 + .quad 0x3ff6dfb23c651a2f + .quad 0x3ff6ef9298593ae5 + .quad 0x3ff6ff7df9519484 + .quad 0x3ff70f7466f42e87 + .quad 0x3ff71f75e8ec5f74 + .quad 0x3ff72f8286ead08a + .quad 0x3ff73f9a48a58174 + .quad 0x3ff74fbd35d7cbfd + .quad 0x3ff75feb564267c9 + .quad 0x3ff77024b1ab6e09 + .quad 0x3ff780694fde5d3f + .quad 0x3ff790b938ac1cf6 + .quad 0x3ff7a11473eb0187 + .quad 0x3ff7b17b0976cfdb + .quad 0x3ff7c1ed0130c132 + .quad 0x3ff7d26a62ff86f0 + .quad 0x3ff7e2f336cf4e62 + .quad 0x3ff7f3878491c491 + .quad 0x3ff80427543e1a12 + .quad 0x3ff814d2add106d9 + .quad 0x3ff82589994cce13 + .quad 0x3ff8364c1eb941f7 + .quad 0x3ff8471a4623c7ad + .quad 0x3ff857f4179f5b21 + .quad 0x3ff868d99b4492ed + .quad 0x3ff879cad931a436 + .quad 0x3ff88ac7d98a6699 + .quad 0x3ff89bd0a478580f + .quad 0x3ff8ace5422aa0db + .quad 0x3ff8be05bad61778 + .quad 0x3ff8cf3216b5448c + .quad 0x3ff8e06a5e0866d9 + .quad 0x3ff8f1ae99157736 + .quad 0x3ff902fed0282c8a + .quad 0x3ff9145b0b91ffc6 + .quad 0x3ff925c353aa2fe2 + .quad 0x3ff93737b0cdc5e5 + .quad 0x3ff948b82b5f98e5 + .quad 0x3ff95a44cbc8520f + .quad 0x3ff96bdd9a7670b3 + .quad 0x3ff97d829fde4e50 + .quad 0x3ff98f33e47a22a2 + .quad 0x3ff9a0f170ca07ba + .quad 0x3ff9b2bb4d53fe0d + .quad 0x3ff9c49182a3f090 + .quad 0x3ff9d674194bb8d5 + .quad 0x3ff9e86319e32323 + .quad 0x3ff9fa5e8d07f29e + .quad 0x3ffa0c667b5de565 + .quad 0x3ffa1e7aed8eb8bb + .quad 0x3ffa309bec4a2d33 + .quad 0x3ffa42c980460ad8 + .quad 0x3ffa5503b23e255d + .quad 0x3ffa674a8af46052 + .quad 0x3ffa799e1330b358 + .quad 0x3ffa8bfe53c12e59 + .quad 0x3ffa9e6b5579fdbf + .quad 0x3ffab0e521356eba + .quad 0x3ffac36bbfd3f37a + .quad 0x3ffad5ff3a3c2774 + .quad 0x3ffae89f995ad3ad + .quad 0x3ffafb4ce622f2ff + .quad 0x3ffb0e07298db666 + .quad 0x3ffb20ce6c9a8952 + .quad 0x3ffb33a2b84f15fb + .quad 0x3ffb468415b749b1 + .quad 0x3ffb59728de5593a + .quad 0x3ffb6c6e29f1c52a + .quad 0x3ffb7f76f2fb5e47 + .quad 0x3ffb928cf22749e4 + .quad 0x3ffba5b030a1064a + .quad 0x3ffbb8e0b79a6f1f + .quad 0x3ffbcc1e904bc1d2 + .quad 0x3ffbdf69c3f3a207 + .quad 0x3ffbf2c25bd71e09 + .quad 0x3ffc06286141b33d + .quad 0x3ffc199bdd85529c + .quad 0x3ffc2d1cd9fa652c + .quad 0x3ffc40ab5fffd07a + .quad 0x3ffc544778fafb22 + .quad 0x3ffc67f12e57d14b + .quad 0x3ffc7ba88988c933 + .quad 0x3ffc8f6d9406e7b5 + .quad 0x3ffca3405751c4db + .quad 0x3ffcb720dcef9069 + .quad 0x3ffccb0f2e6d1675 + .quad 0x3ffcdf0b555dc3fa + .quad 0x3ffcf3155b5bab74 + .quad 0x3ffd072d4a07897c + .quad 0x3ffd1b532b08c968 + .quad 0x3ffd2f87080d89f2 + .quad 0x3ffd43c8eacaa1d6 + .quad 0x3ffd5818dcfba487 + .quad 0x3ffd6c76e862e6d3 + .quad 0x3ffd80e316c98398 + .quad 0x3ffd955d71ff6075 + .quad 0x3ffda9e603db3285 + .quad 0x3ffdbe7cd63a8315 + .quad 0x3ffdd321f301b460 + .quad 0x3ffde7d5641c0658 + .quad 0x3ffdfc97337b9b5f + .quad 0x3ffe11676b197d17 + .quad 0x3ffe264614f5a129 + .quad 0x3ffe3b333b16ee12 + .quad 0x3ffe502ee78b3ff6 + .quad 0x3ffe653924676d76 + .quad 0x3ffe7a51fbc74c83 + .quad 0x3ffe8f7977cdb740 + .quad 0x3ffea4afa2a490da + .quad 0x3ffeb9f4867cca6e + .quad 0x3ffecf482d8e67f1 + .quad 0x3ffee4aaa2188510 + .quad 0x3ffefa1bee615a27 + .quad 0x3fff0f9c1cb6412a + .quad 0x3fff252b376bba97 + .quad 0x3fff3ac948dd7274 + .quad 0x3fff50765b6e4540 + .quad 0x3fff6632798844f8 + .quad 0x3fff7bfdad9cbe14 + .quad 0x3fff91d802243c89 + .quad 0x3fffa7c1819e90d8 + .quad 0x3fffbdba3692d514 + .quad 0x3fffd3c22b8f71f1 + .quad 0x3fffe9d96b2a23d9 + +/* General purpose constants: + * hsw_dMantMask */ +double_vector _hsw_dMantMask 0x000fffffffffffff + +/* hsw_dOne */ +double_vector _hsw_dOne 0x3ff0000000000000 + +/* hsw_dCvtMask */ +double_vector _hsw_dCvtMask 0x4338000000000000 + +/* hsw_dMinNorm */ +double_vector _hsw_dMinNorm 0x0010000000000000 + +/* hsw_dMaxNorm */ +double_vector _hsw_dMaxNorm 0x7fefffffffffffff + +/* hsw_lRndBit */ +double_vector _hsw_lRndBit 0x0000040000000000 + +/* hsw_lRndMask */ +double_vector _hsw_lRndMask 0xfffff80000000000 + +/* Log polynomial: + * hsw_dc6 */ +double_vector _hsw_dc6 0xbfcec1cfbbc5c90c + +/* hsw_dc5 */ +double_vector _hsw_dc5 0x3fd2776da3d26e6a + +/* hsw_dc4 */ +double_vector _hsw_dc4 0xbfd71547655d37e0 + +/* hsw_dc3 */ +double_vector _hsw_dc3 0x3fdec709dc39fb02 + +/* hsw_dc1 */ +double_vector _hsw_dc1 0x3c777a3a2c24613d + +/* hsw_dc1h */ +double_vector _hsw_dc1h 0x3ff71547652b82fe + +/* hsw_dc2 */ +double_vector _hsw_dc2 0xbfe71547652b82fe + +/* Additional constants: + * hsw_AbsMask */ +double_vector _hsw_dAbsMask 0x7fffffffffffffff + +/* hsw_dDomainRange */ +double_vector _hsw_dDomainRange 0x408fec0000000000 + +/* hsw_dShifter */ +double_vector _hsw_dShifter 0x42b800000003ff00 + +/* hsw_dIndexMask */ +double_vector _hsw_dIndexMask 0x00000000000007f8 + +/* Exp polynomial: + * hsw_dce4 */ +double_vector _hsw_dce4 0x3f83b2ab930f15f9 + +/* hsw_dce3 */ +double_vector _hsw_dce3 0x3fac6b090da1e0a9 + +/* hsw_dce2 */ +double_vector _hsw_dce2 0x3fcebfbdff82c54d + +/* hsw_dce1 */ +double_vector _hsw_dce1 0x3fe62e42fefa39b9 + +/* Reciprocal lookup table for log part (non HSW): */ +.if .-__svml_dpow_data != _rcp_t1 +.err +.endif + .quad 0x3ff7154740000000 + .quad 0x3ff70f8340000000 + .quad 0x3ff709c240000000 + .quad 0x3ff7040440000000 + .quad 0x3ff6fe4900000000 + .quad 0x3ff6f89080000000 + .quad 0x3ff6f2db00000000 + .quad 0x3ff6ed2840000000 + .quad 0x3ff6e77840000000 + .quad 0x3ff6e1cb40000000 + .quad 0x3ff6dc2100000000 + .quad 0x3ff6d67980000000 + .quad 0x3ff6d0d4c0000000 + .quad 0x3ff6cb32c0000000 + .quad 0x3ff6c593c0000000 + .quad 0x3ff6bff780000000 + .quad 0x3ff6ba5dc0000000 + .quad 0x3ff6b4c700000000 + .quad 0x3ff6af32c0000000 + .quad 0x3ff6a9a180000000 + .quad 0x3ff6a41300000000 + .quad 0x3ff69e8700000000 + .quad 0x3ff698fdc0000000 + .quad 0x3ff6937740000000 + .quad 0x3ff68df380000000 + .quad 0x3ff6887280000000 + .quad 0x3ff682f400000000 + .quad 0x3ff67d7840000000 + .quad 0x3ff677ff40000000 + .quad 0x3ff67288c0000000 + .quad 0x3ff66d1540000000 + .quad 0x3ff667a400000000 + .quad 0x3ff6623580000000 + .quad 0x3ff65cc9c0000000 + .quad 0x3ff6576080000000 + .quad 0x3ff651fa00000000 + .quad 0x3ff64c9600000000 + .quad 0x3ff6473480000000 + .quad 0x3ff641d5c0000000 + .quad 0x3ff63c7980000000 + .quad 0x3ff6372000000000 + .quad 0x3ff631c900000000 + .quad 0x3ff62c7480000000 + .quad 0x3ff6272280000000 + .quad 0x3ff621d340000000 + .quad 0x3ff61c8640000000 + .quad 0x3ff6173c00000000 + .quad 0x3ff611f440000000 + .quad 0x3ff60caf00000000 + .quad 0x3ff6076c40000000 + .quad 0x3ff6022c00000000 + .quad 0x3ff5fcee80000000 + .quad 0x3ff5f7b340000000 + .quad 0x3ff5f27a80000000 + .quad 0x3ff5ed4440000000 + .quad 0x3ff5e81040000000 + .quad 0x3ff5e2df00000000 + .quad 0x3ff5ddb040000000 + .quad 0x3ff5d883c0000000 + .quad 0x3ff5d359c0000000 + .quad 0x3ff5ce3240000000 + .quad 0x3ff5c90d40000000 + .quad 0x3ff5c3ea80000000 + .quad 0x3ff5beca40000000 + .quad 0x3ff5b9ac80000000 + .quad 0x3ff5b49100000000 + .quad 0x3ff5af7800000000 + .quad 0x3ff5aa6180000000 + .quad 0x3ff5a54d40000000 + .quad 0x3ff5a03b40000000 + .quad 0x3ff59b2bc0000000 + .quad 0x3ff5961ec0000000 + .quad 0x3ff59113c0000000 + .quad 0x3ff58c0b80000000 + .quad 0x3ff5870540000000 + .quad 0x3ff58201c0000000 + .quad 0x3ff57d0040000000 + .quad 0x3ff5780140000000 + .quad 0x3ff5730480000000 + .quad 0x3ff56e0a00000000 + .quad 0x3ff56911c0000000 + .quad 0x3ff5641c00000000 + .quad 0x3ff55f2880000000 + .quad 0x3ff55a3740000000 + .quad 0x3ff5554840000000 + .quad 0x3ff5505bc0000000 + .quad 0x3ff54b7140000000 + .quad 0x3ff5468900000000 + .quad 0x3ff541a340000000 + .quad 0x3ff53cbf80000000 + .quad 0x3ff537de40000000 + .quad 0x3ff532ff00000000 + .quad 0x3ff52e2240000000 + .quad 0x3ff5294780000000 + .quad 0x3ff5246f00000000 + .quad 0x3ff51f98c0000000 + .quad 0x3ff51ac4c0000000 + .quad 0x3ff515f300000000 + .quad 0x3ff5112340000000 + .quad 0x3ff50c5600000000 + .quad 0x3ff5078ac0000000 + .quad 0x3ff502c1c0000000 + .quad 0x3ff4fdfac0000000 + .quad 0x3ff4f93600000000 + .quad 0x3ff4f47380000000 + .quad 0x3ff4efb340000000 + .quad 0x3ff4eaf500000000 + .quad 0x3ff4e638c0000000 + .quad 0x3ff4e17ec0000000 + .quad 0x3ff4dcc700000000 + .quad 0x3ff4d81180000000 + .quad 0x3ff4d35dc0000000 + .quad 0x3ff4ceac80000000 + .quad 0x3ff4c9fd00000000 + .quad 0x3ff4c54fc0000000 + .quad 0x3ff4c0a4c0000000 + .quad 0x3ff4bbfbc0000000 + .quad 0x3ff4b754c0000000 + .quad 0x3ff4b2b000000000 + .quad 0x3ff4ae0d40000000 + .quad 0x3ff4a96c80000000 + .quad 0x3ff4a4ce00000000 + .quad 0x3ff4a03140000000 + .quad 0x3ff49b9700000000 + .quad 0x3ff496fe80000000 + .quad 0x3ff4926800000000 + .quad 0x3ff48dd3c0000000 + .quad 0x3ff4894180000000 + .quad 0x3ff484b100000000 + .quad 0x3ff48022c0000000 + .quad 0x3ff47b96c0000000 + .quad 0x3ff4770c80000000 + .quad 0x3ff4728440000000 + .quad 0x3ff46dfe00000000 + .quad 0x3ff46979c0000000 + .quad 0x3ff464f780000000 + .quad 0x3ff4607780000000 + .quad 0x3ff45bf940000000 + .quad 0x3ff4577d00000000 + .quad 0x3ff45302c0000000 + .quad 0x3ff44e8a40000000 + .quad 0x3ff44a1400000000 + .quad 0x3ff4459f80000000 + .quad 0x3ff4412d40000000 + .quad 0x3ff43cbcc0000000 + .quad 0x3ff4384e40000000 + .quad 0x3ff433e180000000 + .quad 0x3ff42f7700000000 + .quad 0x3ff42b0e40000000 + .quad 0x3ff426a780000000 + .quad 0x3ff4224280000000 + .quad 0x3ff41ddf80000000 + .quad 0x3ff4197e80000000 + .quad 0x3ff4151f40000000 + .quad 0x3ff410c200000000 + .quad 0x3ff40c66c0000000 + .quad 0x3ff4080d40000000 + .quad 0x3ff403b5c0000000 + .quad 0x3ff3ff6000000000 + .quad 0x3ff3fb0c00000000 + .quad 0x3ff3f6ba40000000 + .quad 0x3ff3f26a00000000 + .quad 0x3ff3ee1bc0000000 + .quad 0x3ff3e9cf80000000 + .quad 0x3ff3e58500000000 + .quad 0x3ff3e13c40000000 + .quad 0x3ff3dcf580000000 + .quad 0x3ff3d8b080000000 + .quad 0x3ff3d46d40000000 + .quad 0x3ff3d02c00000000 + .quad 0x3ff3cbec80000000 + .quad 0x3ff3c7aec0000000 + .quad 0x3ff3c37300000000 + .quad 0x3ff3bf3900000000 + .quad 0x3ff3bb00c0000000 + .quad 0x3ff3b6ca40000000 + .quad 0x3ff3b29580000000 + .quad 0x3ff3ae62c0000000 + .quad 0x3ff3aa3180000000 + .quad 0x3ff3a60240000000 + .quad 0x3ff3a1d4c0000000 + .quad 0x3ff39da900000000 + .quad 0x3ff3997f40000000 + .quad 0x3ff3955700000000 + .quad 0x3ff3913080000000 + .quad 0x3ff38d0bc0000000 + .quad 0x3ff388e900000000 + .quad 0x3ff384c7c0000000 + .quad 0x3ff380a840000000 + .quad 0x3ff37c8ac0000000 + .quad 0x3ff3786ec0000000 + .quad 0x3ff3745480000000 + .quad 0x3ff3703c00000000 + .quad 0x3ff36c2540000000 + .quad 0x3ff3681040000000 + .quad 0x3ff363fcc0000000 + .quad 0x3ff35feb40000000 + .quad 0x3ff35bdb40000000 + .quad 0x3ff357cd00000000 + .quad 0x3ff353c080000000 + .quad 0x3ff34fb5c0000000 + .quad 0x3ff34bac80000000 + .quad 0x3ff347a540000000 + .quad 0x3ff3439f80000000 + .quad 0x3ff33f9b40000000 + .quad 0x3ff33b9900000000 + .quad 0x3ff3379840000000 + .quad 0x3ff3339900000000 + .quad 0x3ff32f9bc0000000 + .quad 0x3ff32b9fc0000000 + .quad 0x3ff327a5c0000000 + .quad 0x3ff323ad40000000 + .quad 0x3ff31fb680000000 + .quad 0x3ff31bc140000000 + .quad 0x3ff317cdc0000000 + .quad 0x3ff313dbc0000000 + .quad 0x3ff30feb80000000 + .quad 0x3ff30bfd00000000 + .quad 0x3ff3080fc0000000 + .quad 0x3ff3042480000000 + .quad 0x3ff3003ac0000000 + .quad 0x3ff2fc5280000000 + .quad 0x3ff2f86bc0000000 + .quad 0x3ff2f48700000000 + .quad 0x3ff2f0a380000000 + .quad 0x3ff2ecc1c0000000 + .quad 0x3ff2e8e180000000 + .quad 0x3ff2e502c0000000 + .quad 0x3ff2e125c0000000 + .quad 0x3ff2dd4a40000000 + .quad 0x3ff2d97080000000 + .quad 0x3ff2d59840000000 + .quad 0x3ff2d1c180000000 + .quad 0x3ff2cdec40000000 + .quad 0x3ff2ca1880000000 + .quad 0x3ff2c64680000000 + .quad 0x3ff2c27600000000 + .quad 0x3ff2bea700000000 + .quad 0x3ff2bad9c0000000 + .quad 0x3ff2b70dc0000000 + .quad 0x3ff2b34380000000 + .quad 0x3ff2af7ac0000000 + .quad 0x3ff2abb340000000 + .quad 0x3ff2a7ed80000000 + .quad 0x3ff2a42980000000 + .quad 0x3ff2a066c0000000 + .quad 0x3ff29ca580000000 + .quad 0x3ff298e5c0000000 + .quad 0x3ff29527c0000000 + .quad 0x3ff2916b00000000 + .quad 0x3ff28dafc0000000 + .quad 0x3ff289f640000000 + .quad 0x3ff2863e00000000 + .quad 0x3ff2828740000000 + .quad 0x3ff27ed240000000 + .quad 0x3ff27b1e80000000 + .quad 0x3ff2776c40000000 + .quad 0x3ff273bb80000000 + .quad 0x3ff2700c40000000 + .quad 0x3ff26c5e80000000 + .quad 0x3ff268b200000000 + .quad 0x3ff2650740000000 + .quad 0x3ff2615dc0000000 + .quad 0x3ff25db5c0000000 + .quad 0x3ff25a0f40000000 + .quad 0x3ff2566a40000000 + .quad 0x3ff252c6c0000000 + .quad 0x3ff24f2480000000 + .quad 0x3ff24b83c0000000 + .quad 0x3ff247e480000000 + .quad 0x3ff24446c0000000 + .quad 0x3ff240aa40000000 + .quad 0x3ff23d0f40000000 + .quad 0x3ff23975c0000000 + .quad 0x3ff235dd80000000 + .quad 0x3ff23246c0000000 + .quad 0x3ff22eb180000000 + .quad 0x3ff22b1d80000000 + .quad 0x3ff2278b00000000 + .quad 0x3ff223fa00000000 + .quad 0x3ff2206a40000000 + .quad 0x3ff21cdc00000000 + .quad 0x3ff2194f00000000 + .quad 0x3ff215c380000000 + .quad 0x3ff2123940000000 + .quad 0x3ff20eb080000000 + .quad 0x3ff20b2940000000 + .quad 0x3ff207a340000000 + .quad 0x3ff2041ec0000000 + .quad 0x3ff2009b80000000 + .quad 0x3ff1fd1980000000 + .quad 0x3ff1f99900000000 + .quad 0x3ff1f619c0000000 + .quad 0x3ff1f29c00000000 + .quad 0x3ff1ef1fc0000000 + .quad 0x3ff1eba480000000 + .quad 0x3ff1e82ac0000000 + .quad 0x3ff1e4b280000000 + .quad 0x3ff1e13b80000000 + .quad 0x3ff1ddc5c0000000 + .quad 0x3ff1da5180000000 + .quad 0x3ff1d6de80000000 + .quad 0x3ff1d36cc0000000 + .quad 0x3ff1cffc40000000 + .quad 0x3ff1cc8d40000000 + .quad 0x3ff1c91f80000000 + .quad 0x3ff1c5b340000000 + .quad 0x3ff1c24840000000 + .quad 0x3ff1bede40000000 + .quad 0x3ff1bb7600000000 + .quad 0x3ff1b80ec0000000 + .quad 0x3ff1b4a900000000 + .quad 0x3ff1b14480000000 + .quad 0x3ff1ade140000000 + .quad 0x3ff1aa7f40000000 + .quad 0x3ff1a71e80000000 + .quad 0x3ff1a3bf40000000 + .quad 0x3ff1a06140000000 + .quad 0x3ff19d0480000000 + .quad 0x3ff199a900000000 + .quad 0x3ff1964ec0000000 + .quad 0x3ff192f5c0000000 + .quad 0x3ff18f9e00000000 + .quad 0x3ff18c47c0000000 + .quad 0x3ff188f280000000 + .quad 0x3ff1859ec0000000 + .quad 0x3ff1824c00000000 + .quad 0x3ff17efac0000000 + .quad 0x3ff17baa80000000 + .quad 0x3ff1785bc0000000 + .quad 0x3ff1750e40000000 + .quad 0x3ff171c1c0000000 + .quad 0x3ff16e76c0000000 + .quad 0x3ff16b2d00000000 + .quad 0x3ff167e440000000 + .quad 0x3ff1649d00000000 + .quad 0x3ff16156c0000000 + .quad 0x3ff15e11c0000000 + .quad 0x3ff15ace40000000 + .quad 0x3ff1578bc0000000 + .quad 0x3ff1544a80000000 + .quad 0x3ff1510a80000000 + .quad 0x3ff14dcbc0000000 + .quad 0x3ff14a8e40000000 + .quad 0x3ff14751c0000000 + .quad 0x3ff14416c0000000 + .quad 0x3ff140dcc0000000 + .quad 0x3ff13da400000000 + .quad 0x3ff13a6c80000000 + .quad 0x3ff1373600000000 + .quad 0x3ff1340100000000 + .quad 0x3ff130cd00000000 + .quad 0x3ff12d9a40000000 + .quad 0x3ff12a68c0000000 + .quad 0x3ff1273840000000 + .quad 0x3ff1240900000000 + .quad 0x3ff120db00000000 + .quad 0x3ff11dae40000000 + .quad 0x3ff11a8280000000 + .quad 0x3ff1175800000000 + .quad 0x3ff1142ec0000000 + .quad 0x3ff11106c0000000 + .quad 0x3ff10ddfc0000000 + .quad 0x3ff10ab9c0000000 + .quad 0x3ff1079540000000 + .quad 0x3ff10471c0000000 + .quad 0x3ff1014f80000000 + .quad 0x3ff0fe2e40000000 + .quad 0x3ff0fb0e40000000 + .quad 0x3ff0f7ef40000000 + .quad 0x3ff0f4d180000000 + .quad 0x3ff0f1b500000000 + .quad 0x3ff0ee9980000000 + .quad 0x3ff0eb7f40000000 + .quad 0x3ff0e86600000000 + .quad 0x3ff0e54e00000000 + .quad 0x3ff0e23700000000 + .quad 0x3ff0df2140000000 + .quad 0x3ff0dc0c80000000 + .quad 0x3ff0d8f900000000 + .quad 0x3ff0d5e6c0000000 + .quad 0x3ff0d2d540000000 + .quad 0x3ff0cfc540000000 + .quad 0x3ff0ccb640000000 + .quad 0x3ff0c9a840000000 + .quad 0x3ff0c69b40000000 + .quad 0x3ff0c38f80000000 + .quad 0x3ff0c08500000000 + .quad 0x3ff0bd7b80000000 + .quad 0x3ff0ba7300000000 + .quad 0x3ff0b76bc0000000 + .quad 0x3ff0b46580000000 + .quad 0x3ff0b16040000000 + .quad 0x3ff0ae5c40000000 + .quad 0x3ff0ab5940000000 + .quad 0x3ff0a85780000000 + .quad 0x3ff0a556c0000000 + .quad 0x3ff0a25700000000 + .quad 0x3ff09f5880000000 + .quad 0x3ff09c5ac0000000 + .quad 0x3ff0995e80000000 + .quad 0x3ff0966300000000 + .quad 0x3ff09368c0000000 + .quad 0x3ff0906f80000000 + .quad 0x3ff08d7740000000 + .quad 0x3ff08a8000000000 + .quad 0x3ff0878a00000000 + .quad 0x3ff0849500000000 + .quad 0x3ff081a100000000 + .quad 0x3ff07eae40000000 + .quad 0x3ff07bbc40000000 + .quad 0x3ff078cb80000000 + .quad 0x3ff075dbc0000000 + .quad 0x3ff072ed00000000 + .quad 0x3ff06fff80000000 + .quad 0x3ff06d12c0000000 + .quad 0x3ff06a2740000000 + .quad 0x3ff0673cc0000000 + .quad 0x3ff0645340000000 + .quad 0x3ff0616ac0000000 + .quad 0x3ff05e8340000000 + .quad 0x3ff05b9d00000000 + .quad 0x3ff058b780000000 + .quad 0x3ff055d340000000 + .quad 0x3ff052f000000000 + .quad 0x3ff0500d80000000 + .quad 0x3ff04d2c40000000 + .quad 0x3ff04a4c00000000 + .quad 0x3ff0476cc0000000 + .quad 0x3ff0448e80000000 + .quad 0x3ff041b140000000 + .quad 0x3ff03ed500000000 + .quad 0x3ff03bf9c0000000 + .quad 0x3ff0391fc0000000 + .quad 0x3ff0364680000000 + .quad 0x3ff0336e40000000 + .quad 0x3ff0309700000000 + .quad 0x3ff02dc0c0000000 + .quad 0x3ff02aeb80000000 + .quad 0x3ff0281740000000 + .quad 0x3ff0254400000000 + .quad 0x3ff02271c0000000 + .quad 0x3ff01fa080000000 + .quad 0x3ff01cd040000000 + .quad 0x3ff01a00c0000000 + .quad 0x3ff0173280000000 + .quad 0x3ff0146540000000 + .quad 0x3ff01198c0000000 + .quad 0x3ff00ecd80000000 + .quad 0x3ff00c0300000000 + .quad 0x3ff0093980000000 + .quad 0x3ff0067100000000 + .quad 0x3ff003a980000000 + .quad 0x3ff000e300000000 + .quad 0x3feffc3a80000000 + .quad 0x3feff6b140000000 + .quad 0x3feff129c0000000 + .quad 0x3fefeba480000000 + .quad 0x3fefe620c0000000 + .quad 0x3fefe09f40000000 + .quad 0x3fefdb1f80000000 + .quad 0x3fefd5a180000000 + .quad 0x3fefd02580000000 + .quad 0x3fefcaab80000000 + .quad 0x3fefc53340000000 + .quad 0x3fefbfbd00000000 + .quad 0x3fefba4880000000 + .quad 0x3fefb4d600000000 + .quad 0x3fefaf6540000000 + .quad 0x3fefa9f680000000 + .quad 0x3fefa48980000000 + .quad 0x3fef9f1e40000000 + .quad 0x3fef99b500000000 + .quad 0x3fef944dc0000000 + .quad 0x3fef8ee800000000 + .quad 0x3fef898440000000 + .quad 0x3fef842280000000 + .quad 0x3fef7ec280000000 + .quad 0x3fef796440000000 + .quad 0x3fef7407c0000000 + .quad 0x3fef6ead40000000 + .quad 0x3fef695480000000 + .quad 0x3fef63fd80000000 + .quad 0x3fef5ea880000000 + .quad 0x3fef595540000000 + .quad 0x3fef5403c0000000 + .quad 0x3fef4eb400000000 + .quad 0x3fef496640000000 + .quad 0x3fef441a00000000 + .quad 0x3fef3ecfc0000000 + .quad 0x3fef398740000000 + .quad 0x3fef344080000000 + .quad 0x3fef2efb80000000 + .quad 0x3fef29b880000000 + .quad 0x3fef247700000000 + .quad 0x3fef1f3780000000 + .quad 0x3fef19f980000000 + .quad 0x3fef14bd80000000 + .quad 0x3fef0f8340000000 + .quad 0x3fef0a4ac0000000 + .quad 0x3fef0513c0000000 + .quad 0x3feeffdec0000000 + .quad 0x3feefaab80000000 + .quad 0x3feef57a00000000 + .quad 0x3feef04a00000000 + .quad 0x3feeeb1c00000000 + .quad 0x3feee5ef80000000 + .quad 0x3feee0c500000000 + .quad 0x3feedb9c00000000 + .quad 0x3feed67500000000 + .quad 0x3feed14f80000000 + .quad 0x3feecc2bc0000000 + .quad 0x3feec709c0000000 + .quad 0x3feec1e940000000 + .quad 0x3feebccac0000000 + .quad 0x3feeb7adc0000000 + .quad 0x3feeb29280000000 + .quad 0x3feead7900000000 + .quad 0x3feea86140000000 + .quad 0x3feea34b40000000 + .quad 0x3fee9e36c0000000 + .quad 0x3fee992400000000 + .quad 0x3fee941300000000 + .quad 0x3fee8f0380000000 + .quad 0x3fee89f5c0000000 + .quad 0x3fee84e9c0000000 + .quad 0x3fee7fdf40000000 + .quad 0x3fee7ad680000000 + .quad 0x3fee75cf80000000 + .quad 0x3fee70ca00000000 + .quad 0x3fee6bc640000000 + .quad 0x3fee66c440000000 + .quad 0x3fee61c3c0000000 + .quad 0x3fee5cc500000000 + .quad 0x3fee57c7c0000000 + .quad 0x3fee52cc40000000 + .quad 0x3fee4dd280000000 + .quad 0x3fee48da00000000 + .quad 0x3fee43e380000000 + .quad 0x3fee3eee80000000 + .quad 0x3fee39fb00000000 + .quad 0x3fee350940000000 + .quad 0x3fee301940000000 + .quad 0x3fee2b2ac0000000 + .quad 0x3fee263dc0000000 + .quad 0x3fee215280000000 + .quad 0x3fee1c68c0000000 + .quad 0x3fee178080000000 + .quad 0x3fee129a00000000 + .quad 0x3fee0db540000000 + .quad 0x3fee08d1c0000000 + .quad 0x3fee03f000000000 + .quad 0x3fedff1000000000 + .quad 0x3fedfa3140000000 + .quad 0x3fedf55440000000 + .quad 0x3fedf07900000000 + .quad 0x3fedeb9f00000000 + .quad 0x3fede6c6c0000000 + .quad 0x3fede1f040000000 + .quad 0x3feddd1b00000000 + .quad 0x3fedd84780000000 + .quad 0x3fedd37580000000 + .quad 0x3fedcea500000000 + .quad 0x3fedc9d600000000 + .quad 0x3fedc508c0000000 + .quad 0x3fedc03d00000000 + .quad 0x3fedbb72c0000000 + .quad 0x3fedb6aa00000000 + .quad 0x3fedb1e2c0000000 + .quad 0x3fedad1d00000000 + .quad 0x3feda85900000000 + .quad 0x3feda39680000000 + .quad 0x3fed9ed540000000 + .quad 0x3fed9a15c0000000 + .quad 0x3fed9557c0000000 + .quad 0x3fed909b40000000 + .quad 0x3fed8be040000000 + .quad 0x3fed8726c0000000 + .quad 0x3fed826f00000000 + .quad 0x3fed7db880000000 + .quad 0x3fed790380000000 + .quad 0x3fed745000000000 + .quad 0x3fed6f9e40000000 + .quad 0x3fed6aedc0000000 + .quad 0x3fed663ec0000000 + .quad 0x3fed619140000000 + .quad 0x3fed5ce540000000 + .quad 0x3fed583ac0000000 + .quad 0x3fed5391c0000000 + .quad 0x3fed4eea40000000 + .quad 0x3fed4a4440000000 + .quad 0x3fed459f80000000 + .quad 0x3fed40fc80000000 + .quad 0x3fed3c5ac0000000 + .quad 0x3fed37bac0000000 + .quad 0x3fed331c00000000 + .quad 0x3fed2e7ec0000000 + .quad 0x3fed29e300000000 + .quad 0x3fed254880000000 + .quad 0x3fed20afc0000000 + .quad 0x3fed1c1840000000 + .quad 0x3fed178240000000 + .quad 0x3fed12edc0000000 + .quad 0x3fed0e5ac0000000 + .quad 0x3fed09c900000000 + .quad 0x3fed0538c0000000 + .quad 0x3fed00aa00000000 + .quad 0x3fecfc1c80000000 + .quad 0x3fecf790c0000000 + .quad 0x3fecf30600000000 + .quad 0x3fecee7d00000000 + .quad 0x3fece9f540000000 + .quad 0x3fece56f00000000 + .quad 0x3fece0ea40000000 + .quad 0x3fecdc66c0000000 + .quad 0x3fecd7e4c0000000 + .quad 0x3fecd36440000000 + .quad 0x3feccee500000000 + .quad 0x3fecca6740000000 + .quad 0x3fecc5eac0000000 + .quad 0x3fecc16fc0000000 + .quad 0x3fecbcf640000000 + .quad 0x3fecb87e00000000 + .quad 0x3fecb40740000000 + .quad 0x3fecaf91c0000000 + .quad 0x3fecab1dc0000000 + .quad 0x3feca6ab00000000 + .quad 0x3feca239c0000000 + .quad 0x3fec9dc9c0000000 + .quad 0x3fec995b40000000 + .quad 0x3fec94ee00000000 + .quad 0x3fec908240000000 + .quad 0x3fec8c17c0000000 + .quad 0x3fec87aec0000000 + .quad 0x3fec834700000000 + .quad 0x3fec7ee0c0000000 + .quad 0x3fec7a7bc0000000 + .quad 0x3fec761800000000 + .quad 0x3fec71b5c0000000 + .quad 0x3fec6d54c0000000 + .quad 0x3fec68f540000000 + .quad 0x3fec649700000000 + .quad 0x3fec603a00000000 + .quad 0x3fec5bde80000000 + .quad 0x3fec578440000000 + .quad 0x3fec532b80000000 + .quad 0x3fec4ed3c0000000 + .quad 0x3fec4a7dc0000000 + .quad 0x3fec4628c0000000 + .quad 0x3fec41d540000000 + .quad 0x3fec3d8300000000 + .quad 0x3fec393200000000 + .quad 0x3fec34e240000000 + .quad 0x3fec309400000000 + .quad 0x3fec2c4700000000 + .quad 0x3fec27fb80000000 + .quad 0x3fec23b100000000 + .quad 0x3fec1f6800000000 + .quad 0x3fec1b2040000000 + .quad 0x3fec16d9c0000000 + .quad 0x3fec1294c0000000 + .quad 0x3fec0e50c0000000 + .quad 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0x3fea4eab80000000 + .quad 0x3fea4aecc0000000 + .quad 0x3fea472ec0000000 + .quad 0x3fea437200000000 + .quad 0x3fea3fb640000000 + .quad 0x3fea3bfbc0000000 + .quad 0x3fea384240000000 + .quad 0x3fea3489c0000000 + .quad 0x3fea30d240000000 + .quad 0x3fea2d1bc0000000 + .quad 0x3fea296680000000 + .quad 0x3fea25b200000000 + .quad 0x3fea21fec0000000 + .quad 0x3fea1e4cc0000000 + .quad 0x3fea1a9b80000000 + .quad 0x3fea16eb40000000 + .quad 0x3fea133c40000000 + .quad 0x3fea0f8e40000000 + .quad 0x3fea0be140000000 + .quad 0x3fea083540000000 + .quad 0x3fea048a40000000 + .quad 0x3fea00e080000000 + .quad 0x3fe9fd3780000000 + .quad 0x3fe9f98fc0000000 + .quad 0x3fe9f5e900000000 + .quad 0x3fe9f24340000000 + .quad 0x3fe9ee9e80000000 + .quad 0x3fe9eafac0000000 + .quad 0x3fe9e75800000000 + .quad 0x3fe9e3b640000000 + .quad 0x3fe9e01580000000 + .quad 0x3fe9dc7600000000 + .quad 0x3fe9d8d740000000 + .quad 0x3fe9d539c0000000 + .quad 0x3fe9d19d00000000 + .quad 0x3fe9ce0180000000 + .quad 0x3fe9ca66c0000000 + .quad 0x3fe9c6cd40000000 + .quad 0x3fe9c33480000000 + .quad 0x3fe9bf9d00000000 + .quad 0x3fe9bc0680000000 + .quad 0x3fe9b870c0000000 + .quad 0x3fe9b4dc40000000 + .quad 0x3fe9b148c0000000 + .quad 0x3fe9adb600000000 + .quad 0x3fe9aa2480000000 + .quad 0x3fe9a693c0000000 + .quad 0x3fe9a30440000000 + .quad 0x3fe99f7580000000 + .quad 0x3fe99be7c0000000 + .quad 0x3fe9985b40000000 + .quad 0x3fe994cf80000000 + .quad 0x3fe99144c0000000 + .quad 0x3fe98dbb00000000 + .quad 0x3fe98a3240000000 + .quad 0x3fe986aa80000000 + .quad 0x3fe98323c0000000 + .quad 0x3fe97f9e00000000 + .quad 0x3fe97c1900000000 + .quad 0x3fe9789540000000 + .quad 0x3fe9751240000000 + .quad 0x3fe9719080000000 + .quad 0x3fe96e0f80000000 + .quad 0x3fe96a8f80000000 + .quad 0x3fe9671040000000 + .quad 0x3fe9639240000000 + .quad 0x3fe9601540000000 + .quad 0x3fe95c9900000000 + .quad 0x3fe9591dc0000000 + .quad 0x3fe955a380000000 + .quad 0x3fe9522a40000000 + .quad 0x3fe94eb200000000 + .quad 0x3fe94b3a80000000 + .quad 0x3fe947c400000000 + .quad 0x3fe9444e80000000 + .quad 0x3fe940da00000000 + .quad 0x3fe93d6640000000 + .quad 0x3fe939f3c0000000 + .quad 0x3fe9368200000000 + .quad 0x3fe9331140000000 + .quad 0x3fe92fa140000000 + .quad 0x3fe92c3280000000 + .quad 0x3fe928c480000000 + .quad 0x3fe9255780000000 + .quad 0x3fe921eb40000000 + .quad 0x3fe91e8040000000 + .quad 0x3fe91b1600000000 + .quad 0x3fe917ac80000000 + .quad 0x3fe9144440000000 + .quad 0x3fe910dcc0000000 + .quad 0x3fe90d7640000000 + .quad 0x3fe90a1080000000 + .quad 0x3fe906abc0000000 + .quad 0x3fe9034800000000 + .quad 0x3fe8ffe540000000 + .quad 0x3fe8fc8340000000 + .quad 0x3fe8f92240000000 + .quad 0x3fe8f5c200000000 + .quad 0x3fe8f26300000000 + .quad 0x3fe8ef0480000000 + .quad 0x3fe8eba740000000 + .quad 0x3fe8e84ac0000000 + .quad 0x3fe8e4ef40000000 + .quad 0x3fe8e19480000000 + .quad 0x3fe8de3ac0000000 + .quad 0x3fe8dae1c0000000 + .quad 0x3fe8d78a00000000 + .quad 0x3fe8d432c0000000 + .quad 0x3fe8d0dcc0000000 + .quad 0x3fe8cd8780000000 + .quad 0x3fe8ca3300000000 + .quad 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0x3fe76a2800000000 + .quad 0x3fe7673080000000 + .quad 0x3fe7643980000000 + .quad 0x3fe7614340000000 + .quad 0x3fe75e4e00000000 + .quad 0x3fe75b5940000000 + .quad 0x3fe7586580000000 + .quad 0x3fe7557240000000 + .quad 0x3fe7527fc0000000 + .quad 0x3fe74f8e40000000 + .quad 0x3fe74c9d40000000 + .quad 0x3fe749ad00000000 + .quad 0x3fe746bd80000000 + .quad 0x3fe743cec0000000 + .quad 0x3fe740e100000000 + .quad 0x3fe73df3c0000000 + .quad 0x3fe73b0740000000 + .quad 0x3fe7381b80000000 + .quad 0x3fe7353080000000 + .quad 0x3fe7324600000000 + .quad 0x3fe72f5c80000000 + .quad 0x3fe72c73c0000000 + .quad 0x3fe7298b80000000 + .quad 0x3fe726a440000000 + .quad 0x3fe723bd80000000 + .quad 0x3fe720d7c0000000 + .quad 0x3fe71df280000000 + .quad 0x3fe71b0e00000000 + .quad 0x3fe7182a40000000 + .quad 0x3fe7154740000000 + .quad 0x0000000000000000 + .rept 48 + .byte 0 + .endr + +/* Log(2) lookup table for log part (non HSW): */ +.if .-__svml_dpow_data != _log2_t1 +.err +.endif + .rept 2 + .quad 0x0000000000000000 + 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0xbfbcdf1a00000000 + .quad 0xbe66073d700e9f19 + .quad 0xbfbcad3500000000 + .quad 0xbe63a29cd758d759 + .quad 0xbfbc7b5100000000 + .quad 0xbe49b8777d6bbc9d + .quad 0xbfbc497800000000 + .quad 0xbe623f87f4487fe4 + .quad 0xbfbc17a400000000 + .quad 0xbe55196cb4c66620 + .quad 0xbfbbe5d800000000 + .quad 0xbe496e785a0317a3 + .quad 0xbfbbb41000000000 + .quad 0xbe5ee49501957b40 + .quad 0xbfbb825000000000 + .quad 0xbe6cf6df4849748b + .quad 0xbfbb509500000000 + .quad 0xbe688f964bd70c8f + .quad 0xbfbb1ee600000000 + .quad 0xbe6072c317519bb4 + .quad 0xbfbaed3800000000 + .quad 0xbe05b3290a662bd0 + .quad 0xbfbabb9500000000 + .quad 0xbe5b246ad0582c09 + .quad 0xbfba89f700000000 + .quad 0xbe55372721811f66 + .quad 0xbfba585d00000000 + .quad 0xbe67c995fe88bce3 + .quad 0xbfba26cc00000000 + .quad 0xbe596605e161e768 + .quad 0xbfb9f54300000000 + .quad 0xbe53bd6ea8cdcabf + .quad 0xbfb9c3be00000000 + .quad 0xbe6873a6488f239e + .quad 0xbfb9924200000000 + .quad 0xbe6038db2539e54e + .quad 0xbfb960ca00000000 + .quad 0xbe6a3576f0eb47ea + .quad 0xbfb92f5b00000000 + .quad 0xbe5ca16578e782d8 + .quad 0xbfb8fdf000000000 + .quad 0xbe6571dd058c9404 + .quad 0xbfb8cc8e00000000 + .quad 0xbe4e8172926b3912 + .quad 0xbfb89b3400000000 + .quad 0xbe458eb8a49a1ed9 + .quad 0xbfb869de00000000 + .quad 0xbe67736434037b3e + .quad 0xbfb8388d00000000 + .quad 0xbe6e2728b7069e85 + .quad 0xbfb8074500000000 + .quad 0xbe61c6bcd5b504de + .quad 0xbfb7d60500000000 + .quad 0xbe62d9f791fd12f7 + .quad 0xbfb7a4ca00000000 + .quad 0xbe53b18b476f88bf + .quad 0xbfb7739300000000 + .quad 0xbe671b2ad71bba2e + .quad 0xbfb7426500000000 + .quad 0xbe6329422bbd68e8 + .quad 0xbfb7113f00000000 + .quad 0xbe6e8b3c2fe4ecae + .quad 0xbfb6e01f00000000 + .quad 0xbe2795edd5ed58e9 + .quad 0xbfb6af0200000000 + .quad 0xbe6c4c07447a13fa + .quad 0xbfb67def00000000 + .quad 0xbe4f2ea58340e81e + .quad 0xbfb64ce400000000 + .quad 0xbe4203398a8ffda4 + .quad 0xbfb61bda00000000 + .quad 0xbe2d4147ad124eaa + .quad 0xbfb5eadc00000000 + .quad 0xbe539c66835b9867 + .quad 0xbfb5b9df00000000 + .quad 0xbe6317f3d15a9860 + .quad 0xbfb588ef00000000 + .quad 0xbe503474104b244e + .quad 0xbfb557ff00000000 + .quad 0xbe6f1dfae0bd2e94 + .quad 0xbfb5271900000000 + .quad 0xbe541889ef09d7c8 + .quad 0xbfb4f63b00000000 + .quad 0xbe52dc76d475d4d1 + .quad 0xbfb4c56200000000 + .quad 0xbe433458770a1735 + .quad 0xbfb4948d00000000 + .quad 0xbe6c8223b5c8b49b + .quad 0xbfb463c200000000 + .quad 0xbe540d91e2302042 + .quad 0xbfb432fb00000000 + .quad 0xbe64b47f064d986f + .quad 0xbfb4023900000000 + .quad 0xbe6ce4d526c81e43 + .quad 0xbfb3d18000000000 + .quad 0xbe6c41714a091d46 + .quad 0xbfb3a0d000000000 + .quad 0xbe63540db8c80703 + .quad 0xbfb3702100000000 + .quad 0xbe5f8cf1a845a25c + .quad 0xbfb33f7b00000000 + .quad 0xbe430a65c7a2686f + .quad 0xbfb30edd00000000 + .quad 0xbe62d26a7215665c + .quad 0xbfb2de4500000000 + .quad 0xbe1bff57e3bab991 + .quad 0xbfb2adb100000000 + .quad 0xbe5e8adfc156e82d + .quad 0xbfb27d2200000000 + .quad 0xbe6e5d041c5f1a05 + .quad 0xbfb24c9d00000000 + .quad 0xbe50a21095df344c + .quad 0xbfb21c2000000000 + .quad 0xbe5b57c218054e22 + .quad 0xbfb1eba400000000 + .quad 0xbe6b1806f4988888 + .quad 0xbfb1bb3200000000 + .quad 0xbe430029dc60a716 + .quad 0xbfb18ac400000000 + .quad 0xbe611e8ed29c4bea + .quad 0xbfb15a5f00000000 + .quad 0xbe6aae4e1e1cd7e9 + .quad 0xbfb12a0000000000 + .quad 0xbe4f2855166a96d5 + .quad 0xbfb0f9a500000000 + .quad 0xbe68ccc743692647 + .quad 0xbfb0c95400000000 + .quad 0xbe50c2b8ff93eea0 + .quad 0xbfb0990400000000 + .quad 0xbe329700306849f4 + .quad 0xbfb068c000000000 + .quad 0xbe661c7597dfa0cf + .quad 0xbfb0387e00000000 + .quad 0xbe64f950c199fdd6 + .quad 0xbfb0084500000000 + .quad 0xbe6434bda55a11e5 + .quad 0xbfafb02300000000 + .quad 0xbe537435dba745c1 + .quad 0xbfaf4fc600000000 + .quad 0xbe4793720209c664 + .quad 0xbfaeef7b00000000 + .quad 0xbe3e845c9d0173b4 + .quad 0xbfae8f3a00000000 + .quad 0xbe527188bd53b8bf + .quad 0xbfae2f0400000000 + .quad 0xbe49e4e1f2d00cb9 + .quad 0xbfadced800000000 + .quad 0xbe57db5b6132809a + .quad 0xbfad6ebf00000000 + .quad 0xbe43c7fbabdf571f + .quad 0xbfad0eb000000000 + .quad 0xbe4c086873f1531f + .quad 0xbfacaeac00000000 + .quad 0xbe33d01264312288 + .quad 0xbfac4eb200000000 + .quad 0xbe4ed73a1b11c287 + .quad 0xbfabeecb00000000 + .quad 0xbe328d5761ea48d2 + .quad 0xbfab8eee00000000 + .quad 0xbe4e2759579ac08a + .quad 0xbfab2f1c00000000 + .quad 0xbe4eea927b8de26e + .quad 0xbfaacf5500000000 + .quad 0xbe3a03ec4341a4ac + .quad 0xbfaa6f9800000000 + .quad 0xbe54efb9656181bf + .quad 0xbfaa0fee00000000 + .quad 0xbe529aa680456564 + .quad 0xbfa9b04f00000000 + .quad 0xbe42b60fbbf05015 + .quad 0xbfa950ba00000000 + .quad 0xbe59ea4d388956ac + .quad 0xbfa8f13800000000 + .quad 0xbe5c820f8ddadcd6 + .quad 0xbfa891ba00000000 + .quad 0xbe27e05a334c58f7 + .quad 0xbfa8324d00000000 + .quad 0xbe5d3229b2ba0376 + .quad 0xbfa7d2ec00000000 + .quad 0xbe545e77c08ed94c + .quad 0xbfa7739600000000 + .quad 0xbe427656b6f95551 + .quad 0xbfa7144a00000000 + .quad 0xbe5c82a193d30405 + .quad 0xbfa6b50a00000000 + .quad 0xbe4ddebd1f3c284a + .quad 0xbfa655dc00000000 + .quad 0xbe599c108199cfd8 + .quad 0xbfa5f6ba00000000 + .quad 0xbe348e1f3828f0d8 + .quad 0xbfa597a200000000 + .quad 0xbe5240beb8df56ca + .quad 0xbfa5389600000000 + .quad 0xbe1aed65370b9099 + .quad 0xbfa4d99400000000 + .quad 0xbe5429166d091c5d + .quad 0xbfa47a9e00000000 + .quad 0xbe44d5db06b75692 + .quad 0xbfa41bba00000000 + .quad 0xbe5e4ff2e670387a + .quad 0xbfa3bcda00000000 + .quad 0xbe5e73df6e675ed2 + .quad 0xbfa35e0d00000000 + .quad 0xbe5df2994af6bbf0 + .quad 0xbfa2ff4c00000000 + .quad 0xbe31a09f65bfdef1 + .quad 0xbfa2a09500000000 + .quad 0xbe5290bafe6a7061 + .quad 0xbfa241ea00000000 + .quad 0xbe425151c43b4181 + .quad 0xbfa1e34a00000000 + .quad 0xbe41d8dbc0646431 + .quad 0xbfa184b500000000 + .quad 0xbe5298ac777c8c9d + .quad 0xbfa1263400000000 + .quad 0xbe10a2f9d7e8035a + .quad 0xbfa0c7b600000000 + .quad 0xbe0bbc4c660fd088 + .quad 0xbfa0694b00000000 + .quad 0xbe3cc374b7950d13 + .quad 0xbfa00aeb00000000 + .quad 0xbe5aa058acdc0265 + .quad 0xbf9f592000000000 + .quad 0xbe149b4d7e5df2c0 + .quad 0xbf9e9c8f00000000 + .quad 0xbe10a7a7e78bdba3 + .quad 0xbf9de01500000000 + .quad 0xbde02a1d978db2f1 + .quad 0xbf9d23b100000000 + .quad 0xbe4e9227a287068e + .quad 0xbf9c676500000000 + .quad 0xbe4e8561096793f8 + .quad 0xbf9bab3100000000 + .quad 0xbe0968e122179f22 + .quad 0xbf9aef1300000000 + .quad 0xbe328465c0dba24f + .quad 0xbf9a330c00000000 + .quad 0xbe47051e31e0d70b + .quad 0xbf99771d00000000 + .quad 0xbe38b8d275ff3a9a + .quad 0xbf98bb5500000000 + .quad 0xbe122bdb89883925 + .quad 0xbf97ff9400000000 + .quad 0xbe36fbf85d50fecb + .quad 0xbf9743eb00000000 + .quad 0xbdf87cba8eccac44 + .quad 0xbf96886800000000 + .quad 0xbe4bd57d800c1470 + .quad 0xbf95ccee00000000 + .quad 0xbe3be2933856d62e + .quad 0xbf95118b00000000 + .quad 0xbe409620e0f1be7b + .quad 0xbf94564f00000000 + .quad 0xbe4e4325cf62b811 + .quad 0xbf939b1c00000000 + .quad 0xbe2adee9af6a25c0 + .quad 0xbf92e00000000000 + .quad 0xbe20ce46d28f63c9 + .quad 0xbf92250b00000000 + .quad 0xbe41f6aa9fb6fe0b + .quad 0xbf916a1e00000000 + .quad 0xbe4e41409957601b + .quad 0xbf90af5900000000 + .quad 0xbe4e53e5a63658ad + .quad 0xbf8fe93900000000 + .quad 0xbe3eded24d629d7d + .quad 0xbf8e73ef00000000 + .quad 0xbe3a29d2ea7d362b + .quad 0xbf8cfef500000000 + .quad 0xbe1e2e79fe4aa765 + .quad 0xbf8b8a0a00000000 + .quad 0xbe3e8785027a216b + .quad 0xbf8a155000000000 + .quad 0xbe37a174d5a8bded + .quad 0xbf88a0c600000000 + .quad 0xbe35dde88f39d7ce + .quad 0xbf872c6c00000000 + .quad 0xbe3c41ea3f44a785 + .quad 0xbf85b86300000000 + .quad 0xbe194c69ffd7f42d + .quad 0xbf84446a00000000 + .quad 0xbe1a5e4e0d24af39 + .quad 0xbf82d0a100000000 + .quad 0xbe381611eb6c3818 + .quad 0xbf815d0900000000 + .quad 0xbe3dd5da9cc5f987 + .quad 0xbf7fd34500000000 + .quad 0xbe25bd80e0b0590e + .quad 0xbf7cec9900000000 + .quad 0xbe1ce47bb0eea510 + .quad 0xbf7a068e00000000 + .quad 0xbe26dbe100877575 + .quad 0xbf7720e600000000 + .quad 0xbd9aa4f614b9e1ac + .quad 0xbf743b5f00000000 + .quad 0xbe271a96b1eb7842 + .quad 0xbf71567b00000000 + .quad 0xbe2318f60005710d + .quad 0xbf6ce37400000000 + .quad 0xbe0c7a4e122b1762 + .quad 0xbf671b3600000000 + .quad 0xbe1c85d1e3d214d1 + .quad 0xbf61533f00000000 + .quad 0xbe0e793b61aa1f54 + .quad 0xbf57181c00000000 + .quad 0xbe01296a4555af78 + .quad 0xbf47168e00000000 + .quad 0xbdf30d6f34ebfa1c + .rept 2 + .quad 0x0000000000000000 + .endr + .rept 48 + .byte 0 + .endr + +/* Exp(2) lookup table for exp part (non HSW) */ +.if .-__svml_dpow_data != _exp2_tbl +.err +.endif + .quad 0x3ff0000000000000 + .quad 0x0000000000000000 + .quad 0x3ff0163da9fb3335 + .quad 0x3c9b61299ab8cdb7 + .quad 0x3ff02c9a3e778061 + .quad 0xbc719083535b085d + .quad 0x3ff04315e86e7f85 + .quad 0xbc90a31c1977c96e + .quad 0x3ff059b0d3158574 + .quad 0x3c8d73e2a475b465 + .quad 0x3ff0706b29ddf6de + .quad 0xbc8c91dfe2b13c26 + .quad 0x3ff0874518759bc8 + .quad 0x3c6186be4bb284ff + .quad 0x3ff09e3ecac6f383 + .quad 0x3c91487818316135 + .quad 0x3ff0b5586cf9890f + .quad 0x3c98a62e4adc610a + .quad 0x3ff0cc922b7247f7 + .quad 0x3c901edc16e24f71 + .quad 0x3ff0e3ec32d3d1a2 + .quad 0x3c403a1727c57b52 + .quad 0x3ff0fb66affed31b + .quad 0xbc6b9bedc44ebd7b + .quad 0x3ff11301d0125b51 + .quad 0xbc96c51039449b39 + .quad 0x3ff12abdc06c31cc + .quad 0xbc51b514b36ca5c7 + .quad 0x3ff1429aaea92de0 + .quad 0xbc932fbf9af1369e + .quad 0x3ff15a98c8a58e51 + .quad 0x3c82406ab9eeab09 + .quad 0x3ff172b83c7d517b + .quad 0xbc819041b9d78a75 + .quad 0x3ff18af9388c8dea + .quad 0xbc911023d1970f6b + .quad 0x3ff1a35beb6fcb75 + .quad 0x3c8e5b4c7b4968e4 + .quad 0x3ff1bbe084045cd4 + .quad 0xbc995386352ef607 + .quad 0x3ff1d4873168b9aa + .quad 0x3c9e016e00a2643c + .quad 0x3ff1ed5022fcd91d + .quad 0xbc91df98027bb78b + .quad 0x3ff2063b88628cd6 + .quad 0x3c8dc775814a8494 + .quad 0x3ff21f49917ddc96 + .quad 0x3c82a97e9494a5ed + .quad 0x3ff2387a6e756238 + .quad 0x3c99b07eb6c70572 + .quad 0x3ff251ce4fb2a63f + .quad 0x3c8ac155bef4f4a4 + .quad 0x3ff26b4565e27cdd + .quad 0x3c82bd339940e9d9 + .quad 0x3ff284dfe1f56381 + .quad 0xbc9a4c3a8c3f0d7d + .quad 0x3ff29e9df51fdee1 + .quad 0x3c8612e8afad1255 + .quad 0x3ff2b87fd0dad990 + .quad 0xbc410adcd6381aa3 + .quad 0x3ff2d285a6e4030b + .quad 0x3c90024754db41d4 + .quad 0x3ff2ecafa93e2f56 + .quad 0x3c71ca0f45d52383 + .quad 0x3ff306fe0a31b715 + .quad 0x3c86f46ad23182e4 + .quad 0x3ff32170fc4cd831 + .quad 0x3c8a9ce78e18047c + .quad 0x3ff33c08b26416ff + .quad 0x3c932721843659a5 + .quad 0x3ff356c55f929ff1 + .quad 0xbc8b5cee5c4e4628 + .quad 0x3ff371a7373aa9cb + .quad 0xbc963aeabf42eae1 + .quad 0x3ff38cae6d05d866 + .quad 0xbc9e958d3c9904bc + .quad 0x3ff3a7db34e59ff7 + .quad 0xbc75e436d661f5e2 + .quad 0x3ff3c32dc313a8e5 + .quad 0xbc9efff8375d29c3 + .quad 0x3ff3dea64c123422 + .quad 0x3c8ada0911f09ebb + .quad 0x3ff3fa4504ac801c + .quad 0xbc97d023f956f9f3 + .quad 0x3ff4160a21f72e2a + .quad 0xbc5ef3691c309278 + .quad 0x3ff431f5d950a897 + .quad 0xbc81c7dde35f7998 + .quad 0x3ff44e086061892d + .quad 0x3c489b7a04ef80cf + .quad 0x3ff46a41ed1d0057 + .quad 0x3c9c944bd1648a76 + .quad 0x3ff486a2b5c13cd0 + .quad 0x3c73c1a3b69062f0 + .quad 0x3ff4a32af0d7d3de + .quad 0x3c99cb62f3d1be56 + .quad 0x3ff4bfdad5362a27 + .quad 0x3c7d4397afec42e2 + .quad 0x3ff4dcb299fddd0d + .quad 0x3c98ecdbbc6a7833 + .quad 0x3ff4f9b2769d2ca7 + .quad 0xbc94b309d25957e3 + .quad 0x3ff516daa2cf6642 + .quad 0xbc8f768569bd93ee + .quad 0x3ff5342b569d4f82 + .quad 0xbc807abe1db13cac + .quad 0x3ff551a4ca5d920f + .quad 0xbc8d689cefede59a + .quad 0x3ff56f4736b527da + .quad 0x3c99bb2c011d93ac + .quad 0x3ff58d12d497c7fd + .quad 0x3c8295e15b9a1de7 + .quad 0x3ff5ab07dd485429 + .quad 0x3c96324c054647ac + .quad 0x3ff5c9268a5946b7 + .quad 0x3c3c4b1b816986a2 + .quad 0x3ff5e76f15ad2148 + .quad 0x3c9ba6f93080e65d + .quad 0x3ff605e1b976dc09 + .quad 0xbc93e2429b56de47 + .quad 0x3ff6247eb03a5585 + .quad 0xbc9383c17e40b496 + .quad 0x3ff6434634ccc320 + .quad 0xbc8c483c759d8932 + .quad 0x3ff6623882552225 + .quad 0xbc9bb60987591c33 + .quad 0x3ff68155d44ca973 + .quad 0x3c6038ae44f73e64 + .quad 0x3ff6a09e667f3bcd + .quad 0xbc9bdd3413b26455 + .quad 0x3ff6c012750bdabf + .quad 0xbc72895667ff0b0c + .quad 0x3ff6dfb23c651a2f + .quad 0xbc6bbe3a683c88aa + .quad 0x3ff6ff7df9519484 + .quad 0xbc883c0f25860ef6 + .quad 0x3ff71f75e8ec5f74 + .quad 0xbc816e4786887a99 + .quad 0x3ff73f9a48a58174 + .quad 0xbc90a8d96c65d53b + .quad 0x3ff75feb564267c9 + .quad 0xbc90245957316dd3 + .quad 0x3ff780694fde5d3f + .quad 0x3c9866b80a02162c + .quad 0x3ff7a11473eb0187 + .quad 0xbc841577ee04992f + .quad 0x3ff7c1ed0130c132 + .quad 0x3c9f124cd1164dd5 + .quad 0x3ff7e2f336cf4e62 + .quad 0x3c705d02ba15797e + .quad 0x3ff80427543e1a12 + .quad 0xbc927c86626d972a + .quad 0x3ff82589994cce13 + .quad 0xbc9d4c1dd41532d7 + .quad 0x3ff8471a4623c7ad + .quad 0xbc88d684a341cdfb + .quad 0x3ff868d99b4492ed + .quad 0xbc9fc6f89bd4f6ba + .quad 0x3ff88ac7d98a6699 + .quad 0x3c9994c2f37cb53a + .quad 0x3ff8ace5422aa0db + .quad 0x3c96e9f156864b26 + .quad 0x3ff8cf3216b5448c + .quad 0xbc70d55e32e9e3aa + .quad 0x3ff8f1ae99157736 + .quad 0x3c85cc13a2e3976c + .quad 0x3ff9145b0b91ffc6 + .quad 0xbc9dd6792e582523 + .quad 0x3ff93737b0cdc5e5 + .quad 0xbc675fc781b57ebb + .quad 0x3ff95a44cbc8520f + .quad 0xbc764b7c96a5f039 + .quad 0x3ff97d829fde4e50 + .quad 0xbc9d185b7c1b85d0 + .quad 0x3ff9a0f170ca07ba + .quad 0xbc9173bd91cee632 + .quad 0x3ff9c49182a3f090 + .quad 0x3c7c7c46b071f2be + .quad 0x3ff9e86319e32323 + .quad 0x3c7824ca78e64c6e + .quad 0x3ffa0c667b5de565 + .quad 0xbc9359495d1cd532 + .quad 0x3ffa309bec4a2d33 + .quad 0x3c96305c7ddc36ab + .quad 0x3ffa5503b23e255d + .quad 0xbc9d2f6edb8d41e1 + .quad 0x3ffa799e1330b358 + .quad 0x3c9bcb7ecac563c6 + .quad 0x3ffa9e6b5579fdbf + .quad 0x3c90fac90ef7fd31 + .quad 0x3ffac36bbfd3f37a + .quad 0xbc8f9234cae76cd0 + .quad 0x3ffae89f995ad3ad + .quad 0x3c97a1cd345dcc81 + .quad 0x3ffb0e07298db666 + .quad 0xbc9bdef54c80e424 + .quad 0x3ffb33a2b84f15fb + .quad 0xbc62805e3084d707 + .quad 0x3ffb59728de5593a + .quad 0xbc9c71dfbbba6de3 + .quad 0x3ffb7f76f2fb5e47 + .quad 0xbc75584f7e54ac3a + .quad 0x3ffba5b030a1064a + .quad 0xbc9efcd30e54292e + .quad 0x3ffbcc1e904bc1d2 + .quad 0x3c823dd07a2d9e84 + .quad 0x3ffbf2c25bd71e09 + .quad 0xbc9efdca3f6b9c72 + .quad 0x3ffc199bdd85529c + .quad 0x3c811065895048dd + .quad 0x3ffc40ab5fffd07a + .quad 0x3c9b4537e083c60a + .quad 0x3ffc67f12e57d14b + .quad 0x3c92884dff483cac + .quad 0x3ffc8f6d9406e7b5 + .quad 0x3c71acbc48805c44 + .quad 0x3ffcb720dcef9069 + .quad 0x3c7503cbd1e949db + .quad 0x3ffcdf0b555dc3fa + .quad 0xbc8dd83b53829d72 + .quad 0x3ffd072d4a07897c + .quad 0xbc9cbc3743797a9c + .quad 0x3ffd2f87080d89f2 + .quad 0xbc9d487b719d8577 + .quad 0x3ffd5818dcfba487 + .quad 0x3c82ed02d75b3706 + .quad 0x3ffd80e316c98398 + .quad 0xbc911ec18beddfe8 + .quad 0x3ffda9e603db3285 + .quad 0x3c9c2300696db532 + .quad 0x3ffdd321f301b460 + .quad 0x3c92da5778f018c2 + .quad 0x3ffdfc97337b9b5f + .quad 0xbc91a5cd4f184b5b + .quad 0x3ffe264614f5a129 + .quad 0xbc97b627817a1496 + .quad 0x3ffe502ee78b3ff6 + .quad 0x3c839e8980a9cc8f + .quad 0x3ffe7a51fbc74c83 + .quad 0x3c92d522ca0c8de1 + .quad 0x3ffea4afa2a490da + .quad 0xbc9e9c23179c2893 + .quad 0x3ffecf482d8e67f1 + .quad 0xbc9c93f3b411ad8c + .quad 0x3ffefa1bee615a27 + .quad 0x3c9dc7f486a4b6b0 + .quad 0x3fff252b376bba97 + .quad 0x3c93a1a5bf0d8e43 + .quad 0x3fff50765b6e4540 + .quad 0x3c99d3e12dd8a18a + .quad 0x3fff7bfdad9cbe14 + .quad 0xbc9dbb12d0063509 + .quad 0x3fffa7c1819e90d8 + .quad 0x3c874853f3a5931e + .quad 0x3fffd3c22b8f71f1 + .quad 0x3c62eb74966579e7 + +/* log2 polynomial coefficients: + * clv7 */ +double_vector _clv_1 0x3f903950cf599c56 + +/* clv6 */ +double_vector _clv_2 0xbf9b4ea0e9419f52 + +/* clv5 */ +double_vector _clv_3 0x3fa7a334ddfc9f86 + +/* clv4 */ +double_vector _clv_4 0xbfb550472a8bb463 + +/* clv3 */ +double_vector _clv_5 0x3fc47fd462b3b816 + +/* clv2 */ +double_vector _clv_6 0xbfd62e4346694107 + +/* clv1 */ +double_vector _clv_7 0x3e79c3a6966457ee + +/* exponential polynomial coefficients: + * cev5 */ +double_vector _cev_1 0x3f55d87fe78a6731 + +/* cev4 */ +double_vector _cev_2 0x3f83b2ab6fba4e77 + +/* cev3 */ +double_vector _cev_3 0x3fac6b08d704a0bf + +/* cev2 */ +double_vector _cev_4 0x3fcebfbdff82c58e + +/* cev1 */ +double_vector _cev_5 0x3fe62e42fefa39ef + +/* General purpose constants: + * iMantissaMask */ +double_vector _iMantissaMask 0x000fffffffffffff + +/* i3fe7fe0000000000 */ +double_vector _i3fe7fe0000000000 0x3fe7fe0000000000 + +/* dbOne */ +double_vector _dbOne 0x3ff0000000000000 + +/* iffffffff00000000 */ +double_vector _iffffffff00000000 0xffffffff00000000 + +/* db2p20_2p19 = 2^20+2^19 */ +double_vector _db2p20_2p19 0x4138000000000000 + +/* iHighMask */ +double_vector _iHighMask 0xfffffffff8000000 + +/* LHN = -log2(e) truncated to 22 bits */ +double_vector _LHN 0xbff7154740000000 + +/* ifff0000000000000 */ +double_vector _ifff0000000000000 0xfff0000000000000 + +/* db2p45_2p44 */ +double_vector _db2p45_2p44 0x42c8000000000000 + +/* NEG_INF */ +double_vector _NEG_INF 0xfff0000000000000 + +/* NEG_ZERO */ +double_vector _NEG_ZERO 0x8000000000000000 + +/* 2pow52 */ +double_vector _d2pow52 0x4330000000000000 + +/* 1div2pow111 */ +double_vector _d1div2pow111 0x3900000000000000 + +/* HIDELTA */ +float_vector _HIDELTA 0x00100000 + +/* LORANGE */ +float_vector _LORANGE 0x00200000 + +/* ABSMASK */ +float_vector _ABSMASK 0x7fffffff + +/* INF */ +float_vector _INF 0x7f800000 + +/* DOMAINRANGE */ +float_vector _DOMAINRANGE 0x408f3fff + +/* iIndexMask */ +float_vector _iIndexMask 0x000ffe00 + +/* iIndexAdd */ +float_vector _iIndexAdd 0x00000200 + +/* i3fe7fe00 */ +float_vector _i3fe7fe00 0x3fe7fe00 + +/* i2p20_2p19 */ +float_vector _i2p20_2p19 0x41380000 + +/* iOne */ +float_vector _iOne 0x3ff00000 + +/* jIndexMask */ +float_vector _jIndexMask 0x0000007f + .type __svml_dpow_data,@object + .size __svml_dpow_data,.-__svml_dpow_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.h new file mode 100644 index 0000000000..ce90d8546b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_pow_data.h @@ -0,0 +1,104 @@ +/* Offsets for data table for function pow. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_POW_DATA_H +#define D_POW_DATA_H + +#define _hsw_log2_table 0 +#define _hsw_dTe 8256 +#define _hsw_dMantMask 10304 +#define _hsw_dOne 10368 +#define _hsw_dCvtMask 10432 +#define _hsw_dMinNorm 10496 +#define _hsw_dMaxNorm 10560 +#define _hsw_lRndBit 10624 +#define _hsw_lRndMask 10688 +#define _hsw_dc6 10752 +#define _hsw_dc5 10816 +#define _hsw_dc4 10880 +#define _hsw_dc3 10944 +#define _hsw_dc1 11008 +#define _hsw_dc1h 11072 +#define _hsw_dc2 11136 +#define _hsw_dAbsMask 11200 +#define _hsw_dDomainRange 11264 +#define _hsw_dShifter 11328 +#define _hsw_dIndexMask 11392 +#define _hsw_dce4 11456 +#define _hsw_dce3 11520 +#define _hsw_dce2 11584 +#define _hsw_dce1 11648 +#define _rcp_t1 11712 +#define _log2_t1 19968 +#define _exp2_tbl 36416 +#define _clv_1 38464 +#define _clv_2 38528 +#define _clv_3 38592 +#define _clv_4 38656 +#define _clv_5 38720 +#define _clv_6 38784 +#define _clv_7 38848 +#define _cev_1 38912 +#define _cev_2 38976 +#define _cev_3 39040 +#define _cev_4 39104 +#define _cev_5 39168 +#define _iMantissaMask 39232 +#define _i3fe7fe0000000000 39296 +#define _dbOne 39360 +#define _iffffffff00000000 39424 +#define _db2p20_2p19 39488 +#define _iHighMask 39552 +#define _LHN 39616 +#define _ifff0000000000000 39680 +#define _db2p45_2p44 39744 +#define _NEG_INF 39808 +#define _NEG_ZERO 39872 +#define _d2pow52 39936 +#define _d1div2pow111 40000 +#define _HIDELTA 40064 +#define _LORANGE 40128 +#define _ABSMASK 40192 +#define _INF 40256 +#define _DOMAINRANGE 40320 +#define _iIndexMask 40384 +#define _iIndexAdd 40448 +#define _i3fe7fe00 40512 +#define _i2p20_2p19 40576 +#define _iOne 40640 +#define _jIndexMask 40704 + +.macro double_vector offset value +.if .-__svml_dpow_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +.macro float_vector offset value +.if .-__svml_dpow_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin2_core.S new file mode 100644 index 0000000000..85990833be --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin2_core.S @@ -0,0 +1,29 @@ +/* Function sin vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2v_sin) +WRAPPER_IMPL_SSE2 sin +END (_ZGVbN2v_sin) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2v_sin) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core.S new file mode 100644 index 0000000000..7b9211d8c7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core.S @@ -0,0 +1,29 @@ +/* Function sin vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4v_sin) +WRAPPER_IMPL_AVX _ZGVbN2v_sin +END (_ZGVdN4v_sin) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4v_sin) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S new file mode 100644 index 0000000000..3edf88a047 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S @@ -0,0 +1,25 @@ +/* Function sin vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4v_sin) +WRAPPER_IMPL_AVX _ZGVbN2v_sin +END (_ZGVcN4v_sin) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin8_core.S new file mode 100644 index 0000000000..8e67f3cbbe --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sin8_core.S @@ -0,0 +1,25 @@ +/* Function sin vectorized with AVX-512, wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8v_sin) +WRAPPER_IMPL_AVX512 _ZGVdN4v_sin +END (_ZGVeN8v_sin) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos2_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos2_core.S new file mode 100644 index 0000000000..e8023e8e8e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos2_core.S @@ -0,0 +1,110 @@ +/* Function sincos vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVbN2vl8l8_sincos) +WRAPPER_IMPL_SSE2_fFF sincos +END (_ZGVbN2vl8l8_sincos) +libmvec_hidden_def (_ZGVbN2vl8l8_sincos) + +/* SSE2 ISA version as wrapper to scalar (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_SSE2_fFF_vvv callee +#ifndef __ILP32__ + subq $88, %rsp + cfi_adjust_cfa_offset(88) + movaps %xmm0, 64(%rsp) + lea (%rsp), %rdi + movdqa %xmm1, 32(%rdi) + lea 16(%rsp), %rsi + movdqa %xmm2, 32(%rsi) + call JUMPTARGET(\callee) + movsd 72(%rsp), %xmm0 + lea 8(%rsp), %rdi + lea 24(%rsp), %rsi + call JUMPTARGET(\callee) + movq 32(%rsp), %rdx + movq 48(%rsp), %rsi + movq 40(%rsp), %r8 + movq 56(%rsp), %r10 + movq (%rsp), %rax + movq 16(%rsp), %rcx + movq 8(%rsp), %rdi + movq 24(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq %rdi, (%r8) + movq %r9, (%r10) + addq $88, %rsp + cfi_adjust_cfa_offset(-88) + ret +#else + pushq %rbp + .cfi_def_cfa_offset 16 + .cfi_offset 6, -16 + pushq %rbx + .cfi_def_cfa_offset 24 + .cfi_offset 3, -24 + subl $88, %esp + .cfi_def_cfa_offset 112 + leal 64(%rsp), %esi + movaps %xmm1, 32(%esp) + leal 48(%rsp), %edi + movaps %xmm2, 16(%esp) + movq %rsi, %rbp + movq %rdi, %rbx + movaps %xmm0, (%esp) + call JUMPTARGET(\callee) + movupd 8(%esp), %xmm0 + leal 8(%rbp), %esi + leal 8(%rbx), %edi + call JUMPTARGET(\callee) + movdqa 32(%esp), %xmm1 + movsd 48(%esp), %xmm0 + movq %xmm1, %rax + movdqa 16(%esp), %xmm2 + movsd %xmm0, (%eax) + movsd 56(%esp), %xmm0 + pextrd $1, %xmm1, %eax + movsd %xmm0, (%eax) + movsd 64(%esp), %xmm0 + movq %xmm2, %rax + movsd %xmm0, (%eax) + movsd 72(%esp), %xmm0 + pextrd $1, %xmm2, %eax + movsd %xmm0, (%eax) + addl $88, %esp + .cfi_def_cfa_offset 24 + popq %rbx + .cfi_def_cfa_offset 16 + popq %rbp + .cfi_def_cfa_offset 8 + ret +#endif +.endm + +ENTRY (_ZGVbN2vvv_sincos) +WRAPPER_IMPL_SSE2_fFF_vvv sincos +END (_ZGVbN2vvv_sincos) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN2vvv_sincos) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core.S new file mode 100644 index 0000000000..3bcd09b62d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core.S @@ -0,0 +1,152 @@ +/* Function sincos vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVdN4vl8l8_sincos) +WRAPPER_IMPL_AVX_fFF _ZGVbN2vl8l8_sincos +END (_ZGVdN4vl8l8_sincos) +libmvec_hidden_def (_ZGVdN4vl8l8_sincos) + +/* AVX2 ISA version as wrapper to SSE ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX2_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $160, %rsp + vmovupd %ymm0, 128(%rsp) + lea (%rsp), %rdi + vmovdqu %ymm1, 64(%rdi) + vmovdqu %ymm2, 96(%rdi) + lea 32(%rsp), %rsi + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovupd 144(%rsp), %xmm0 + lea 16(%rsp), %rdi + lea 48(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 64(%rsp), %rdx + movq 96(%rsp), %rsi + movq 72(%rsp), %r8 + movq 104(%rsp), %r10 + movq (%rsp), %rax + movq 32(%rsp), %rcx + movq 8(%rsp), %rdi + movq 40(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq 80(%rsp), %rax + movq 112(%rsp), %rcx + movq %rdi, (%r8) + movq %r9, (%r10) + movq 88(%rsp), %rdi + movq 120(%rsp), %r9 + movq 16(%rsp), %r11 + movq 48(%rsp), %rdx + movq 24(%rsp), %rsi + movq 56(%rsp), %r8 + movq %r11, (%rax) + movq %rdx, (%rcx) + movq %rsi, (%rdi) + movq %r8, (%r9) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -80(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -112(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $152, %esp + vmovaps %xmm1, -128(%ebp) + vmovaps %xmm2, -144(%ebp) + vmovapd %ymm0, -176(%ebp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + leal 16(%r12), %esi + vmovapd -160(%ebp), %xmm0 + leal 16(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movq -128(%ebp), %rax + vmovsd -112(%ebp), %xmm0 + vmovdqa -128(%ebp), %xmm5 + vmovdqa -144(%ebp), %xmm1 + vmovsd %xmm0, (%eax) + vmovsd -104(%ebp), %xmm0 + vpextrd $1, %xmm5, %eax + vmovsd %xmm0, (%eax) + movq -120(%ebp), %rax + vmovsd -96(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -88(%ebp), %xmm0 + vpextrd $3, %xmm5, %eax + vmovsd %xmm0, (%eax) + movq -144(%ebp), %rax + vmovsd -80(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -72(%ebp), %xmm0 + vpextrd $1, %xmm1, %eax + vmovsd %xmm0, (%eax) + movq -136(%ebp), %rax + vmovsd -64(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -56(%ebp), %xmm0 + vpextrd $3, %xmm1, %eax + vmovsd %xmm0, (%eax) + addl $152, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVdN4vvv_sincos) +WRAPPER_IMPL_AVX2_fFF_vvv _ZGVbN2vl8l8_sincos +END (_ZGVdN4vvv_sincos) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN4vvv_sincos) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S new file mode 100644 index 0000000000..1164ae7a74 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S @@ -0,0 +1,143 @@ +/* Function sincos vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVcN4vl8l8_sincos) +WRAPPER_IMPL_AVX_fFF _ZGVbN2vl8l8_sincos +END (_ZGVcN4vl8l8_sincos) + +/* AVX ISA version as wrapper to SSE ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + movq %rsp, %rbp + andq $-32, %rsp + subq $160, %rsp + vmovupd %ymm0, 64(%rsp) + lea (%rsp), %rdi + vmovdqu %xmm1, 96(%rdi) + vmovdqu %xmm2, 112(%rdi) + vmovdqu %xmm3, 128(%rdi) + vmovdqu %xmm4, 144(%rdi) + lea 32(%rsp), %rsi + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovdqu 80(%rsp), %xmm0 + lea 16(%rsp), %rdi + lea 48(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 96(%rsp), %rdx + movq 104(%rsp), %rsi + movq 112(%rsp), %r8 + movq 120(%rsp), %r10 + movq (%rsp), %rax + movq 8(%rsp), %rcx + movq 16(%rsp), %rdi + movq 24(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq 128(%rsp), %rax + movq 136(%rsp), %rcx + movq %rdi, (%r8) + movq %r9, (%r10) + movq 144(%rsp), %rdi + movq 152(%rsp), %r9 + movq 32(%rsp), %r11 + movq 40(%rsp), %rdx + movq 48(%rsp), %rsi + movq 56(%rsp), %r8 + movq %r11, (%rax) + movq %rdx, (%rcx) + movq %rsi, (%rdi) + movq %r8, (%r9) + movq %rbp, %rsp + popq %rbp + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -80(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -112(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $152, %esp + vmovaps %xmm1, -128(%ebp) + vmovaps %xmm2, -144(%ebp) + vmovapd %ymm0, -176(%ebp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + leal 16(%r12), %esi + vmovupd -160(%ebp), %xmm0 + leal 16(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movq -128(%ebp), %rax + vmovsd -112(%ebp), %xmm0 + vmovdqa -128(%ebp), %xmm5 + vmovdqa -144(%ebp), %xmm1 + vmovsd %xmm0, (%eax) + vmovsd -104(%ebp), %xmm0 + vpextrd $1, %xmm5, %eax + vmovsd %xmm0, (%eax) + movq -120(%ebp), %rax + vmovsd -96(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -88(%ebp), %xmm0 + vpextrd $3, %xmm5, %eax + vmovsd %xmm0, (%eax) + movq -144(%ebp), %rax + vmovsd -80(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -72(%ebp), %xmm0 + vpextrd $1, %xmm1, %eax + vmovsd %xmm0, (%eax) + movq -136(%ebp), %rax + vmovsd -64(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + vmovsd -56(%ebp), %xmm0 + vpextrd $3, %xmm1, %eax + vmovsd %xmm0, (%eax) + addl $152, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVcN4vvv_sincos) +WRAPPER_IMPL_AVX_fFF_vvv _ZGVbN2vl8l8_sincos +END (_ZGVcN4vvv_sincos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos8_core.S new file mode 100644 index 0000000000..c104539821 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_sincos8_core.S @@ -0,0 +1,224 @@ +/* Function sincos vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_d_wrapper_impl.h" + + .text +ENTRY (_ZGVeN8vl8l8_sincos) +WRAPPER_IMPL_AVX512_fFF _ZGVdN4vl8l8_sincos +END (_ZGVeN8vl8l8_sincos) + +/* AVX512 ISA version as wrapper to AVX2 ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX512_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $320, %rsp + /* Encoding for vmovups %zmm0, 256(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x44 + .byte 0x24 + .byte 0x04 + lea (%rsp), %rdi + /* Encoding for vmovups %zmm1, 128(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4f + .byte 0x02 + /* Encoding for vmovups %zmm2, 192(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x57 + .byte 0x03 + lea 64(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovdqu 288(%rsp), %ymm0 + lea 32(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 128(%rsp), %rdx + movq 192(%rsp), %rsi + movq 136(%rsp), %r8 + movq 200(%rsp), %r10 + movq (%rsp), %rax + movq 64(%rsp), %rcx + movq 8(%rsp), %rdi + movq 72(%rsp), %r9 + movq %rax, (%rdx) + movq %rcx, (%rsi) + movq 144(%rsp), %rax + movq 208(%rsp), %rcx + movq %rdi, (%r8) + movq %r9, (%r10) + movq 152(%rsp), %rdi + movq 216(%rsp), %r9 + movq 16(%rsp), %r11 + movq 80(%rsp), %rdx + movq 24(%rsp), %rsi + movq 88(%rsp), %r8 + movq %r11, (%rax) + movq %rdx, (%rcx) + movq 160(%rsp), %r11 + movq 224(%rsp), %rdx + movq %rsi, (%rdi) + movq %r8, (%r9) + movq 168(%rsp), %rsi + movq 232(%rsp), %r8 + movq 32(%rsp), %r10 + movq 96(%rsp), %rax + movq 40(%rsp), %rcx + movq 104(%rsp), %rdi + movq %r10, (%r11) + movq %rax, (%rdx) + movq 176(%rsp), %r10 + movq 240(%rsp), %rax + movq %rcx, (%rsi) + movq %rdi, (%r8) + movq 184(%rsp), %rcx + movq 248(%rsp), %rdi + movq 48(%rsp), %r9 + movq 112(%rsp), %r11 + movq 56(%rsp), %rdx + movq 120(%rsp), %rsi + movq %r9, (%r10) + movq %r11, (%rax) + movq %rdx, (%rcx) + movq %rsi, (%rdi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-64, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -112(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -176(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $280, %esp + vmovdqa %ymm1, -208(%ebp) + vmovdqa %ymm2, -240(%ebp) + /* Encoding for vmovapd %zmm0, -304(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0xfd + .byte 0x48 + .byte 0x29 + .byte 0x85 + .byte 0xd0 + .byte 0xfe + .byte 0xff + .byte 0xff + call HIDDEN_JUMPTARGET(\callee) + leal 32(%r12), %esi + vmovupd -272(%ebp), %ymm0 + leal 32(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movl -208(%ebp), %eax + vmovsd -176(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -204(%ebp), %eax + vmovsd -168(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -200(%ebp), %eax + vmovsd -160(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -196(%ebp), %eax + vmovsd -152(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -192(%ebp), %eax + vmovsd -144(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -188(%ebp), %eax + vmovsd -136(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -184(%ebp), %eax + vmovsd -128(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -180(%ebp), %eax + vmovsd -120(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -240(%ebp), %eax + vmovsd -112(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -236(%ebp), %eax + vmovsd -104(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -232(%ebp), %eax + vmovsd -96(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -228(%ebp), %eax + vmovsd -88(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -224(%ebp), %eax + vmovsd -80(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -220(%ebp), %eax + vmovsd -72(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -216(%ebp), %eax + vmovsd -64(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + movl -212(%ebp), %eax + vmovsd -56(%ebp), %xmm0 + vmovsd %xmm0, (%eax) + addl $280, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVeN8vvv_sincos) +WRAPPER_IMPL_AVX512_fFF_vvv _ZGVdN4vl8l8_sincos +END (_ZGVeN8vvv_sincos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.S new file mode 100644 index 0000000000..f7cf6c0a08 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.S @@ -0,0 +1,130 @@ +/* Data for vectorized sin, cos, sincos. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_d_trig_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations. + The table may contain polynomial, reduction, lookup + coefficients and other constants obtained through different + methods of research and experimental work. + */ + .globl __svml_d_trig_data +__svml_d_trig_data: + +/* General purpose constants: + absolute value mask + */ +double_vector __dAbsMask 0x7fffffffffffffff + +/* working range threshold */ +double_vector __dRangeVal 0x4160000000000000 + +/* working range threshold */ +double_vector __dRangeVal_sin 0x4170000000000000 + +/* PI/2 */ +double_vector __dHalfPI 0x3ff921fb54442d18 + +/* 1/PI */ +double_vector __dInvPI 0x3fd45f306dc9c883 + +/* right-shifter constant */ +double_vector __dRShifter 0x4338000000000000 + +/* 0.0 */ +double_vector __dZero 0x0000000000000000 + +/* -0.0 */ +double_vector __lNZero 0x8000000000000000 + +/* 0.5 */ +double_vector __dOneHalf 0x3fe0000000000000 + +/* Range reduction PI-based constants: + PI high part + */ +double_vector __dPI1 0x400921fb40000000 + +/* PI mid part 1 */ +double_vector __dPI2 0x3e84442d00000000 + +/* PI mid part 2 */ +double_vector __dPI3 0x3d08469880000000 + +/* PI low part */ +double_vector __dPI4 0x3b88cc51701b839a + +/* Range reduction PI-based constants if FMA available: + PI high part (FMA available) + */ +double_vector __dPI1_FMA 0x400921fb54442d18 + +/* PI mid part (FMA available) */ +double_vector __dPI2_FMA 0x3ca1a62633145c06 + +/* PI low part (FMA available) */ +double_vector __dPI3_FMA 0x395c1cd129024e09 + +/* HalfPI1 */ +double_vector __dHalfPI1 0x3ff921fc00000000 + +/* HalfPI2 */ +double_vector __dHalfPI2 0xbea5777a00000000 + +/* HalfPI3 */ +double_vector __dHalfPI3 0xbd473dcc00000000 + +/* HalfPI4 */ +double_vector __dHalfPI4 0x3bf898cc51701b84 + +/* Polynomial coefficients (relative error 2^(-52.115)): */ +double_vector __dC1 0xbfc55555555554a7 +double_vector __dC2 0x3f8111111110a4a8 +double_vector __dC3 0xbf2a01a019a5b86d +double_vector __dC4 0x3ec71de38030fea0 +double_vector __dC5 0xbe5ae63546002231 +double_vector __dC6 0x3de60e6857a2f220 +double_vector __dC7 0xbd69f0d60811aac8 + +/* Polynomial coefficients (relative error 2^(-52.115)): */ +double_vector __dC1_sin 0xbfc55555555554a8 +double_vector __dC2_sin 0x3f8111111110a573 +double_vector __dC3_sin 0xbf2a01a019a659dd +double_vector __dC4_sin 0x3ec71de3806add1a +double_vector __dC5_sin 0xbe5ae6355aaa4a53 +double_vector __dC6_sin 0x3de60e6bee01d83e +double_vector __dC7_sin 0xbd69f1517e9f65f0 + +/* + Additional constants: + absolute value mask + */ +/* right-shifer for low accuracy version */ +double_vector __dRShifter_la 0x4330000000000000 + +/* right-shifer-1.0 for low accuracy version */ +double_vector __dRShifterm5_la 0x432fffffffffffff + +/* right-shifer with low mask for low accuracy version */ +double_vector __dRXmax_la 0x43300000007ffffe + + .type __svml_d_trig_data,@object + .size __svml_d_trig_data,.-__svml_d_trig_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.h new file mode 100644 index 0000000000..ccdff7edb8 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_trig_data.h @@ -0,0 +1,72 @@ +/* Offsets for data table for vectorized sin, cos, sincos. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_TRIG_DATA_H +#define D_TRIG_DATA_H + +#define __dAbsMask 0 +#define __dRangeVal 64 +#define __dRangeVal_sin 64*2 +#define __dHalfPI 64*3 +#define __dInvPI 64*4 +#define __dRShifter 64*5 +#define __dZero 64*6 +#define __lNZero 64*7 +#define __dOneHalf 64*8 +#define __dPI1 64*9 +#define __dPI2 64*10 +#define __dPI3 64*11 +#define __dPI4 64*12 +#define __dPI1_FMA 64*13 +#define __dPI2_FMA 64*14 +#define __dPI3_FMA 64*15 +#define __dHalfPI1 64*16 +#define __dHalfPI2 64*17 +#define __dHalfPI3 64*18 +#define __dHalfPI4 64*19 +#define __dC1 64*20 +#define __dC2 64*21 +#define __dC3 64*22 +#define __dC4 64*23 +#define __dC5 64*24 +#define __dC6 64*25 +#define __dC7 64*26 +#define __dC1_sin 64*27 +#define __dC2_sin 64*28 +#define __dC3_sin 64*29 +#define __dC4_sin 64*30 +#define __dC5_sin 64*31 +#define __dC6_sin 64*32 +#define __dC7_sin 64*33 +#define __dRShifter_la 64*34 +#define __dRShifterm5_la 64*35 +#define __dRXmax_la 64*36 +#define __dAbsMask_la __dAbsMask +#define __dInvPI_la __dInvPI +#define __dSignMask __lNZero + +.macro double_vector offset value +.if .-__svml_d_trig_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h new file mode 100644 index 0000000000..625eb6642b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h @@ -0,0 +1,335 @@ +/* Wrapper implementations of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2 callee + subq $40, %rsp + cfi_adjust_cfa_offset(40) + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + movsd %xmm0, 16(%rsp) + movsd 8(%rsp), %xmm0 + call JUMPTARGET(\callee) + movsd 16(%rsp), %xmm1 + movsd %xmm0, 24(%rsp) + unpcklpd %xmm0, %xmm1 + movaps %xmm1, %xmm0 + addq $40, %rsp + cfi_adjust_cfa_offset(-40) + ret +.endm + +/* 2 argument SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2_ff callee + subq $56, %rsp + cfi_adjust_cfa_offset(56) + movaps %xmm0, (%rsp) + movaps %xmm1, 16(%rsp) + call JUMPTARGET(\callee) + movsd %xmm0, 32(%rsp) + movsd 8(%rsp), %xmm0 + movsd 24(%rsp), %xmm1 + call JUMPTARGET(\callee) + movsd 32(%rsp), %xmm1 + movsd %xmm0, 40(%rsp) + unpcklpd %xmm0, %xmm1 + movaps %xmm1, %xmm0 + addq $56, %rsp + cfi_adjust_cfa_offset(-56) + ret +.endm + +/* 3 argument SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + pushq %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + movq %rdi, %rbp + movq %rsi, %rbx + subq $40, %rsp + cfi_adjust_cfa_offset(40) + leaq 16(%rsp), %rsi + leaq 24(%rsp), %rdi + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + leaq 16(%rsp), %rsi + leaq 24(%rsp), %rdi + movsd 24(%rsp), %xmm0 + movapd (%rsp), %xmm1 + movsd %xmm0, 0(%rbp) + unpckhpd %xmm1, %xmm1 + movsd 16(%rsp), %xmm0 + movsd %xmm0, (%rbx) + movapd %xmm1, %xmm0 + call JUMPTARGET(\callee) + movsd 24(%rsp), %xmm0 + movsd %xmm0, 8(%rbp) + movsd 16(%rsp), %xmm0 + movsd %xmm0, 8(%rbx) + addq $40, %rsp + cfi_adjust_cfa_offset(-40) + popq %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $32, %rsp + vextractf128 $1, %ymm0, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovapd %xmm0, 16(%rsp) + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovapd %xmm0, %xmm1 + vmovapd 16(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $64, %rsp + vextractf128 $1, %ymm0, 16(%rsp) + vextractf128 $1, %ymm1, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 32(%rsp) + vmovaps 16(%rsp), %xmm0 + vmovaps (%rsp), %xmm1 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 32(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + pushq %r14 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r14, 0) + subq $48, %rsp + movq %rsi, %r14 + movq %rdi, %r13 + vextractf128 $1, %ymm0, 32(%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %xmm0 + lea (%rsp), %rdi + lea 16(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovapd (%rsp), %xmm0 + vmovapd 16(%rsp), %xmm1 + vmovapd %xmm0, 16(%r13) + vmovapd %xmm1, 16(%r14) + addq $48, %rsp + popq %r14 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r14) + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512 callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $128, %rsp +/* Below is encoding for vmovups %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x04 + .byte 0x24 + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 64(%rsp) + vmovupd 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 96(%rsp) +/* Below is encoding for vmovups 64(%rsp), %zmm0. */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x10 + .byte 0x44 + .byte 0x24 + .byte 0x01 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $192, %rsp +/* Below is encoding for vmovups %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x04 + .byte 0x24 +/* Below is encoding for vmovups %zmm1, 64(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4c + .byte 0x24 + .byte 0x01 + vmovupd (%rsp), %ymm0 + vmovupd 64(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 128(%rsp) + vmovupd 32(%rsp), %ymm0 + vmovupd 96(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 160(%rsp) +/* Below is encoding for vmovups 128(%rsp), %zmm0. */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x10 + .byte 0x44 + .byte 0x24 + .byte 0x02 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + pushq %r12 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r12, 0) + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + subq $176, %rsp + movq %rsi, %r13 +/* Below is encoding for vmovups %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x04 + .byte 0x24 + movq %rdi, %r12 + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd 32(%rsp), %ymm0 + lea 64(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovupd 64(%rsp), %ymm0 + vmovupd 96(%rsp), %ymm1 + vmovupd %ymm0, 32(%r12) + vmovupd %ymm1, 32(%r13) + vzeroupper + addq $176, %rsp + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + popq %r12 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r12) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_finite_alias.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_finite_alias.S new file mode 100644 index 0000000000..7e39e7801d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_finite_alias.S @@ -0,0 +1,58 @@ +/* These aliases added as workaround to exclude unnecessary symbol + aliases in libmvec.so while compiler creates the vector names + based on scalar asm name. Corresponding discussion is at + <https://gcc.gnu.org/ml/gcc/2015-06/msg00173.html>. + Copyright (C) 2015-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ALIAS_IMPL(alias, target) \ +ENTRY (alias); \ + jmp *target@GOTPCREL(%rip); \ +END (alias) + + .text +ALIAS_IMPL (_ZGVbN2v___log_finite, _ZGVbN2v_log) +ALIAS_IMPL (_ZGVcN4v___log_finite, _ZGVcN4v_log) +ALIAS_IMPL (_ZGVdN4v___log_finite, _ZGVdN4v_log) +ALIAS_IMPL (_ZGVeN8v___log_finite, _ZGVeN8v_log) + +ALIAS_IMPL (_ZGVbN4v___logf_finite, _ZGVbN4v_logf) +ALIAS_IMPL (_ZGVcN8v___logf_finite, _ZGVcN8v_logf) +ALIAS_IMPL (_ZGVdN8v___logf_finite, _ZGVdN8v_logf) +ALIAS_IMPL (_ZGVeN16v___logf_finite, _ZGVeN16v_logf) + +ALIAS_IMPL (_ZGVbN2v___exp_finite, _ZGVbN2v_exp) +ALIAS_IMPL (_ZGVcN4v___exp_finite, _ZGVcN4v_exp) +ALIAS_IMPL (_ZGVdN4v___exp_finite, _ZGVdN4v_exp) +ALIAS_IMPL (_ZGVeN8v___exp_finite, _ZGVeN8v_exp) + +ALIAS_IMPL (_ZGVbN4v___expf_finite, _ZGVbN4v_expf) +ALIAS_IMPL (_ZGVcN8v___expf_finite, _ZGVcN8v_expf) +ALIAS_IMPL (_ZGVdN8v___expf_finite, _ZGVdN8v_expf) +ALIAS_IMPL (_ZGVeN16v___expf_finite, _ZGVeN16v_expf) + +ALIAS_IMPL (_ZGVbN2vv___pow_finite, _ZGVbN2vv_pow) +ALIAS_IMPL (_ZGVcN4vv___pow_finite, _ZGVcN4vv_pow) +ALIAS_IMPL (_ZGVdN4vv___pow_finite, _ZGVdN4vv_pow) +ALIAS_IMPL (_ZGVeN8vv___pow_finite, _ZGVeN8vv_pow) + +ALIAS_IMPL (_ZGVbN4vv___powf_finite, _ZGVbN4vv_powf) +ALIAS_IMPL (_ZGVcN8vv___powf_finite, _ZGVcN8vv_powf) +ALIAS_IMPL (_ZGVdN8vv___powf_finite, _ZGVdN8vv_powf) +ALIAS_IMPL (_ZGVeN16vv___powf_finite, _ZGVeN16vv_powf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf16_core.S new file mode 100644 index 0000000000..127eb82ae0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf16_core.S @@ -0,0 +1,25 @@ +/* Function cosf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_cosf) +WRAPPER_IMPL_AVX512 _ZGVdN8v_cosf +END (_ZGVeN16v_cosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf4_core.S new file mode 100644 index 0000000000..800766cc4e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf4_core.S @@ -0,0 +1,29 @@ +/* Function cosf vectorized with SSE2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4v_cosf) +WRAPPER_IMPL_SSE2 cosf +END (_ZGVbN4v_cosf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4v_cosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core.S new file mode 100644 index 0000000000..46c588074c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core.S @@ -0,0 +1,29 @@ +/* Function cosf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8v_cosf) +WRAPPER_IMPL_AVX _ZGVbN4v_cosf +END (_ZGVdN8v_cosf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8v_cosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S new file mode 100644 index 0000000000..459685ee6a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S @@ -0,0 +1,25 @@ +/* Function cosf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVcN8v_cosf) +WRAPPER_IMPL_AVX _ZGVbN4v_cosf +END (_ZGVcN8v_cosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf16_core.S new file mode 100644 index 0000000000..a32f03e1a7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf16_core.S @@ -0,0 +1,25 @@ +/* Function expf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_expf) +WRAPPER_IMPL_AVX512 _ZGVdN8v_expf +END (_ZGVeN16v_expf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf4_core.S new file mode 100644 index 0000000000..c8ec8f97b7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf4_core.S @@ -0,0 +1,30 @@ +/* Function expf vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4v_expf) +WRAPPER_IMPL_SSE2 __expf_finite +END (_ZGVbN4v_expf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4v_expf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core.S new file mode 100644 index 0000000000..f5e1be62eb --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core.S @@ -0,0 +1,29 @@ +/* Function expf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8v_expf) +WRAPPER_IMPL_AVX _ZGVbN4v_expf +END (_ZGVdN8v_expf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8v_expf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S new file mode 100644 index 0000000000..f3557f8c19 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S @@ -0,0 +1,25 @@ +/* Function expf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY(_ZGVcN8v_expf) +WRAPPER_IMPL_AVX _ZGVbN4v_expf +END(_ZGVcN8v_expf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.S new file mode 100644 index 0000000000..226104f5f9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.S @@ -0,0 +1,63 @@ +/* Data for function expf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_s_expf_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function expf. + The table may contain polynomial, reduction, lookup coefficients and + other coefficients obtained through different methods of research and + experimental work. */ + + .globl __svml_sexp_data +__svml_sexp_data: + +/* Range reduction coefficients: + * log(2) inverted */ +float_vector __sInvLn2 0x3fb8aa3b + +/* right shifter constant */ +float_vector __sShifter 0x4b400000 + +/* log(2) high part */ +float_vector __sLn2hi 0x3f317200 + +/* log(2) low part */ +float_vector __sLn2lo 0x35bfbe8e + +/* bias */ +float_vector __iBias 0x0000007f + +/* Polynomial coefficients: + * Here we approximate 2^x on [-0.5, 0.5] */ +float_vector __sPC0 0x3f800000 +float_vector __sPC1 0x3f7ffffe +float_vector __sPC2 0x3effff34 +float_vector __sPC3 0x3e2aacac +float_vector __sPC4 0x3d2b8392 +float_vector __sPC5 0x3c07d9fe + +/* absolute value mask */ +float_vector __iAbsMask 0x7fffffff + +/* working domain range */ +float_vector __iDomainRange 0x42aeac4f + .type __svml_sexp_data,@object + .size __svml_sexp_data,.-__svml_sexp_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.h new file mode 100644 index 0000000000..5badb84b14 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_expf_data.h @@ -0,0 +1,45 @@ +/* Offsets for data table for vector function expf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef S_EXPF_DATA_H +#define S_EXPF_DATA_H + +#define __sInvLn2 0 +#define __sShifter 64 +#define __sLn2hi 128 +#define __sLn2lo 192 +#define __iBias 256 +#define __sPC0 320 +#define __sPC1 384 +#define __sPC2 448 +#define __sPC3 512 +#define __sPC4 576 +#define __sPC5 640 +#define __iAbsMask 704 +#define __iDomainRange 768 + +.macro float_vector offset value +.if .-__svml_sexp_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf16_core.S new file mode 100644 index 0000000000..081c449f42 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf16_core.S @@ -0,0 +1,25 @@ +/* Function logf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_logf) +WRAPPER_IMPL_AVX512 _ZGVdN8v_logf +END (_ZGVeN16v_logf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf4_core.S new file mode 100644 index 0000000000..fab301db1e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf4_core.S @@ -0,0 +1,30 @@ +/* Function logf vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4v_logf) +WRAPPER_IMPL_SSE2 __logf_finite +END (_ZGVbN4v_logf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4v_logf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core.S new file mode 100644 index 0000000000..e1aa2f363c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core.S @@ -0,0 +1,29 @@ +/* Function logf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8v_logf) +WRAPPER_IMPL_AVX _ZGVbN4v_logf +END (_ZGVdN8v_logf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8v_logf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S new file mode 100644 index 0000000000..e74e47c152 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S @@ -0,0 +1,25 @@ +/* Function logf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY(_ZGVcN8v_logf) +WRAPPER_IMPL_AVX _ZGVbN4v_logf +END(_ZGVcN8v_logf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.S new file mode 100644 index 0000000000..487c439120 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.S @@ -0,0 +1,102 @@ +/* Data for vector function logf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_s_logf_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function logf. + The table may contain polynomial, reduction, lookup coefficients and + other coefficients obtained through different methods of research and + experimental work. */ + + .globl __svml_slog_data +__svml_slog_data: + +/* Polynomial sPoly[] coefficients: + * -5.0000000000000000000000000e-01 */ +float_vector _sPoly_1 0xbf000000 + +/* 3.3336564898490905761718750e-01 */ +float_vector _sPoly_2 0x3eaaaee7 + +/* -2.5004664063453674316406250e-01 */ +float_vector _sPoly_3 0xbe80061d + +/* 1.9822503626346588134765625e-01 */ +float_vector _sPoly_4 0x3e4afb81 + +/* -1.6462457180023193359375000e-01 */ +float_vector _sPoly_5 0xbe289358 + +/* 1.6964881122112274169921875e-01 */ +float_vector _sPoly_6 0x3e2db86b + +/* -1.5177205204963684082031250e-01 */ +float_vector _sPoly_7 0xbe1b6a22 + +/* Constant for work range check: Delta 80000000-7f800000 */ +float_vector _iHiDelta 0x00800000 + +/* Constant for work range check: 00800000 + Delta */ +float_vector _iLoRange 0x01000000 + +/* Mantissa break point SP 2/3 */ +float_vector _iBrkValue 0x3f2aaaab + +/* SP significand mask */ +float_vector _iOffExpoMask 0x007fffff + +/* 1.0f */ +float_vector _sOne 0x3f800000 + +/* SP log(2) */ +float_vector _sLn2 0x3f317218 + +/* SP infinity, +/- */ +.if .-__svml_slog_data != _sInfs +.err +.endif + .long 0x7f800000 + .long 0xff800000 + .rept 56 + .byte 0 + .endr + +/* SP one, +/- */ +.if .-__svml_slog_data != _sOnes +.err +.endif + .long 0x3f800000 + .long 0xbf800000 + .rept 56 + .byte 0 + .endr + +/* SP zero +/- */ +.if .-__svml_slog_data != _sZeros +.err +.endif + .long 0x00000000 + .long 0x80000000 + .rept 56 + .byte 0 + .endr + .type __svml_slog_data,@object + .size __svml_slog_data,.-__svml_slog_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.h new file mode 100644 index 0000000000..52612e3ae3 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_logf_data.h @@ -0,0 +1,48 @@ +/* Offsets for data table for vectorized function logf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef S_LOGF_DATA_H +#define S_LOGF_DATA_H + +#define _sPoly_1 0 +#define _sPoly_2 64 +#define _sPoly_3 128 +#define _sPoly_4 192 +#define _sPoly_5 256 +#define _sPoly_6 320 +#define _sPoly_7 384 +#define _iHiDelta 448 +#define _iLoRange 512 +#define _iBrkValue 576 +#define _iOffExpoMask 640 +#define _sOne 704 +#define _sLn2 768 +#define _sInfs 832 +#define _sOnes 896 +#define _sZeros 960 + +.macro float_vector offset value +.if .-__svml_slog_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf16_core.S new file mode 100644 index 0000000000..ac041df507 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf16_core.S @@ -0,0 +1,25 @@ +/* Function powf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16vv_powf) +WRAPPER_IMPL_AVX512_ff _ZGVdN8vv_powf +END (_ZGVeN16vv_powf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf4_core.S new file mode 100644 index 0000000000..61d336e160 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf4_core.S @@ -0,0 +1,29 @@ +/* Function powf vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4vv_powf) +WRAPPER_IMPL_SSE2_ff __powf_finite +END (_ZGVbN4vv_powf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4vv_powf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core.S new file mode 100644 index 0000000000..2ae28051c5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core.S @@ -0,0 +1,29 @@ +/* Function powf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8vv_powf) +WRAPPER_IMPL_AVX_ff _ZGVbN4vv_powf +END (_ZGVdN8vv_powf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8vv_powf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S new file mode 100644 index 0000000000..0522865ef1 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S @@ -0,0 +1,25 @@ +/* Function powf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY(_ZGVcN8vv_powf) +WRAPPER_IMPL_AVX_ff _ZGVbN4vv_powf +END(_ZGVcN8vv_powf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.S new file mode 100644 index 0000000000..630baa62a8 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.S @@ -0,0 +1,3759 @@ +/* Data for function powf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_s_powf_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function powf. + The table may contain polynomial, reduction, lookup coefficients and + other coefficients obtained through different methods of research + and experimental work. */ + + .globl __svml_spow_data +__svml_spow_data: + +/* General purpose constants for H+L multiplication: + * NMINNORM */ +float_vector _NMINNORM 0x80800000 + +/* NMAXVAL */ +float_vector _NMAXVAL 0xfeffffff + +/* INF */ +float_vector _INF 0x7f800000 + +/* ABSMASK */ +float_vector _ABSMASK 0x7fffffff + +/* DOMAINRANGE */ +float_vector _DOMAINRANGE 0x42ae9a00 + +/* Log(2) lookup High+Low table for logarithmic part */ +.if .-__svml_spow_data != _Log_HA_table +.err +.endif + .quad 0xc086232bdd7a8300 + .quad 0xbe1ce91eef3fb100 + .quad 0xc086232fdc7ad828 + .quad 0xbe1cefcffda73b6a + .quad 0xc0862333d97d2ba0 + .quad 0xbe1cef406748f1ff + .quad 0xc0862337d48378e0 + .quad 0xbe1cef2a9429925a + .quad 0xc086233bcd8fb878 + .quad 0xbe1cf138d17ebecb + .quad 0xc086233fc4a3e018 + .quad 0xbe1ceff2dbbbb29e + .quad 0xc0862343b9c1e270 + .quad 0xbe1cf1a42aae437b + .quad 0xc0862347acebaf68 + .quad 0xbe1cef3b152048af + .quad 0xc086234b9e2333f0 + .quad 0xbe1cef20e127805e + .quad 0xc086234f8d6a5a30 + .quad 0xbe1cf00ad6052cf4 + .quad 0xc08623537ac30980 + .quad 0xbe1cefc4642ee597 + .quad 0xc0862357662f2660 + .quad 0xbe1cf1f277d36e16 + .quad 0xc086235b4fb092a0 + .quad 0xbe1ceed009e8d8e6 + .quad 0xc086235f37492d28 + .quad 0xbe1cf1e4038cb362 + .quad 0xc08623631cfad250 + .quad 0xbe1cf0b0873b8557 + .quad 0xc086236700c75b98 + .quad 0xbe1cf15bb3227c0b + .quad 0xc086236ae2b09fe0 + .quad 0xbe1cf151ef8ca9ed + .quad 0xc086236ec2b87358 + .quad 0xbe1cefe1dc2cd2ed + .quad 0xc0862372a0e0a780 + .quad 0xbe1cf0d1eec5454f + .quad 0xc08623767d2b0b48 + .quad 0xbe1ceeefd570bbce + .quad 0xc086237a57996af0 + .quad 0xbe1cee99ae91b3a7 + .quad 0xc086237e302d9028 + .quad 0xbe1cf0412830fbd1 + .quad 0xc086238206e94218 + .quad 0xbe1ceee898588610 + .quad 0xc0862385dbce4548 + .quad 0xbe1cee9a1fbcaaea + .quad 0xc0862389aede5bc0 + .quad 0xbe1ceed8e7cc1ad6 + .quad 0xc086238d801b4500 + .quad 0xbe1cf10c8d059da6 + .quad 0xc08623914f86be18 + .quad 0xbe1ceee6c63a8165 + .quad 0xc08623951d228180 + .quad 0xbe1cf0c3592d2ff1 + .quad 0xc0862398e8f04758 + .quad 0xbe1cf0026cc4cb1b + .quad 0xc086239cb2f1c538 + .quad 0xbe1cf15d48d8e670 + .quad 0xc08623a07b28ae60 + .quad 0xbe1cef359363787c + .quad 0xc08623a44196b390 + .quad 0xbe1cefdf1ab2e82c + .quad 0xc08623a8063d8338 + .quad 0xbe1cefe43c02aa84 + .quad 0xc08623abc91ec960 + .quad 0xbe1cf044f5ae35b7 + .quad 0xc08623af8a3c2fb8 + .quad 0xbe1cf0b0b4001e1b + .quad 0xc08623b349975d98 + .quad 0xbe1cf1bae76dfbcf + .quad 0xc08623b70731f810 + .quad 0xbe1cef0a72e13a62 + .quad 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0x3fc7d6903caf5ad0 + .quad 0x3fc7b0091651528c + .quad 0x3fc7898d85444c73 + .quad 0x3fc7631d82935a86 + .quad 0x3fc73cb9074fd14d + .quad 0x3fc716600c914054 + .quad 0x3fc6f0128b756abc + .quad 0x3fc6c9d07d203fc7 + .quad 0x3fc6a399dabbd383 + .quad 0x3fc67d6e9d785771 + .quad 0x3fc6574ebe8c133a + .quad 0x3fc6313a37335d76 + .quad 0x3fc60b3100b09476 + .quad 0x3fc5e533144c1719 + .quad 0x3fc5bf406b543db2 + .quad 0x3fc59958ff1d52f1 + .quad 0x3fc5737cc9018cdd + .quad 0x3fc54dabc26105d2 + .quad 0x3fc527e5e4a1b58d + .quad 0x3fc5022b292f6a45 + .quad 0x3fc4dc7b897bc1c8 + .quad 0x3fc4b6d6fefe22a4 + .quad 0x3fc4913d8333b561 + .quad 0x3fc46baf0f9f5db7 + .quad 0x3fc4462b9dc9b3dc + .quad 0x3fc420b32740fdd4 + .quad 0x3fc3fb45a59928cc + .quad 0x3fc3d5e3126bc27f + .quad 0x3fc3b08b6757f2a9 + .quad 0x3fc38b3e9e027479 + .quad 0x3fc365fcb0159016 + .quad 0x3fc340c59741142e + .quad 0x3fc31b994d3a4f85 + .quad 0x3fc2f677cbbc0a96 + .quad 0x3fc2d1610c86813a + .quad 0x3fc2ac55095f5c59 + .quad 0x3fc28753bc11aba5 + .quad 0x3fc2625d1e6ddf57 + .quad 0x3fc23d712a49c202 + .quad 0x3fc2188fd9807263 + .quad 0x3fc1f3b925f25d41 + .quad 0x3fc1ceed09853752 + .quad 0x3fc1aa2b7e23f72a + .quad 0x3fc185747dbecf34 + .quad 0x3fc160c8024b27b1 + .quad 0x3fc13c2605c398c3 + .quad 0x3fc1178e8227e47c + .quad 0x3fc0f301717cf0fb + .quad 0x3fc0ce7ecdccc28d + .quad 0x3fc0aa06912675d5 + .quad 0x3fc08598b59e3a07 + .quad 0x3fc06135354d4b18 + .quad 0x3fc03cdc0a51ec0d + .quad 0x3fc0188d2ecf6140 + .quad 0x3fbfe89139dbd566 + .quad 0x3fbfa01c9db57ce2 + .quad 0x3fbf57bc7d9005db + .quad 0x3fbf0f70cdd992e3 + .quad 0x3fbec739830a1120 + .quad 0x3fbe7f1691a32d3e + .quad 0x3fbe3707ee30487b + .quad 0x3fbdef0d8d466db9 + .quad 0x3fbda727638446a2 + .quad 0x3fbd5f55659210e2 + .quad 0x3fbd179788219364 + .quad 0x3fbccfedbfee13a8 + .quad 0x3fbc885801bc4b23 + .quad 0x3fbc40d6425a5cb1 + .quad 0x3fbbf968769fca11 + .quad 0x3fbbb20e936d6974 + .quad 0x3fbb6ac88dad5b1c + .quad 0x3fbb23965a52ff00 + .quad 0x3fbadc77ee5aea8c + .quad 0x3fba956d3ecade63 + .quad 0x3fba4e7640b1bc38 + .quad 0x3fba0792e9277cac + .quad 0x3fb9c0c32d4d2548 + .quad 0x3fb97a07024cbe74 + .quad 0x3fb9335e5d594989 + .quad 0x3fb8ecc933aeb6e8 + .quad 0x3fb8a6477a91dc29 + .quad 0x3fb85fd927506a48 + .quad 0x3fb8197e2f40e3f0 + .quad 0x3fb7d33687c293c9 + .quad 0x3fb78d02263d82d3 + .quad 0x3fb746e100226ed9 + .quad 0x3fb700d30aeac0e1 + .quad 0x3fb6bad83c1883b6 + .quad 0x3fb674f089365a7a + .quad 0x3fb62f1be7d77743 + .quad 0x3fb5e95a4d9791cb + .quad 0x3fb5a3abb01ade25 + .quad 0x3fb55e10050e0384 + .quad 0x3fb518874226130a + .quad 0x3fb4d3115d207eac + .quad 0x3fb48dae4bc31018 + .quad 0x3fb4485e03dbdfad + .quad 0x3fb403207b414b7f + .quad 0x3fb3bdf5a7d1ee64 + .quad 0x3fb378dd7f749714 + .quad 0x3fb333d7f8183f4b + .quad 0x3fb2eee507b40301 + .quad 0x3fb2aa04a44717a5 + .quad 0x3fb26536c3d8c369 + .quad 0x3fb2207b5c78549e + .quad 0x3fb1dbd2643d190b + .quad 0x3fb1973bd1465567 + .quad 0x3fb152b799bb3cc9 + .quad 0x3fb10e45b3cae831 + .quad 0x3fb0c9e615ac4e17 + .quad 0x3fb08598b59e3a07 + .quad 0x3fb0415d89e74444 + .quad 0x3faffa6911ab9301 + .quad 0x3faf723b517fc523 + .quad 0x3faeea31c006b87c + .quad 0x3fae624c4a0b5e1b + .quad 0x3fadda8adc67ee4e + .quad 0x3fad52ed6405d86f + .quad 0x3faccb73cdddb2cc + .quad 0x3fac441e06f72a9e + .quad 0x3fabbcebfc68f420 + .quad 0x3fab35dd9b58baad + .quad 0x3faaaef2d0fb10fc + .quad 0x3faa282b8a936171 + .quad 0x3fa9a187b573de7c + .quad 0x3fa91b073efd7314 + .quad 0x3fa894aa149fb343 + .quad 0x3fa80e7023d8ccc4 + .quad 0x3fa788595a3577ba + .quad 0x3fa70265a550e777 + .quad 0x3fa67c94f2d4bb58 + .quad 0x3fa5f6e73078efb8 + .quad 0x3fa5715c4c03ceef + .quad 0x3fa4ebf43349e26f + .quad 0x3fa466aed42de3ea + .quad 0x3fa3e18c1ca0ae92 + .quad 0x3fa35c8bfaa1306b + .quad 0x3fa2d7ae5c3c5bae + .quad 0x3fa252f32f8d183f + .quad 0x3fa1ce5a62bc353a + .quad 0x3fa149e3e4005a8d + .quad 0x3fa0c58fa19dfaaa + .quad 0x3fa0415d89e74444 + .quad 0x3f9f7a9b16782856 + .quad 0x3f9e72bf2813ce51 + .quad 0x3f9d6b2725979802 + .quad 0x3f9c63d2ec14aaf2 + .quad 0x3f9b5cc258b718e6 + .quad 0x3f9a55f548c5c43f + .quad 0x3f994f6b99a24475 + .quad 0x3f98492528c8cabf + .quad 0x3f974321d3d006d3 + .quad 0x3f963d6178690bd6 + .quad 0x3f9537e3f45f3565 + .quad 0x3f9432a925980cc1 + .quad 0x3f932db0ea132e22 + .quad 0x3f9228fb1fea2e28 + .quad 0x3f912487a5507f70 + .quad 0x3f90205658935847 + .quad 0x3f8e38ce3033310c + .quad 0x3f8c317384c75f06 + .quad 0x3f8a2a9c6c170462 + .quad 0x3f882448a388a2aa + .quad 0x3f861e77e8b53fc6 + .quad 0x3f841929f96832f0 + .quad 0x3f82145e939ef1e9 + .quad 0x3f8010157588de71 + .quad 0x3f7c189cbb0e27fb + .quad 0x3f78121214586b54 + .quad 0x3f740c8a747878e2 + .quad 0x3f70080559588b35 + .quad 0x3f680904828985c0 + .quad 0x3f60040155d5889e + .quad 0x3f50020055655889 + .quad 0x0000000000000000 + .rept 56 + .byte 0 + .endr + +/* Polynomial coefficients for log part: + * coeff4 */ +double_vector _poly_coeff_1 0x3fc9999cacdb4d0a + +/* coeff3 */ +double_vector _poly_coeff_2 0xbfd0000148058ee1 + +/* coeff2 */ +double_vector _poly_coeff_3 0x3fd55555555543c5 + +/* coeff1 */ +double_vector _poly_coeff_4 0xbfdffffffffff81f + +/* General purpose constants for log part: ExpMask */ +double_vector _ExpMask 0x000fffffffffffff + +/* Two10 */ +double_vector _Two10 0x3f50000000000000 + +/* MinNorm */ +double_vector _MinNorm 0x0010000000000000 + +/* MaxNorm */ +double_vector _MaxNorm 0x7fefffffffffffff + +/* HalfMask */ +double_vector _HalfMask 0xfffffffffc000000 + +/* One */ +double_vector _One 0x3ff0000000000000 + +/* L2H */ +double_vector _L2H 0x3fe62e42fefa0000 + +/* L2L */ +double_vector _L2L 0x3d7cf79abc9e0000 + +/* Threshold */ +double_vector _Threshold 0x4086a00000000000 + +/* Bias */ +double_vector _Bias 0x408ff80000000000 + +/* Bias1 */ +double_vector _Bias1 0x408ff00000000000 + +/* L2L */ +double_vector _L2 0x3fe62e42fefa39ef + +/* dInfs = DP infinity, +/- == */ +.if .-__svml_spow_data != _dInfs +.err +.endif + .quad 0x7ff0000000000000 + .quad 0xfff0000000000000 + .rept 48 + .byte 0 + .endr + +/* dOnes = DP one, +/- == */ +.if .-__svml_spow_data != _dOnes +.err +.endif + .quad 0x3ff0000000000000 + .quad 0xbff0000000000000 + .rept 48 + .byte 0 + .endr + +/* dZeros = DP zero +/- == */ +.if .-__svml_spow_data != _dZeros +.err +.endif + .quad 0x0000000000000000 + .quad 0x8000000000000000 + .rept 48 + .byte 0 + .endr +.if .-__svml_spow_data != __dbT +.err +.endif + .quad 0x3feffffffc27dd9e + .quad 0x3ff00162f1a4047d + .quad 0x3ff002c603f68252 + .quad 0x3ff00429350e12af + .quad 0x3ff0058c84ed6032 + .quad 0x3ff006eff39715b2 + .quad 0x3ff00853810dde41 + .quad 0x3ff009b72d54652f + .quad 0x3ff00b1af86d5604 + .quad 0x3ff00c7ee25b5c86 + .quad 0x3ff00de2eb2124b3 + .quad 0x3ff00f4712c15ac8 + .quad 0x3ff010ab593eab39 + .quad 0x3ff0120fbe9bc2ba + .quad 0x3ff0137442db4e38 + .quad 0x3ff014d8e5fffada + .quad 0x3ff0163da80c7604 + .quad 0x3ff017a289036d56 + .quad 0x3ff0190788e78eab + .quad 0x3ff01a6ca7bb8818 + .quad 0x3ff01bd1e58207ef + .quad 0x3ff01d37423dbcbc + .quad 0x3ff01e9cbdf15549 + .quad 0x3ff02002589f8099 + .quad 0x3ff02168124aedec + .quad 0x3ff022cdeaf64cbc + .quad 0x3ff02433e2a44cc1 + .quad 0x3ff02599f9579ded + .quad 0x3ff027002f12f06d + .quad 0x3ff0286683d8f4ac + .quad 0x3ff029ccf7ac5b4d + .quad 0x3ff02b338a8fd532 + .quad 0x3ff02c9a3c861379 + .quad 0x3ff02e010d91c778 + .quad 0x3ff02f67fdb5a2c4 + .quad 0x3ff030cf0cf4572d + .quad 0x3ff032363b5096bc + .quad 0x3ff0339d88cd13bc + .quad 0x3ff03504f56c80ae + .quad 0x3ff0366c81319053 + .quad 0x3ff037d42c1ef5a2 + .quad 0x3ff0393bf63763d5 + .quad 0x3ff03aa3df7d8e5f + .quad 0x3ff03c0be7f428eb + .quad 0x3ff03d740f9de766 + .quad 0x3ff03edc567d7df7 + .quad 0x3ff04044bc95a0fe + .quad 0x3ff041ad41e9051d + .quad 0x3ff04315e67a5f2a + .quad 0x3ff0447eaa4c643e + .quad 0x3ff045e78d61c9ac + .quad 0x3ff047508fbd4502 + .quad 0x3ff048b9b1618c0b + .quad 0x3ff04a22f25154cd + .quad 0x3ff04b8c528f558b + .quad 0x3ff04cf5d21e44c4 + .quad 0x3ff04e5f7100d935 + .quad 0x3ff04fc92f39c9d4 + .quad 0x3ff051330ccbcdd5 + .quad 0x3ff0529d09b99ca8 + .quad 0x3ff054072605edfb + .quad 0x3ff0557161b379b3 + .quad 0x3ff056dbbcc4f7f8 + .quad 0x3ff05846373d212a + .quad 0x3ff059b0d11eade5 + .quad 0x3ff05b1b8a6c5706 + .quad 0x3ff05c866328d5a2 + .quad 0x3ff05df15b56e30a + .quad 0x3ff05f5c72f938cf + .quad 0x3ff060c7aa1290bd + .quad 0x3ff0623300a5a4db + .quad 0x3ff0639e76b52f6e + .quad 0x3ff0650a0c43eaf6 + .quad 0x3ff06675c1549232 + .quad 0x3ff067e195e9e01a + .quad 0x3ff0694d8a068fe7 + .quad 0x3ff06ab99dad5d0c + .quad 0x3ff06c25d0e10338 + .quad 0x3ff06d9223a43e58 + .quad 0x3ff06efe95f9ca95 + .quad 0x3ff0706b27e46455 + .quad 0x3ff071d7d966c83a + .quad 0x3ff07344aa83b324 + .quad 0x3ff074b19b3de22f + .quad 0x3ff0761eab9812b4 + .quad 0x3ff0778bdb950247 + .quad 0x3ff078f92b376ebc + .quad 0x3ff07a669a821621 + .quad 0x3ff07bd42977b6c4 + .quad 0x3ff07d41d81b0f2b + .quad 0x3ff07eafa66ede1e + .quad 0x3ff0801d9475e2a0 + .quad 0x3ff0818ba232dbee + .quad 0x3ff082f9cfa88985 + .quad 0x3ff084681cd9ab21 + .quad 0x3ff085d689c900b6 + .quad 0x3ff0874516794a79 + .quad 0x3ff088b3c2ed48d9 + .quad 0x3ff08a228f27bc86 + .quad 0x3ff08b917b2b6667 + .quad 0x3ff08d0086fb07a6 + .quad 0x3ff08e6fb29961a8 + .quad 0x3ff08fdefe09360d + .quad 0x3ff0914e694d46b6 + .quad 0x3ff092bdf46855c0 + .quad 0x3ff0942d9f5d2582 + .quad 0x3ff0959d6a2e7893 + .quad 0x3ff0970d54df11c8 + .quad 0x3ff0987d5f71b432 + .quad 0x3ff099ed89e9231e + .quad 0x3ff09b5dd448221a + .quad 0x3ff09cce3e9174ec + .quad 0x3ff09e3ec8c7df9d + .quad 0x3ff09faf72ee2670 + .quad 0x3ff0a1203d070de5 + .quad 0x3ff0a29127155abd + .quad 0x3ff0a402311bd1f0 + .quad 0x3ff0a5735b1d38bb + .quad 0x3ff0a6e4a51c5493 + .quad 0x3ff0a8560f1beb2c + .quad 0x3ff0a9c7991ec278 + .quad 0x3ff0ab394327a0a7 + .quad 0x3ff0acab0d394c25 + .quad 0x3ff0ae1cf7568b9d + .quad 0x3ff0af8f018225f7 + .quad 0x3ff0b1012bbee259 + .quad 0x3ff0b273760f8825 + .quad 0x3ff0b3e5e076defc + .quad 0x3ff0b5586af7aebc + .quad 0x3ff0b6cb1594bf84 + .quad 0x3ff0b83de050d9ab + .quad 0x3ff0b9b0cb2ec5ca + .quad 0x3ff0bb23d6314cb7 + .quad 0x3ff0bc97015b3783 + .quad 0x3ff0be0a4caf4f81 + .quad 0x3ff0bf7db8305e3f + .quad 0x3ff0c0f143e12d8a + .quad 0x3ff0c264efc4876c + .quad 0x3ff0c3d8bbdd362e + .quad 0x3ff0c54ca82e0455 + .quad 0x3ff0c6c0b4b9bca6 + .quad 0x3ff0c834e1832a24 + .quad 0x3ff0c9a92e8d180e + .quad 0x3ff0cb1d9bda51e1 + .quad 0x3ff0cc92296da35b + .quad 0x3ff0ce06d749d876 + .quad 0x3ff0cf7ba571bd6a + .quad 0x3ff0d0f093e81eab + .quad 0x3ff0d265a2afc8f1 + .quad 0x3ff0d3dad1cb892b + .quad 0x3ff0d550213e2c8c + .quad 0x3ff0d6c5910a8081 + .quad 0x3ff0d83b213352b8 + .quad 0x3ff0d9b0d1bb711b + .quad 0x3ff0db26a2a5a9d4 + .quad 0x3ff0dc9c93f4cb4a + .quad 0x3ff0de12a5aba423 + .quad 0x3ff0df88d7cd0344 + .quad 0x3ff0e0ff2a5bb7cd + .quad 0x3ff0e2759d5a9121 + .quad 0x3ff0e3ec30cc5edd + .quad 0x3ff0e562e4b3f0df + .quad 0x3ff0e6d9b9141745 + .quad 0x3ff0e850adefa265 + .quad 0x3ff0e9c7c34962db + .quad 0x3ff0eb3ef924297d + .quad 0x3ff0ecb64f82c75e + .quad 0x3ff0ee2dc6680dd6 + .quad 0x3ff0efa55dd6ce75 + .quad 0x3ff0f11d15d1db0c + .quad 0x3ff0f294ee5c05ab + .quad 0x3ff0f40ce77820a2 + .quad 0x3ff0f5850128fe7a + .quad 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0x3ffef20fb01ebafb + .quad 0x3ffef4be32cd20da + .quad 0x3ffef76cf0f9649a + .quad 0x3ffefa1beaa8ae04 + .quad 0x3ffefccb1fe02556 + .quad 0x3ffeff7a90a4f33f + .quad 0x3fff022a3cfc40e1 + .quad 0x3fff04da24eb37d0 + .quad 0x3fff078a48770213 + .quad 0x3fff0a3aa7a4ca23 + .quad 0x3fff0ceb4279baea + .quad 0x3fff0f9c18faffca + .quad 0x3fff124d2b2dc491 + .quad 0x3fff14fe79173584 + .quad 0x3fff17b002bc7f5a + .quad 0x3fff1a61c822cf3c + .quad 0x3fff1d13c94f52c7 + .quad 0x3fff1fc606473809 + .quad 0x3fff22787f0fad85 + .quad 0x3fff252b33ade22f + .quad 0x3fff27de24270571 + .quad 0x3fff2a9150804723 + .quad 0x3fff2d44b8bed796 + .quad 0x3fff2ff85ce7e78a + .quad 0x3fff32ac3d00a832 + .quad 0x3fff3560590e4b38 + .quad 0x3fff3814b11602b5 + .quad 0x3fff3ac9451d0138 + .quad 0x3fff3d7e152879c2 + .quad 0x3fff4033213d9fc8 + .quad 0x3fff42e86961a731 + .quad 0x3fff459ded99c45a + .quad 0x3fff4853adeb2c11 + .quad 0x3fff4b09aa5b1398 + .quad 0x3fff4dbfe2eeb0a6 + .quad 0x3fff507657ab3963 + .quad 0x3fff532d0895e46e + .quad 0x3fff55e3f5b3e8d8 + .quad 0x3fff589b1f0a7e23 + .quad 0x3fff5b52849edc4a + .quad 0x3fff5e0a26763bb8 + .quad 0x3fff60c20495d54d + .quad 0x3fff637a1f02e25c + .quad 0x3fff663275c29cab + .quad 0x3fff68eb08da3e7a + .quad 0x3fff6ba3d84f0275 + .quad 0x3fff6e5ce42623c1 + .quad 0x3fff71162c64ddf3 + .quad 0x3fff73cfb1106d1b + .quad 0x3fff7689722e0db5 + .quad 0x3fff79436fc2fcb6 + .quad 0x3fff7bfda9d47787 + .quad 0x3fff7eb82067bc04 + .quad 0x3fff8172d382087c + .quad 0x3fff842dc3289bb5 + .quad 0x3fff86e8ef60b4ea + .quad 0x3fff89a4582f93c7 + .quad 0x3fff8c5ffd9a786e + .quad 0x3fff8f1bdfa6a377 + .quad 0x3fff91d7fe5955eb + .quad 0x3fff949459b7d14b + .quad 0x3fff9750f1c7578c + .quad 0x3fff9a0dc68d2b16 + .quad 0x3fff9ccad80e8ec8 + .quad 0x3fff9f882650c5f2 + .quad 0x3fffa245b159145c + .quad 0x3fffa503792cbe42 + .quad 0x3fffa7c17dd10856 + .quad 0x3fffaa7fbf4b37bd + .quad 0x3fffad3e3da09211 + .quad 0x3fffaffcf8d65d61 + .quad 0x3fffb2bbf0f1e031 + .quad 0x3fffb57b25f8617d + .quad 0x3fffb83a97ef28b2 + .quad 0x3fffbafa46db7db4 + .quad 0x3fffbdba32c2a8db + .quad 0x3fffc07a5ba9f2f6 + .quad 0x3fffc33ac196a548 + .quad 0x3fffc5fb648e098a + .quad 0x3fffc8bc449569e9 + .quad 0x3fffcb7d61b21108 + .quad 0x3fffce3ebbe94a01 + .quad 0x3fffd10053406061 + .quad 0x3fffd3c227bca02c + .quad 0x3fffd684396355da + .quad 0x3fffd9468839ce5a + .quad 0x3fffdc0914455712 + .quad 0x3fffdecbdd8b3dd8 + .quad 0x3fffe18ee410d0ff + .quad 0x3fffe45227db5f4b + .quad 0x3fffe715a8f037f6 + .quad 0x3fffe9d96754aab1 + .quad 0x3fffec9d630e07a4 + .quad 0x3fffef619c219f69 + .quad 0x3ffff2261294c314 + .quad 0x3ffff4eac66cc42c + .quad 0x3ffff7afb7aef4b0 + .quad 0x3ffffa74e660a715 + .quad 0x3ffffd3a52872e44 + .quad 0x3ffffffffc27dd9e + .rept 56 + .byte 0 + .endr + +/* Other general purpose constants: + * _dbInvLn2 */ +double_vector __dbInvLn2 0x40a71547652b82fe + +/* _dbShifter */ +double_vector __dbShifter 0x4338000000000000 + +/* _dbHALF */ +double_vector __dbHALF 0x3fe0000000000000 + +/* _dbC1 = 2^(1/2^K)-1 */ +double_vector __dbC1 0x3f362f3904051fa1 + +/* _lbLOWKBITS = 2^K-1 */ +double_vector __lbLOWKBITS 0x00000000000007ff + +/* _iAbsMask */ +float_vector __iAbsMask 0x7fffffff + +/* _iDomainRange */ +float_vector __iDomainRange 0x4059fe36 + .type __svml_spow_data,@object + .size __svml_spow_data,.-__svml_spow_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.h new file mode 100644 index 0000000000..016dbf7fce --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_powf_data.h @@ -0,0 +1,76 @@ +/* Offsets for data table for function powf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef S_POWF_DATA_H +#define S_POWF_DATA_H + +#define _Log2Rcp_lookup -4218496 +#define _NMINNORM 0 +#define _NMAXVAL 64 +#define _INF 128 +#define _ABSMASK 192 +#define _DOMAINRANGE 256 +#define _Log_HA_table 320 +#define _Log_LA_table 8576 +#define _poly_coeff_1 12736 +#define _poly_coeff_2 12800 +#define _poly_coeff_3 12864 +#define _poly_coeff_4 12928 +#define _ExpMask 12992 +#define _Two10 13056 +#define _MinNorm 13120 +#define _MaxNorm 13184 +#define _HalfMask 13248 +#define _One 13312 +#define _L2H 13376 +#define _L2L 13440 +#define _Threshold 13504 +#define _Bias 13568 +#define _Bias1 13632 +#define _L2 13696 +#define _dInfs 13760 +#define _dOnes 13824 +#define _dZeros 13888 +#define __dbT 13952 +#define __dbInvLn2 30400 +#define __dbShifter 30464 +#define __dbHALF 30528 +#define __dbC1 30592 +#define __lbLOWKBITS 30656 +#define __iAbsMask 30720 +#define __iDomainRange 30784 + +.macro double_vector offset value +.if .-__svml_spow_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +.macro float_vector offset value +.if .-__svml_spow_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S new file mode 100644 index 0000000000..d86c91380e --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S @@ -0,0 +1,358 @@ +/* Function sincosf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16vl4l4_sincosf) +WRAPPER_IMPL_AVX512_fFF _ZGVdN8vl4l4_sincosf +END (_ZGVeN16vl4l4_sincosf) + +/* AVX512 ISA version as wrapper to AVX2 ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX512_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $448, %rsp + /* Encoding for vmovups %zmm0, 384(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x44 + .byte 0x24 + .byte 0x06 + lea (%rsp), %rdi + /* Encoding for vmovups %zmm1, 128(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4f + .byte 0x02 + /* Encoding for vmovups %zmm2, 192(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x57 + .byte 0x03 + /* Encoding for vmovups %zmm3, 256(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x5f + .byte 0x04 + /* Encoding for vmovups %zmm4, 320(%rdi). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x67 + .byte 0x05 + lea 64(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovdqu 416(%rsp), %ymm0 + lea 32(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 128(%rsp), %rdx + movq 136(%rsp), %rsi + movq 144(%rsp), %r8 + movq 152(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 160(%rsp), %rax + movq 168(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 176(%rsp), %rdi + movq 184(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 192(%rsp), %r11 + movq 200(%rsp), %rdx + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 208(%rsp), %rsi + movq 216(%rsp), %r8 + movl 32(%rsp), %r10d + movl 36(%rsp), %eax + movl 40(%rsp), %ecx + movl 44(%rsp), %edi + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 224(%rsp), %r10 + movq 232(%rsp), %rax + movl %ecx, (%rsi) + movl %edi, (%r8) + movq 240(%rsp), %rcx + movq 248(%rsp), %rdi + movl 48(%rsp), %r9d + movl 52(%rsp), %r11d + movl 56(%rsp), %edx + movl 60(%rsp), %esi + movl %r9d, (%r10) + movl %r11d, (%rax) + movq 256(%rsp), %r9 + movq 264(%rsp), %r11 + movl %edx, (%rcx) + movl %esi, (%rdi) + movq 272(%rsp), %rdx + movq 280(%rsp), %rsi + movl 64(%rsp), %r8d + movl 68(%rsp), %r10d + movl 72(%rsp), %eax + movl 76(%rsp), %ecx + movl %r8d, (%r9) + movl %r10d, (%r11) + movq 288(%rsp), %r8 + movq 296(%rsp), %r10 + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 304(%rsp), %rax + movq 312(%rsp), %rcx + movl 80(%rsp), %edi + movl 84(%rsp), %r9d + movl 88(%rsp), %r11d + movl 92(%rsp), %edx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 320(%rsp), %rdi + movq 328(%rsp), %r9 + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 336(%rsp), %r11 + movq 344(%rsp), %rdx + movl 96(%rsp), %esi + movl 100(%rsp), %r8d + movl 104(%rsp), %r10d + movl 108(%rsp), %eax + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 352(%rsp), %rsi + movq 360(%rsp), %r8 + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 368(%rsp), %r10 + movq 376(%rsp), %rax + movl 112(%rsp), %ecx + movl 116(%rsp), %edi + movl 120(%rsp), %r9d + movl 124(%rsp), %r11d + movl %ecx, (%rsi) + movl %edi, (%r8) + movl %r9d, (%r10) + movl %r11d, (%rax) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-64, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -112(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -176(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $344, %esp + /* Encoding for vmovdqa64 %zmm1, -240(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0xfd + .byte 0x48 + .byte 0x7f + .byte 0x8d + .byte 0x10 + .byte 0xff + .byte 0xff + .byte 0xff + /* Encoding for vmovdqa64 %zmm2, -304(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0xfd + .byte 0x48 + .byte 0x7f + .byte 0x95 + .byte 0xd0 + .byte 0xfe + .byte 0xff + .byte 0xff + /* Encoding for vmovaps %zmm0, -368(%ebp). */ + .byte 0x67 + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x29 + .byte 0x85 + .byte 0x90 + .byte 0xfe + .byte 0xff + .byte 0xff + call HIDDEN_JUMPTARGET(\callee) + leal 32(%r12), %esi + vmovups -336(%ebp), %ymm0 + leal 32(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movl -240(%ebp), %eax + vmovss -176(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -236(%ebp), %eax + vmovss -172(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -232(%ebp), %eax + vmovss -168(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -228(%ebp), %eax + vmovss -164(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -224(%ebp), %eax + vmovss -160(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -220(%ebp), %eax + vmovss -156(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -216(%ebp), %eax + vmovss -152(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -212(%ebp), %eax + vmovss -148(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -208(%ebp), %eax + vmovss -144(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -204(%ebp), %eax + vmovss -140(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -200(%ebp), %eax + vmovss -136(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -196(%ebp), %eax + vmovss -132(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -192(%ebp), %eax + vmovss -128(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -188(%ebp), %eax + vmovss -124(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -184(%ebp), %eax + vmovss -120(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -180(%ebp), %eax + vmovss -116(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -304(%ebp), %eax + vmovss -112(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -300(%ebp), %eax + vmovss -108(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -296(%ebp), %eax + vmovss -104(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -292(%ebp), %eax + vmovss -100(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -288(%ebp), %eax + vmovss -96(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -284(%ebp), %eax + vmovss -92(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -280(%ebp), %eax + vmovss -88(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -276(%ebp), %eax + vmovss -84(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -272(%ebp), %eax + vmovss -80(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -268(%ebp), %eax + vmovss -76(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -264(%ebp), %eax + vmovss -72(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -260(%ebp), %eax + vmovss -68(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -256(%ebp), %eax + vmovss -64(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -252(%ebp), %eax + vmovss -60(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -248(%ebp), %eax + vmovss -56(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -244(%ebp), %eax + vmovss -52(%ebp), %xmm0 + vmovss %xmm0, (%eax) + addl $344, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVeN16vvv_sincosf) +WRAPPER_IMPL_AVX512_fFF_vvv _ZGVdN8vl4l4_sincosf +END (_ZGVeN16vvv_sincosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S new file mode 100644 index 0000000000..2ab33b59a7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S @@ -0,0 +1,152 @@ +/* Function sincosf vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4vl4l4_sincosf) +WRAPPER_IMPL_SSE2_fFF sincosf +END (_ZGVbN4vl4l4_sincosf) +libmvec_hidden_def (_ZGVbN4vl4l4_sincosf) + +/* SSE2 ISA version as wrapper to scalar (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_SSE2_fFF_vvv callee +#ifndef __ILP32__ + subq $120, %rsp + cfi_adjust_cfa_offset(120) + movaps %xmm0, 96(%rsp) + lea (%rsp), %rdi + movdqa %xmm1, 32(%rdi) + lea 16(%rsp), %rsi + movdqa %xmm2, 32(%rsi) + movdqa %xmm3, 48(%rsi) + movdqa %xmm4, 64(%rsi) + call JUMPTARGET(\callee) + movss 100(%rsp), %xmm0 + lea 4(%rsp), %rdi + lea 20(%rsp), %rsi + call JUMPTARGET(\callee) + movss 104(%rsp), %xmm0 + lea 8(%rsp), %rdi + lea 24(%rsp), %rsi + call JUMPTARGET(\callee) + movss 108(%rsp), %xmm0 + lea 12(%rsp), %rdi + lea 28(%rsp), %rsi + call JUMPTARGET(\callee) + movq 32(%rsp), %rdx + movq 40(%rsp), %rsi + movq 48(%rsp), %r8 + movq 56(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 64(%rsp), %rax + movq 72(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 80(%rsp), %rdi + movq 88(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movl %esi, (%rdi) + movl %r8d, (%r9) + addq $120, %rsp + cfi_adjust_cfa_offset(-120) + ret +#else + pushq %rbp + .cfi_def_cfa_offset 16 + .cfi_offset 6, -16 + pushq %rbx + .cfi_def_cfa_offset 24 + .cfi_offset 3, -24 + subl $88, %esp + .cfi_def_cfa_offset 112 + leal 64(%rsp), %esi + movaps %xmm1, (%esp) + leal 48(%rsp), %edi + movaps %xmm2, 16(%esp) + movq %rsi, %rbp + movq %rdi, %rbx + movaps %xmm0, 32(%esp) + call JUMPTARGET(\callee) + movups 36(%esp), %xmm0 + leal 4(%rbp), %esi + leal 4(%rbx), %edi + call JUMPTARGET(\callee) + movups 40(%esp), %xmm0 + leal 8(%rbp), %esi + leal 8(%rbx), %edi + call JUMPTARGET(\callee) + movups 44(%esp), %xmm0 + leal 12(%rbp), %esi + leal 12(%rbx), %edi + call JUMPTARGET(\callee) + movq (%esp), %rax + movss 48(%esp), %xmm0 + movdqa (%esp), %xmm4 + movdqa 16(%esp), %xmm7 + movss %xmm0, (%eax) + movss 52(%esp), %xmm0 + pextrd $1, %xmm4, %eax + movss %xmm0, (%eax) + movq 8(%esp), %rax + movss 56(%esp), %xmm0 + movss %xmm0, (%eax) + movss 60(%esp), %xmm0 + pextrd $3, %xmm4, %eax + movss %xmm0, (%eax) + movq 16(%esp), %rax + movss 64(%esp), %xmm0 + movss %xmm0, (%eax) + movss 68(%esp), %xmm0 + pextrd $1, %xmm7, %eax + movss %xmm0, (%eax) + movq 24(%esp), %rax + movss 72(%esp), %xmm0 + movss %xmm0, (%eax) + movss 76(%esp), %xmm0 + pextrd $3, %xmm7, %eax + movss %xmm0, (%eax) + addl $88, %esp + .cfi_def_cfa_offset 24 + popq %rbx + .cfi_def_cfa_offset 16 + popq %rbp + .cfi_def_cfa_offset 8 + ret +#endif +.endm + +ENTRY (_ZGVbN4vvv_sincosf) +WRAPPER_IMPL_SSE2_fFF_vvv sincosf +END (_ZGVbN4vvv_sincosf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S new file mode 100644 index 0000000000..757d39c522 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S @@ -0,0 +1,200 @@ +/* Function sincosf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8vl4l4_sincosf) +WRAPPER_IMPL_AVX_fFF _ZGVbN4vl4l4_sincosf +END (_ZGVdN8vl4l4_sincosf) +libmvec_hidden_def (_ZGVdN8vl4l4_sincosf) + +/* AVX2 ISA version as wrapper to SSE ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX2_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $224, %rsp + vmovups %ymm0, 192(%rsp) + lea (%rsp), %rdi + vmovdqu %ymm1, 64(%rdi) + vmovdqu %ymm2, 96(%rdi) + vmovdqu %ymm3, 128(%rdi) + vmovdqu %ymm4, 160(%rdi) + lea 32(%rsp), %rsi + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovups 208(%rsp), %xmm0 + lea 16(%rsp), %rdi + lea 48(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 64(%rsp), %rdx + movq 72(%rsp), %rsi + movq 80(%rsp), %r8 + movq 88(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 96(%rsp), %rax + movq 104(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 112(%rsp), %rdi + movq 120(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 128(%rsp), %r11 + movq 136(%rsp), %rdx + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 144(%rsp), %rsi + movq 152(%rsp), %r8 + movl 32(%rsp), %r10d + movl 36(%rsp), %eax + movl 40(%rsp), %ecx + movl 44(%rsp), %edi + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 160(%rsp), %r10 + movq 168(%rsp), %rax + movl %ecx, (%rsi) + movl %edi, (%r8) + movq 176(%rsp), %rcx + movq 184(%rsp), %rdi + movl 48(%rsp), %r9d + movl 52(%rsp), %r11d + movl 56(%rsp), %edx + movl 60(%rsp), %esi + movl %r9d, (%r10) + movl %r11d, (%rax) + movl %edx, (%rcx) + movl %esi, (%rdi) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -80(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -112(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $184, %esp + vmovdqa %ymm1, -144(%ebp) + vmovdqa %ymm2, -176(%ebp) + vmovaps %ymm0, -208(%ebp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + leal 16(%r12), %esi + vmovups -192(%ebp), %xmm0 + leal 16(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movl -144(%ebp), %eax + vmovss -112(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -140(%ebp), %eax + vmovss -108(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -136(%ebp), %eax + vmovss -104(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -132(%ebp), %eax + vmovss -100(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -128(%ebp), %eax + vmovss -96(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -124(%ebp), %eax + vmovss -92(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -120(%ebp), %eax + vmovss -88(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -116(%ebp), %eax + vmovss -84(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -176(%ebp), %eax + vmovss -80(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -172(%ebp), %eax + vmovss -76(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -168(%ebp), %eax + vmovss -72(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -164(%ebp), %eax + vmovss -68(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -160(%ebp), %eax + vmovss -64(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -156(%ebp), %eax + vmovss -60(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -152(%ebp), %eax + vmovss -56(%ebp), %xmm0 + vmovss %xmm0, (%eax) + movl -148(%ebp), %eax + vmovss -52(%ebp), %xmm0 + vmovss %xmm0, (%eax) + addl $184, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVdN8vvv_sincosf) +WRAPPER_IMPL_AVX2_fFF_vvv _ZGVbN4vl4l4_sincosf +END (_ZGVdN8vvv_sincosf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S new file mode 100644 index 0000000000..0955924cdd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S @@ -0,0 +1,198 @@ +/* Function sincosf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVcN8vl4l4_sincosf) +WRAPPER_IMPL_AVX_fFF _ZGVbN4vl4l4_sincosf +END (_ZGVcN8vl4l4_sincosf) + +/* AVX ISA version as wrapper to SSE ISA version (for vector + function declared with #pragma omp declare simd notinbranch). */ +.macro WRAPPER_IMPL_AVX_fFF_vvv callee +#ifndef __ILP32__ + pushq %rbp + movq %rsp, %rbp + andq $-32, %rsp + subq $224, %rsp + vmovups %ymm0, 64(%rsp) + lea (%rsp), %rdi + vmovdqu %xmm1, 96(%rdi) + vmovdqu %xmm2, 112(%rdi) + vmovdqu %xmm3, 128(%rdi) + vmovdqu %xmm4, 144(%rdi) + vmovdqu %xmm5, 160(%rdi) + lea 32(%rsp), %rsi + vmovdqu %xmm6, 144(%rsi) + vmovdqu %xmm7, 160(%rsi) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovdqu 80(%rsp), %xmm0 + lea 16(%rsp), %rdi + lea 48(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + movq 96(%rsp), %rdx + movq 104(%rsp), %rsi + movq 112(%rsp), %r8 + movq 120(%rsp), %r10 + movl (%rsp), %eax + movl 4(%rsp), %ecx + movl 8(%rsp), %edi + movl 12(%rsp), %r9d + movl %eax, (%rdx) + movl %ecx, (%rsi) + movq 128(%rsp), %rax + movq 136(%rsp), %rcx + movl %edi, (%r8) + movl %r9d, (%r10) + movq 144(%rsp), %rdi + movq 152(%rsp), %r9 + movl 16(%rsp), %r11d + movl 20(%rsp), %edx + movl 24(%rsp), %esi + movl 28(%rsp), %r8d + movl %r11d, (%rax) + movl %edx, (%rcx) + movq 160(%rsp), %r11 + movq 168(%rsp), %rdx + movl %esi, (%rdi) + movl %r8d, (%r9) + movq 176(%rsp), %rsi + movq 184(%rsp), %r8 + movl 32(%rsp), %r10d + movl 36(%rsp), %eax + movl 40(%rsp), %ecx + movl 44(%rsp), %edi + movl %r10d, (%r11) + movl %eax, (%rdx) + movq 192(%rsp), %r10 + movq 200(%rsp), %rax + movl %ecx, (%rsi) + movl %edi, (%r8) + movq 16(%rbp), %rcx + movq 24(%rbp), %rdi + movl 48(%rsp), %r9d + movl 52(%rsp), %r11d + movl 56(%rsp), %edx + movl 60(%rsp), %esi + movl %r9d, (%r10) + movl %r11d, (%rax) + movl %edx, (%rcx) + movl %esi, (%rdi) + movq %rbp, %rsp + popq %rbp + ret +#else + leal 8(%rsp), %r10d + .cfi_def_cfa 10, 0 + andl $-32, %esp + pushq -8(%r10d) + pushq %rbp + .cfi_escape 0x10,0x6,0x2,0x76,0 + movl %esp, %ebp + pushq %r12 + leal -80(%rbp), %esi + pushq %r10 + .cfi_escape 0xf,0x3,0x76,0x70,0x6 + .cfi_escape 0x10,0xc,0x2,0x76,0x78 + leal -112(%rbp), %edi + movq %rsi, %r12 + pushq %rbx + .cfi_escape 0x10,0x3,0x2,0x76,0x68 + movq %rdi, %rbx + subl $184, %esp + vmovaps %xmm1, -128(%ebp) + vmovaps %xmm2, -144(%ebp) + vmovaps %xmm3, -160(%ebp) + vmovaps %xmm4, -176(%ebp) + vmovaps %ymm0, -208(%ebp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + leal 16(%r12), %esi + vmovups -192(%ebp), %xmm0 + leal 16(%rbx), %edi + call HIDDEN_JUMPTARGET(\callee) + movq -128(%ebp), %rax + vmovss -112(%ebp), %xmm0 + vmovdqa -128(%ebp), %xmm7 + vmovdqa -144(%ebp), %xmm3 + vmovss %xmm0, (%eax) + vmovss -108(%ebp), %xmm0 + vpextrd $1, %xmm7, %eax + vmovss %xmm0, (%eax) + movq -120(%ebp), %rax + vmovss -104(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -100(%ebp), %xmm0 + vpextrd $3, %xmm7, %eax + vmovdqa -160(%ebp), %xmm7 + vmovss %xmm0, (%eax) + movq -144(%ebp), %rax + vmovss -96(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -92(%ebp), %xmm0 + vpextrd $1, %xmm3, %eax + vmovss %xmm0, (%eax) + movq -136(%ebp), %rax + vmovss -88(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -84(%ebp), %xmm0 + vpextrd $3, %xmm3, %eax + vmovss %xmm0, (%eax) + movq -160(%ebp), %rax + vmovss -80(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -76(%ebp), %xmm0 + vpextrd $1, %xmm7, %eax + vmovss %xmm0, (%eax) + movq -152(%ebp), %rax + vmovss -72(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -68(%ebp), %xmm0 + vpextrd $3, %xmm7, %eax + vmovss %xmm0, (%eax) + movq -176(%ebp), %rax + vmovss -64(%ebp), %xmm0 + vmovdqa -176(%ebp), %xmm3 + vmovss %xmm0, (%eax) + vmovss -60(%ebp), %xmm0 + vpextrd $1, %xmm3, %eax + vmovss %xmm0, (%eax) + movq -168(%ebp), %rax + vmovss -56(%ebp), %xmm0 + vmovss %xmm0, (%eax) + vmovss -52(%ebp), %xmm0 + vpextrd $3, %xmm3, %eax + vmovss %xmm0, (%eax) + addl $184, %esp + popq %rbx + popq %r10 + .cfi_def_cfa 10, 0 + popq %r12 + popq %rbp + leal -8(%r10), %esp + .cfi_def_cfa 7, 8 + ret +#endif +.endm + +ENTRY (_ZGVcN8vvv_sincosf) +WRAPPER_IMPL_AVX_fFF_vvv _ZGVbN4vl4l4_sincosf +END (_ZGVcN8vvv_sincosf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf16_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf16_core.S new file mode 100644 index 0000000000..14473da427 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf16_core.S @@ -0,0 +1,25 @@ +/* Function sinf vectorized with AVX-512. Wrapper to AVX2 version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVeN16v_sinf) +WRAPPER_IMPL_AVX512 _ZGVdN8v_sinf +END (_ZGVeN16v_sinf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf4_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf4_core.S new file mode 100644 index 0000000000..910f39c7f2 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf4_core.S @@ -0,0 +1,30 @@ +/* Function sinf vectorized with SSE2. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVbN4v_sinf) +WRAPPER_IMPL_SSE2 sinf +END (_ZGVbN4v_sinf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVbN4v_sinf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core.S new file mode 100644 index 0000000000..568c978a22 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core.S @@ -0,0 +1,29 @@ +/* Function sinf vectorized with AVX2, wrapper version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY (_ZGVdN8v_sinf) +WRAPPER_IMPL_AVX _ZGVbN4v_sinf +END (_ZGVdN8v_sinf) + +#ifndef USE_MULTIARCH + libmvec_hidden_def (_ZGVdN8v_sinf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S new file mode 100644 index 0000000000..603f59ed1b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S @@ -0,0 +1,25 @@ +/* Function sinf vectorized in AVX ISA as wrapper to SSE4 ISA version. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include "svml_s_wrapper_impl.h" + + .text +ENTRY(_ZGVcN8v_sinf) +WRAPPER_IMPL_AVX _ZGVbN4v_sinf +END(_ZGVcN8v_sinf) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.S b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.S new file mode 100644 index 0000000000..19a569118f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.S @@ -0,0 +1,111 @@ +/* Data for function cosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "svml_s_trig_data.h" + + .section .rodata, "a" + .align 64 + +/* Data table for vector implementations of function cosf. + The table may contain polynomial, reduction, lookup coefficients + and other macro_names obtained through different methods + of research and experimental work. */ + + .globl __svml_s_trig_data +__svml_s_trig_data: + +/* General purpose constants: + absolute value mask */ +float_vector __sAbsMask 0x7fffffff + +/* threshold for out-of-range values */ +float_vector __sRangeReductionVal 0x461c4000 + +/* +INF */ +float_vector __sRangeVal 0x7f800000 + +/* High Accuracy version polynomial coefficients: + S1 = -1.66666666664728165763e-01 */ +float_vector __sS1 0xbe2aaaab + +/* S2 = 8.33329173045453069014e-03 */ +float_vector __sS2 0x3c08885c + +/* C1 = -5.00000000000000000000e-01 */ +float_vector __sC1 0xbf000000 + +/* C2 = 4.16638942914469202550e-02 */ +float_vector __sC2 0x3d2aaa7c + +/* Range reduction PI-based constants: + PI high part */ +float_vector __sPI1 0x40490000 + +/* PI mid part 1 */ +float_vector __sPI2 0x3a7da000 + +/* PI mid part 2 */ +float_vector __sPI3 0x34222000 + +/* PI low part */ +float_vector __sPI4 0x2cb4611a + +/* PI1, PI2, and PI3 when FMA is available + PI high part (when FMA available) */ +float_vector __sPI1_FMA 0x40490fdb + +/* PI mid part (when FMA available) */ +float_vector __sPI2_FMA 0xb3bbbd2e + +/* PI low part (when FMA available) */ +float_vector __sPI3_FMA 0xa7772ced + +/* Polynomial constants for work w/o FMA, relative error ~ 2^(-26.625) */ +float_vector __sA3 0xbe2aaaa6 +float_vector __sA5 0x3c08876a +float_vector __sA7 0xb94fb7ff +float_vector __sA9 0x362edef8 + +/* Polynomial constants, work with FMA, relative error ~ 2^(-26.417) */ +float_vector __sA5_FMA 0x3c088768 +float_vector __sA7_FMA 0xb94fb6cf +float_vector __sA9_FMA 0x362ec335 + +/* 1/PI */ +float_vector __sInvPI 0x3ea2f983 + +/* right-shifter constant */ +float_vector __sRShifter 0x4b400000 + +/* PI/2 */ +float_vector __sHalfPI 0x3fc90fdb + +/* 1/2 */ +float_vector __sOneHalf 0x3f000000 + +/* high accuracy table index mask */ +float_vector __iIndexMask 0x000000ff + +/* 2^(k-1) */ +float_vector __i2pK_1 0x00000040 + +/* sign field mask */ +float_vector __sSignMask 0x80000000 + + .type __svml_s_trig_data,@object + .size __svml_s_trig_data,.-__svml_s_trig_data diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.h new file mode 100644 index 0000000000..04f4f7b1ed --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_trig_data.h @@ -0,0 +1,62 @@ +/* Offsets for data table for vectorized sinf, cosf, sincosf. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef S_TRIG_DATA_H +#define S_TRIG_DATA_H + +.macro float_vector offset value +.if .-__svml_s_trig_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#define __sAbsMask 0 +#define __sRangeReductionVal 64 +#define __sRangeVal 64*2 +#define __sS1 64*3 +#define __sS2 64*4 +#define __sC1 64*5 +#define __sC2 64*6 +#define __sPI1 64*7 +#define __sPI2 64*8 +#define __sPI3 64*9 +#define __sPI4 64*10 +#define __sPI1_FMA 64*11 +#define __sPI2_FMA 64*12 +#define __sPI3_FMA 64*13 +#define __sA3 64*14 +#define __sA5 64*15 +#define __sA7 64*16 +#define __sA9 64*17 +#define __sA5_FMA 64*18 +#define __sA7_FMA 64*19 +#define __sA9_FMA 64*20 +#define __sInvPI 64*21 +#define __sRShifter 64*22 +#define __sHalfPI 64*23 +#define __sOneHalf 64*24 +#define __iIndexMask 64*25 +#define __i2pK_1 64*26 +#define __sSignMask 64*27 +#define __dT_cosf 64*28 +#define __dT 64*92 + +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h new file mode 100644 index 0000000000..cd6d58361c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h @@ -0,0 +1,371 @@ +/* Wrapper implementations of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2 callee + subq $40, %rsp + cfi_adjust_cfa_offset(40) + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + movss %xmm0, 16(%rsp) + movss 4(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss %xmm0, 20(%rsp) + movss 8(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss %xmm0, 24(%rsp) + movss 12(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss 16(%rsp), %xmm3 + movss 20(%rsp), %xmm2 + movss 24(%rsp), %xmm1 + movss %xmm0, 28(%rsp) + unpcklps %xmm1, %xmm3 + unpcklps %xmm0, %xmm2 + unpcklps %xmm2, %xmm3 + movaps %xmm3, %xmm0 + addq $40, %rsp + cfi_adjust_cfa_offset(-40) + ret +.endm + +/* 2 argument SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2_ff callee + subq $56, %rsp + cfi_adjust_cfa_offset(56) + movaps %xmm0, (%rsp) + movaps %xmm1, 16(%rsp) + call JUMPTARGET(\callee) + movss %xmm0, 32(%rsp) + movss 4(%rsp), %xmm0 + movss 20(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss %xmm0, 36(%rsp) + movss 8(%rsp), %xmm0 + movss 24(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss %xmm0, 40(%rsp) + movss 12(%rsp), %xmm0 + movss 28(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss 32(%rsp), %xmm3 + movss 36(%rsp), %xmm2 + movss 40(%rsp), %xmm1 + movss %xmm0, 44(%rsp) + unpcklps %xmm1, %xmm3 + unpcklps %xmm0, %xmm2 + unpcklps %xmm2, %xmm3 + movaps %xmm3, %xmm0 + addq $56, %rsp + cfi_adjust_cfa_offset(-56) + ret +.endm + +/* 3 argument SSE2 ISA version as wrapper to scalar. */ +.macro WRAPPER_IMPL_SSE2_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + pushq %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + movq %rdi, %rbp + movq %rsi, %rbx + subq $40, %rsp + cfi_adjust_cfa_offset(40) + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movss 28(%rsp), %xmm0 + movss %xmm0, 0(%rbp) + movaps (%rsp), %xmm1 + movss 24(%rsp), %xmm0 + movss %xmm0, (%rbx) + movaps %xmm1, %xmm0 + shufps $85, %xmm1, %xmm0 + call JUMPTARGET(\callee) + movss 28(%rsp), %xmm0 + leaq 24(%rsp), %rsi + movss %xmm0, 4(%rbp) + leaq 28(%rsp), %rdi + movaps (%rsp), %xmm1 + movss 24(%rsp), %xmm0 + movss %xmm0, 4(%rbx) + movaps %xmm1, %xmm0 + unpckhps %xmm1, %xmm0 + call JUMPTARGET(\callee) + movaps (%rsp), %xmm1 + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movss 28(%rsp), %xmm0 + shufps $255, %xmm1, %xmm1 + movss %xmm0, 8(%rbp) + movss 24(%rsp), %xmm0 + movss %xmm0, 8(%rbx) + movaps %xmm1, %xmm0 + call JUMPTARGET(\callee) + movss 28(%rsp), %xmm0 + movss %xmm0, 12(%rbp) + movss 24(%rsp), %xmm0 + movss %xmm0, 12(%rbx) + addq $40, %rsp + cfi_adjust_cfa_offset(-40) + popq %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $32, %rsp + vextractf128 $1, %ymm0, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 16(%rsp) + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 16(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $64, %rsp + vextractf128 $1, %ymm0, 16(%rsp) + vextractf128 $1, %ymm1, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 32(%rsp) + vmovaps 16(%rsp), %xmm0 + vmovaps (%rsp), %xmm1 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 32(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + pushq %r14 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r14, 0) + subq $48, %rsp + movq %rsi, %r14 + vmovaps %ymm0, (%rsp) + movq %rdi, %r13 + vmovaps 16(%rsp), %xmm1 + vmovaps %xmm1, 32(%rsp) + vzeroupper + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %xmm0 + lea (%rsp), %rdi + lea 16(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovaps (%rsp), %xmm0 + vmovaps 16(%rsp), %xmm1 + vmovaps %xmm0, 16(%r13) + vmovaps %xmm1, 16(%r14) + addq $48, %rsp + popq %r14 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r14) + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512 callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $128, %rsp +/* Below is encoding for vmovups %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x04 + .byte 0x24 + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 64(%rsp) + vmovupd 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 96(%rsp) +/* Below is encoding for vmovups 64(%rsp), %zmm0. */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x10 + .byte 0x44 + .byte 0x24 + .byte 0x01 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $192, %rsp +/* Below is encoding for vmovups %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x04 + .byte 0x24 +/* Below is encoding for vmovups %zmm1, 64(%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x11 + .byte 0x4c + .byte 0x24 + .byte 0x01 + vmovups (%rsp), %ymm0 + vmovups 64(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovups %ymm0, 128(%rsp) + vmovups 32(%rsp), %ymm0 + vmovups 96(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovups %ymm0, 160(%rsp) +/* Below is encoding for vmovups 128(%rsp), %zmm0. */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x10 + .byte 0x44 + .byte 0x24 + .byte 0x02 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + pushq %r12 + pushq %r13 + subq $176, %rsp + movq %rsi, %r13 +/* Below is encoding for vmovaps %zmm0, (%rsp). */ + .byte 0x62 + .byte 0xf1 + .byte 0x7c + .byte 0x48 + .byte 0x29 + .byte 0x04 + .byte 0x24 + movq %rdi, %r12 + vmovaps (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %ymm0 + lea 64(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovaps 64(%rsp), %ymm0 + vmovaps 96(%rsp), %ymm1 + vmovaps %ymm0, 32(%r12) + vmovaps %ymm1, 32(%r13) + addq $176, %rsp + popq %r13 + popq %r12 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-main.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-mod.c new file mode 100644 index 0000000000..514883dcf9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx-mod.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-main.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-mod.c new file mode 100644 index 0000000000..514883dcf9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2-mod.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx2.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-main.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-mod.c new file mode 100644 index 0000000000..514883dcf9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512-mod.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-avx512.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-main.c new file mode 100644 index 0000000000..43914ef0e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-mod.c new file mode 100644 index 0000000000..d549c3ec19 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias-mod.c @@ -0,0 +1,25 @@ +/* Part of test to build shared library to ensure link against + *_finite aliases from libmvec. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> +#include <stdlib.h> +#include <math-tests-arch.h> + +#include "test-double.h" +#include "test-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias.c new file mode 100644 index 0000000000..c7048d346f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-alias.c @@ -0,0 +1,29 @@ +/* Part of test to ensure link against *_finite aliases from libmvec. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +extern int +test_finite_alias (void); + +static int +do_test (void) +{ + return test_finite_alias (); +} + +#define TEST_FUNCTION do_test () +#include "../../../test-skeleton.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx-main.c new file mode 100644 index 0000000000..fc2ffea314 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx.c new file mode 100644 index 0000000000..896f1bcbaf --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2-main.c new file mode 100644 index 0000000000..fc2ffea314 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2.c new file mode 100644 index 0000000000..896f1bcbaf --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512-main.c new file mode 100644 index 0000000000..fc2ffea314 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512-main.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512.c new file mode 100644 index 0000000000..896f1bcbaf --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512.c @@ -0,0 +1 @@ +#include "test-double-libmvec-sincos.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-main.c new file mode 100644 index 0000000000..c33436dc0f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos-main.c @@ -0,0 +1,43 @@ +/* Test for vector sincos ABI. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define N 1000 +double x[N], s[N], c[N]; +double* s_ptrs[N]; +double* c_ptrs[N]; + +int +test_sincos_abi (void) +{ + int i; + + for(i = 0; i < N; i++) + { + x[i] = i / 3; + s_ptrs[i] = &s[i]; + c_ptrs[i] = &c[i]; + } + +#pragma omp simd + for(i = 0; i < N; i++) + sincos (x[i], s_ptrs[i], c_ptrs[i]); + + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos.c new file mode 100644 index 0000000000..9be71edd93 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-libmvec-sincos.c @@ -0,0 +1,44 @@ +/* Test for vector sincos ABI. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math-tests-arch.h> + +extern int test_sincos_abi (void); + +int arch_check = 1; + +static void +check_arch (void) +{ + CHECK_ARCH_EXT; + arch_check = 0; +} + +static int +do_test (void) +{ + check_arch (); + + if (arch_check) + return 77; + + return test_sincos_abi (); +} + +#define TEST_FUNCTION do_test () +#include "../../../test-skeleton.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c new file mode 100644 index 0000000000..b4457f700a --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c @@ -0,0 +1,33 @@ +/* Wrapper part of tests for SSE ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-double-vlen2.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m128d + +VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVbN2v_cos) +VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVbN2v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVbN2v_log) +VECTOR_WRAPPER (WRAPPER_NAME (exp), _ZGVbN2v_exp) +VECTOR_WRAPPER_ff (WRAPPER_NAME (pow), _ZGVbN2vv_pow) + +#define VEC_INT_TYPE __m128i + +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincos), _ZGVbN2vvv_sincos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c new file mode 100644 index 0000000000..e6b991ceaf --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c @@ -0,0 +1,40 @@ +/* Wrapper part of tests for AVX2 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-double-vlen4.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#undef VEC_SUFF +#define VEC_SUFF _vlen4_avx2 + +#define VEC_TYPE __m256d + +VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVdN4v_cos) +VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVdN4v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVdN4v_log) +VECTOR_WRAPPER (WRAPPER_NAME (exp), _ZGVdN4v_exp) +VECTOR_WRAPPER_ff (WRAPPER_NAME (pow), _ZGVdN4vv_pow) + +#ifndef __ILP32__ +# define VEC_INT_TYPE __m256i +#else +# define VEC_INT_TYPE __m128i +#endif + +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincos), _ZGVdN4vvv_sincos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2.h b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2.h new file mode 100644 index 0000000000..a15d4be31f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-avx2.h @@ -0,0 +1,25 @@ +/* Tests for AVX2 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <test-double-vlen4.h> + +#undef VEC_SUFF +#define VEC_SUFF _vlen4_avx2 + +#undef REQUIRE_AVX +#define REQUIRE_AVX2 diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c new file mode 100644 index 0000000000..3606b6f55f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c @@ -0,0 +1,37 @@ +/* Wrapper part of tests for AVX ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-double-vlen4.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m256d + +VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVcN4v_cos) +VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVcN4v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVcN4v_log) +VECTOR_WRAPPER (WRAPPER_NAME (exp), _ZGVcN4v_exp) +VECTOR_WRAPPER_ff (WRAPPER_NAME (pow), _ZGVcN4vv_pow) + +#define VEC_INT_TYPE __m128i + +#ifndef __ILP32__ +VECTOR_WRAPPER_fFF_3 (WRAPPER_NAME (sincos), _ZGVcN4vvv_sincos) +#else +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincos), _ZGVcN4vvv_sincos) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4.h b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4.h new file mode 100644 index 0000000000..1698e621d6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen4.h @@ -0,0 +1,21 @@ +/* Tests for AVX ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include_next <test-double-vlen4.h> + +#define REQUIRE_AVX diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c new file mode 100644 index 0000000000..d77b43046d --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c @@ -0,0 +1,37 @@ +/* Wrapper part of tests for AVX-512 versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-double-vlen8.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m512d + +VECTOR_WRAPPER (WRAPPER_NAME (cos), _ZGVeN8v_cos) +VECTOR_WRAPPER (WRAPPER_NAME (sin), _ZGVeN8v_sin) +VECTOR_WRAPPER (WRAPPER_NAME (log), _ZGVeN8v_log) +VECTOR_WRAPPER (WRAPPER_NAME (exp), _ZGVeN8v_exp) +VECTOR_WRAPPER_ff (WRAPPER_NAME (pow), _ZGVeN8vv_pow) + +#ifndef __ILP32__ +# define VEC_INT_TYPE __m512i +#else +# define VEC_INT_TYPE __m256i +#endif + +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincos), _ZGVeN8vvv_sincos) diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8.h b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8.h new file mode 100644 index 0000000000..5802abc121 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-double-vlen8.h @@ -0,0 +1,21 @@ +/* Tests for AVX-512 versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include_next <test-double-vlen8.h> + +#define REQUIRE_AVX512F diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-main.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-mod.c new file mode 100644 index 0000000000..7fc3d8aedd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx-mod.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-main.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-mod.c new file mode 100644 index 0000000000..7fc3d8aedd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2-mod.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx2.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-main.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-mod.c new file mode 100644 index 0000000000..7fc3d8aedd --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512-mod.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-avx512.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-main.c new file mode 100644 index 0000000000..f3691cc8e6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-alias.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-mod.c new file mode 100644 index 0000000000..109307f997 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias-mod.c @@ -0,0 +1,25 @@ +/* Part of test to build shared library to ensure link against + *_finite aliases from libmvec. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> +#include <stdlib.h> +#include <math-tests-arch.h> + +#include "test-float.h" +#include "test-libmvec-alias-mod.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias.c new file mode 100644 index 0000000000..c7048d346f --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-alias.c @@ -0,0 +1,29 @@ +/* Part of test to ensure link against *_finite aliases from libmvec. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +extern int +test_finite_alias (void); + +static int +do_test (void) +{ + return test_finite_alias (); +} + +#define TEST_FUNCTION do_test () +#include "../../../test-skeleton.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx-main.c new file mode 100644 index 0000000000..558e2ac649 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx.c new file mode 100644 index 0000000000..5b45f0a055 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2-main.c new file mode 100644 index 0000000000..558e2ac649 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2.c new file mode 100644 index 0000000000..5b45f0a055 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512-main.c new file mode 100644 index 0000000000..558e2ac649 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512-main.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf-main.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512.c new file mode 100644 index 0000000000..5b45f0a055 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512.c @@ -0,0 +1 @@ +#include "test-float-libmvec-sincosf.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-main.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-main.c new file mode 100644 index 0000000000..5dd1efa8f9 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf-main.c @@ -0,0 +1,42 @@ +/* Test for vector sincosf ABI. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define N 1000 +float x[N], s[N], c[N]; +float *s_ptrs[N]; +float *c_ptrs[N]; + +int +test_sincosf_abi (void) +{ + int i; + for(i = 0; i < N; i++) + { + x[i] = i / 3; + s_ptrs[i] = &s[i]; + c_ptrs[i] = &c[i]; + } + +#pragma omp simd + for(i = 0; i < N; i++) + sincosf (x[i], s_ptrs[i], c_ptrs[i]); + + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c new file mode 100644 index 0000000000..79543f5cb0 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c @@ -0,0 +1,44 @@ +/* Test for vector sincosf ABI. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math-tests-arch.h> + +extern int test_sincosf_abi (void); + +int arch_check = 1; + +static void +check_arch (void) +{ + CHECK_ARCH_EXT; + arch_check = 0; +} + +static int +do_test (void) +{ + check_arch (); + + if (arch_check) + return 77; + + return test_sincosf_abi (); +} + +#define TEST_FUNCTION do_test () +#include "../../../test-skeleton.c" diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c new file mode 100644 index 0000000000..2e729e2770 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c @@ -0,0 +1,37 @@ +/* Wrapper part of tests for AVX-512 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-float-vlen16.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m512 + +VECTOR_WRAPPER (WRAPPER_NAME (cosf), _ZGVeN16v_cosf) +VECTOR_WRAPPER (WRAPPER_NAME (sinf), _ZGVeN16v_sinf) +VECTOR_WRAPPER (WRAPPER_NAME (logf), _ZGVeN16v_logf) +VECTOR_WRAPPER (WRAPPER_NAME (expf), _ZGVeN16v_expf) +VECTOR_WRAPPER_ff (WRAPPER_NAME (powf), _ZGVeN16vv_powf) + +#define VEC_INT_TYPE __m512i + +#ifndef __ILP32__ +VECTOR_WRAPPER_fFF_3 (WRAPPER_NAME (sincosf), _ZGVeN16vvv_sincosf) +#else +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincosf), _ZGVeN16vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16.h b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16.h new file mode 100644 index 0000000000..b2bfbf5371 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen16.h @@ -0,0 +1,21 @@ +/* Tests for AVX-512 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include_next <test-float-vlen16.h> + +#define REQUIRE_AVX512F diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c new file mode 100644 index 0000000000..a332a65236 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c @@ -0,0 +1,37 @@ +/* Wrapper part of tests for SSE ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-float-vlen4.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m128 + +VECTOR_WRAPPER (WRAPPER_NAME (cosf), _ZGVbN4v_cosf) +VECTOR_WRAPPER (WRAPPER_NAME (sinf), _ZGVbN4v_sinf) +VECTOR_WRAPPER (WRAPPER_NAME (logf), _ZGVbN4v_logf) +VECTOR_WRAPPER (WRAPPER_NAME (expf), _ZGVbN4v_expf) +VECTOR_WRAPPER_ff (WRAPPER_NAME (powf), _ZGVbN4vv_powf) + +#define VEC_INT_TYPE __m128i + +#ifndef __ILP32__ +VECTOR_WRAPPER_fFF_3 (WRAPPER_NAME (sincosf), _ZGVbN4vvv_sincosf) +#else +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincosf), _ZGVbN4vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c new file mode 100644 index 0000000000..511f9342a6 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c @@ -0,0 +1,43 @@ +/* Wrapper part of tests for AVX2 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-float-vlen8.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#undef VEC_SUFF +#define VEC_SUFF _vlen8_avx2 + +#define VEC_TYPE __m256 + +VECTOR_WRAPPER (WRAPPER_NAME (cosf), _ZGVdN8v_cosf) +VECTOR_WRAPPER (WRAPPER_NAME (sinf), _ZGVdN8v_sinf) +VECTOR_WRAPPER (WRAPPER_NAME (logf), _ZGVdN8v_logf) +VECTOR_WRAPPER (WRAPPER_NAME (expf), _ZGVdN8v_expf) +VECTOR_WRAPPER_ff (WRAPPER_NAME (powf), _ZGVdN8vv_powf) + +/* Redefinition of wrapper to be compatible with _ZGVdN8vvv_sincosf. */ +#undef VECTOR_WRAPPER_fFF + +#define VEC_INT_TYPE __m256i + +#ifndef __ILP32__ +VECTOR_WRAPPER_fFF_3 (WRAPPER_NAME (sincosf), _ZGVdN8vvv_sincosf) +#else +VECTOR_WRAPPER_fFF_2 (WRAPPER_NAME (sincosf), _ZGVdN8vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2.h b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2.h new file mode 100644 index 0000000000..4967f9d19b --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-avx2.h @@ -0,0 +1,25 @@ +/* Tests for AVX2 ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <test-float-vlen8.h> + +#undef VEC_SUFF +#define VEC_SUFF _vlen8_avx2 + +#undef REQUIRE_AVX +#define REQUIRE_AVX2 diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c new file mode 100644 index 0000000000..5a3581b0c8 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c @@ -0,0 +1,37 @@ +/* Wrapper part of tests for AVX ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "test-float-vlen8.h" +#include "test-math-vector-sincos.h" +#include <immintrin.h> + +#define VEC_TYPE __m256 + +VECTOR_WRAPPER (WRAPPER_NAME (cosf), _ZGVcN8v_cosf) +VECTOR_WRAPPER (WRAPPER_NAME (sinf), _ZGVcN8v_sinf) +VECTOR_WRAPPER (WRAPPER_NAME (logf), _ZGVcN8v_logf) +VECTOR_WRAPPER (WRAPPER_NAME (expf), _ZGVcN8v_expf) +VECTOR_WRAPPER_ff (WRAPPER_NAME (powf), _ZGVcN8vv_powf) + +#define VEC_INT_TYPE __m128i + +#ifndef __ILP32__ +VECTOR_WRAPPER_fFF_4 (WRAPPER_NAME (sincosf), _ZGVcN8vvv_sincosf) +#else +VECTOR_WRAPPER_fFF_3 (WRAPPER_NAME (sincosf), _ZGVcN8vvv_sincosf) +#endif diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8.h b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8.h new file mode 100644 index 0000000000..23ef71c6c5 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-float-vlen8.h @@ -0,0 +1,21 @@ +/* Tests for AVX ISA versions of vector math functions. + Copyright (C) 2014-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include_next <test-float-vlen8.h> + +#define REQUIRE_AVX diff --git a/REORG.TODO/sysdeps/x86_64/fpu/test-libmvec-alias-mod.c b/REORG.TODO/sysdeps/x86_64/fpu/test-libmvec-alias-mod.c new file mode 100644 index 0000000000..9746b0ae1c --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/test-libmvec-alias-mod.c @@ -0,0 +1,66 @@ +/* Part of test to build shared library to ensure link against + *_finite aliases from libmvec. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define N 4000 +FLOAT log_arg[N]; +FLOAT exp_arg[N]; +FLOAT log_res[N]; +FLOAT exp_res[N]; +FLOAT pow_res[N]; +int arch_check = 1; + +static void +init_arg (void) +{ + int i; + + CHECK_ARCH_EXT; + + arch_check = 0; + + for (i = 0; i < N; i += 1) + { + log_arg[i] = 1.0; + exp_arg[i] = 0.0; + } +} + +int +test_finite_alias (void) +{ + int i; + + init_arg (); + + if (arch_check) return 77; + +#pragma omp simd + for (i = 0; i < N; i += 1) + { + log_res[i] = FUNC (log) (log_arg[i]); + exp_res[i] = FUNC (exp) (exp_arg[i]); + pow_res[i] = FUNC (pow) (log_arg[i], log_arg[i]); + } + + if (log_res[0] != 0.0) return 1; + if (exp_res[0] != 1.0) return 1; + if (pow_res[0] != 1.0) return 1; + + return 0; +} diff --git a/REORG.TODO/sysdeps/x86_64/fpu/x86_64-math-asm.h b/REORG.TODO/sysdeps/x86_64/fpu/x86_64-math-asm.h new file mode 100644 index 0000000000..4b4e40c3e7 --- /dev/null +++ b/REORG.TODO/sysdeps/x86_64/fpu/x86_64-math-asm.h @@ -0,0 +1,74 @@ +/* Helper macros for x86_64 libm functions. + Copyright (C) 2015-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _X86_64_MATH_ASM_H +#define _X86_64_MATH_ASM_H 1 + +/* Define constants for the minimum value of a floating-point + type. */ +#define DEFINE_LDBL_MIN \ + .section .rodata.cst16,"aM",@progbits,16; \ + .p2align 4; \ + .type ldbl_min,@object; \ +ldbl_min: \ + .byte 0, 0, 0, 0, 0, 0, 0, 0x80, 0x1, 0; \ + .byte 0, 0, 0, 0, 0, 0; \ + .size ldbl_min, .-ldbl_min; + +/* Force an underflow exception if the given value (nonnegative or + NaN) is subnormal. The relevant constant for the minimum of the + type must have been defined, the MO macro must have been defined + for access to memory operands, and, if PIC, the PIC register must + have been loaded. */ +#define LDBL_CHECK_FORCE_UFLOW_NONNEG_NAN \ + fldt MO(ldbl_min); \ + fld %st(1); \ + fucomip %st(1), %st(0); \ + fstp %st(0); \ + jnc 6464f; \ + fld %st(0); \ + fmul %st(0); \ + fstp %st(0); \ +6464: + +/* Likewise, but the argument is not a NaN. */ +#define LDBL_CHECK_FORCE_UFLOW_NONNAN \ + fldt MO(ldbl_min); \ + fld %st(1); \ + fabs; \ + fcomip %st(1), %st(0); \ + fstp %st(0); \ + jnc 6464f; \ + fld %st(0); \ + fmul %st(0); \ + fstp %st(0); \ +6464: + +/* Likewise, but the argument is nonnegative and not a NaN. */ +#define LDBL_CHECK_FORCE_UFLOW_NONNEG \ + fldt MO(ldbl_min); \ + fld %st(1); \ + fcomip %st(1), %st(0); \ + fstp %st(0); \ + jnc 6464f; \ + fld %st(0); \ + fmul %st(0); \ + fstp %st(0); \ +6464: + +#endif /* x86_64-math-asm.h. */ |