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| author | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2015-01-07 11:31:10 +0000 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2015-01-07 11:31:10 +0000 |
| commit | dc400d7b735c47086a001ed051723e376230cf01 (patch) | |
| tree | f4a14f3ef9ed50d2b9da4302c4a3b1042fcf9ee6 /NEWS | |
| parent | ec582ca0f30c963a1c27f405b6732ca8507271d5 (diff) | |
| download | glibc-dc400d7b735c47086a001ed051723e376230cf01.tar glibc-dc400d7b735c47086a001ed051723e376230cf01.tar.gz glibc-dc400d7b735c47086a001ed051723e376230cf01.tar.bz2 glibc-dc400d7b735c47086a001ed051723e376230cf01.zip | |
AArch64: Optimized implementations of strcpy and stpcpy.
Diffstat (limited to 'NEWS')
| -rw-r--r-- | NEWS | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -19,8 +19,8 @@ Version 2.21 17744, 17745, 17746, 17747, 17775, 17777, 17780, 17781, 17782, 17793, 17796, 17797, 17806 -* Optimized strchrnul and strrchr implementations for AArch64. - Contributed by ARM Ltd. +* Optimized strcpy, stpcpy, strchrnul and strrchr implementations for + AArch64. Contributed by ARM Ltd. * i386 memcpy functions optimized with SSE2 unaligned load/store. |