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| author | David S. Miller <davem@davemloft.net> | 2012-06-01 13:32:04 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-06-01 13:33:28 -0700 |
| commit | 402fe938f60c1f10700c8d0b673bf4a6dc2d1d40 (patch) | |
| tree | f67f8e6827d563eb2df8cd64f4e522b02dbe1c37 | |
| parent | 3bd872c4c481664542c6c5797730f3830e827b92 (diff) | |
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Update longlong.h from GCC to get some sparc improvements.
* stdlib/longlong.h: Updated from GCC.
| -rw-r--r-- | ChangeLog | 4 | ||||
| -rw-r--r-- | stdlib/longlong.h | 80 |
2 files changed, 59 insertions, 25 deletions
@@ -1,3 +1,7 @@ +2012-06-01 David S. Miller <davem@davemloft.net> + + * stdlib/longlong.h: Updated from GCC. + 2012-06-01 H.J. Lu <hongjiu.lu@intel.com> [BZ #14117] diff --git a/stdlib/longlong.h b/stdlib/longlong.h index 4fa9d46832..ad42907f54 100644 --- a/stdlib/longlong.h +++ b/stdlib/longlong.h @@ -1127,6 +1127,29 @@ UDItype __umulsidi3 (USItype, USItype); "rJ" ((USItype) (al)), \ "rI" ((USItype) (bl)) \ __CLOBBER_CC) +#if defined (__sparc_v9__) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + register USItype __g1 asm ("g1"); \ + __asm__ ("umul\t%2,%3,%1\n\t" \ + "srlx\t%1, 32, %0" \ + : "=r" ((USItype) (w1)), \ + "=r" (__g1) \ + : "r" ((USItype) (u)), \ + "r" ((USItype) (v))); \ + (w0) = __g1; \ + } while (0) +#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ + __asm__ ("mov\t%2,%%y\n\t" \ + "udiv\t%3,%4,%0\n\t" \ + "umul\t%0,%4,%1\n\t" \ + "sub\t%3,%1,%1" \ + : "=&r" ((USItype) (__q)), \ + "=&r" ((USItype) (__r)) \ + : "r" ((USItype) (__n1)), \ + "r" ((USItype) (__n0)), \ + "r" ((USItype) (__d))) +#else #if defined (__sparc_v8__) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("umul %2,%3,%1;rd %%y,%0" \ @@ -1292,37 +1315,44 @@ UDItype __umulsidi3 (USItype, USItype); #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ #endif /* __sparclite__ */ #endif /* __sparc_v8__ */ +#endif /* __sparc_v9__ */ #endif /* sparc32 */ #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ && W_TYPE_SIZE == 64 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ - __asm__ ("addcc %r4,%5,%1\n\t" \ - "add %r2,%3,%0\n\t" \ - "bcs,a,pn %%xcc, 1f\n\t" \ - "add %0, 1, %0\n" \ - "1:" \ - : "=r" ((UDItype)(sh)), \ - "=&r" ((UDItype)(sl)) \ - : "%rJ" ((UDItype)(ah)), \ - "rI" ((UDItype)(bh)), \ - "%rJ" ((UDItype)(al)), \ - "rI" ((UDItype)(bl)) \ - __CLOBBER_CC) + do { \ + UDItype __carry = 0; \ + __asm__ ("addcc\t%r5,%6,%1\n\t" \ + "add\t%r3,%4,%0\n\t" \ + "movcs\t%%xcc, 1, %2\n\t" \ + "add\t%0, %2, %0" \ + : "=r" ((UDItype)(sh)), \ + "=&r" ((UDItype)(sl)), \ + "+r" (__carry) \ + : "%rJ" ((UDItype)(ah)), \ + "rI" ((UDItype)(bh)), \ + "%rJ" ((UDItype)(al)), \ + "rI" ((UDItype)(bl)) \ + __CLOBBER_CC); \ + } while (0) -#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ - __asm__ ("subcc %r4,%5,%1\n\t" \ - "sub %r2,%3,%0\n\t" \ - "bcs,a,pn %%xcc, 1f\n\t" \ - "sub %0, 1, %0\n\t" \ - "1:" \ - : "=r" ((UDItype)(sh)), \ - "=&r" ((UDItype)(sl)) \ - : "rJ" ((UDItype)(ah)), \ - "rI" ((UDItype)(bh)), \ - "rJ" ((UDItype)(al)), \ - "rI" ((UDItype)(bl)) \ - __CLOBBER_CC) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + do { \ + UDItype __carry = 0; \ + __asm__ ("subcc\t%r5,%6,%1\n\t" \ + "sub\t%r3,%4,%0\n\t" \ + "movcs\t%%xcc, 1, %2\n\t" \ + "add\t%0, %2, %0" \ + : "=r" ((UDItype)(sh)), \ + "=&r" ((UDItype)(sl)), \ + "+r" (__carry) \ + : "%rJ" ((UDItype)(ah)), \ + "rI" ((UDItype)(bh)), \ + "%rJ" ((UDItype)(al)), \ + "rI" ((UDItype)(bl)) \ + __CLOBBER_CC); \ + } while (0) #define umul_ppmm(wh, wl, u, v) \ do { \ |