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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-05-19 10:02:36 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-06-06 13:22:08 -0700 |
| commit | 07f943915311f6f92e5a031911d32c5e7458bfd5 (patch) | |
| tree | 95c4fa21b06e753fbbba12c41c87ac16c5066eb5 | |
| parent | 201aebf739482fbb730d10eb7cf8335629bb4de4 (diff) | |
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Correct Intel processor level type mask from CPUID
Intel CPUID with EAX == 11 returns:
ECX Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type.
^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
Bits 31 - 16: Reserved.
Intel processor level type mask should be 0xff00, not 0xff0.
[BZ #20119]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
processor level type mask for CPUID with EAX == 11.
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 5c4c616f18..c591d01591 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -552,7 +552,7 @@ init_cacheinfo (void) __cpuid_count (11, i++, eax, ebx, ecx, edx); int shipped = ebx & 0xff; - int type = ecx & 0xff0; + int type = ecx & 0xff00; if (shipped == 0 || type == 0) break; else if (type == 0x200) |