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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-08-06 00:13:45 -0400 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-08-28 13:52:17 -0500 |
| commit | fec2bd2c2d31bc731cf61623e150d047746954bd (patch) | |
| tree | 08a770e031939d3c1b4bed81b88ed7a0071ba456 | |
| parent | e905212627350d54b58426214b5a54ddc852b0c9 (diff) | |
| download | glibc-fec2bd2c2d31bc731cf61623e150d047746954bd.tar glibc-fec2bd2c2d31bc731cf61623e150d047746954bd.tar.gz glibc-fec2bd2c2d31bc731cf61623e150d047746954bd.tar.bz2 glibc-fec2bd2c2d31bc731cf61623e150d047746954bd.zip | |
[powerpc] fesetenv: optimize FPSCR access
fesetenv() reads the current value of the Floating-Point Status and Control
Register (FPSCR) to determine the difference between the current state of
exception enables and the newly requested state. All of these bits are also
returned by the lighter weight 'mffsl' instruction used by fegetenv_status().
Use that instead.
Also, remove a local macro _FPU_MASK_ALL in favor of a common macro,
FPU_ENABLES_MASK from fenv_libc.h.
Finally, use a local variable ('new') in favor of a pointer dereference
('*envp').
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 12 |
2 files changed, 10 insertions, 8 deletions
@@ -1,5 +1,11 @@ 2019-08-28 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Utilize lightweight + FPSCR read. + (_FPU_MASK_ALL): Delete. + +2019-08-28 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_private.h (libc_feholdsetround_ppc_ctx): Utilize lightweight FPSCR read if possible, set fewer FPSCR bits if possible. diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 009a4f025e..5ca15c7c07 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -19,8 +19,6 @@ #include <fenv_libc.h> #include <fpu_control.h> -#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM) - int __fesetenv (const fenv_t *envp) { @@ -28,25 +26,23 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; - old.fenv = fegetenv_register (); - if (old.l == new.l) - return 0; + old.fenv = fegetenv_status (); /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ - if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) + if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0) (void) __fe_nomask_env_priv (); /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) + if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0) (void)__fe_mask_env (); - fesetenv_register (*envp); + fesetenv_register (new.fenv); /* Success. */ return 0; |