diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2016-05-20 14:41:14 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-05-20 14:42:00 -0700 |
| commit | b7598b1b855b39628104feb9a1f6151a86351a64 (patch) | |
| tree | a59690d12b5a09273bafd6cede80a75514c44816 | |
| parent | b003c666efc6c25908a36bcabee87a2bf1c49a09 (diff) | |
| download | glibc-b7598b1b855b39628104feb9a1f6151a86351a64.tar glibc-b7598b1b855b39628104feb9a1f6151a86351a64.tar.gz glibc-b7598b1b855b39628104feb9a1f6151a86351a64.tar.bz2 glibc-b7598b1b855b39628104feb9a1f6151a86351a64.zip | |
Remove special L2 cache case for Knights Landing
L2 cache is shared by 2 cores on Knights Landing, which has 4 threads
per core:
https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing
So L2 cache is shared by 8 threads on Knights Landing as reported by
CPUID. We should remove special L2 cache case for Knights Landing.
[BZ #18185]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads
sharing L2 cache to 2 for Knights Landing.
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 2 |
2 files changed, 6 insertions, 2 deletions
@@ -1,3 +1,9 @@ +2016-05-20 H.J. Lu <hongjiu.lu@intel.com> + + [BZ #18185] + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads + sharing L2 cache to 2 for Knights Landing. + 2016-05-20 Joseph Myers <joseph@codesourcery.com> * conform/data/ftw.h-data (struct FTW): Do not expect for [XPG3]. diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 020d3fd397..182426b2d0 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -573,8 +573,6 @@ init_cacheinfo (void) { switch (model) { - case 0x57: - /* Knights Landing has L2 cache shared by 2 cores. */ case 0x37: case 0x4a: case 0x4d: |